Patent Application
20220013481
Recently, as a structure of semiconductor devices has become finer and more highly integrated, an importance of low-resistivity wiring has been increasing. Along with it, Cu (copper), which has a relatively low resistance, is adapted to be often used as a wiring material. Further, a so-called Low-k film (k<3.0) having a low dielectric constant k is often used as an interlayer insulating film. On the other hand, a pad electrode is usually formed simultaneously with a top layer metallic wiring. Then, a bonding wire is connected to the pad electrode. Specifically, by a method such as ultrasonic or thermocompression bonding to the pad electrode, a gold (Au) wire or a copper (Cu) wire is bonded.
Here, a load or an impact force applied during wire bonding deforms the pad electrode and is directly transmitted to a surface protective film around the pad electrode and the interlayer insulating film. Then, there is a problem that cracks occur in the surface protective film and the interlayer insulating film. Since the surface protective film around the pad electrode includes a film having a relatively low fracture toughness, the cracks tend to occur in the surface protective film. Further, since a mechanical strength is about one order of magnitude lower than a silicon oxide film (SiO2) when the interlayer insulating film is a Low-k film, the cracks tend to occur in the interlayer insulating film. Furthermore, if the bonding wire is the copper (Cu) wire, the impact force applied during wire bonding is increased. A reason is that the copper (Cu) wire has higher hardness than the gold (Au) wire. As a result, in the case of the copper (Cu) wire, the cracks occur in the surface protective film around the pad electrode and the interlayer insulating film becomes more remarkable.
JP-A-2018-74063 (Patent Document 1) discloses a technique for absorbing a bonding impact by forming a plurality of voids in the pad electrode made of aluminum. However, in the technique described in Patent Document 1, a region where the plurality of voids are not formed, that is, an around of an upper surface of the pad electrode, or the portion where the voids are not formed between the upper surface of the pad electrode and the interlayer insulating film. It may not be able to fully absorb a deformation of the pad electrode. As a result, the load or the impact force applied at the time of wire bonding in these locations is directly transmitted to the protective surface film and the interlayer insulating film around the pad electrode, there is a possibility that the cracks occur in the protective surface film and the interlayer insulating film. Therefore, semiconductor device described in Patent Document 1 can be improved from the viewpoint of preventing the cracks in the protective surface film and the interlayer insulating film at the time of wire bonding.
The problem of present embodiments, it is to prevent the cracks in the surface protective film and the interlayer insulating film around the pad electrode at the time of wire bonding.
According to embodiments, in the pad electrode, a groove is formed between an inner peripheral edge of an opening of the pad electrode and an outer peripheral edge of a bonding area, and the groove penetrates a part of the pad electrode.
According to the embodiments, it is possible to prevent the cracks in the surface protective film and the interlayer insulating film around the pad electrode. As the result, it is possible to improve a reliability of the semiconductor device.
Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.
In the following embodiments, where it is necessary for convenience, they shall be explained by dividing them into multiple sections or embodiments, but they shall not be related to each other unless otherwise explicitly indicated. In the following embodiments, reference to the number of elements or the like (including the number, numerical value, quantity, range, and the like) is not limited to the specific number, and may be greater than or equal to the specific number or less, except in the case where it is specifically specified and the case where it is obviously limited to the specific number in principle.
Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are specifically specified and the case where they are considered to be obviously essential in principle. Similarly, in the following embodiments, reference to shapes, positional relationships, and the like of constituent elements and the like includes substantially approximate or similar shapes and the like, except for the case in which they are specifically specified and the case in which they are considered to be obvious in principle and the like. The same applies to the above-mentioned numbers and the like, including the number, the numerical value, the amount, the range, and the like.
In all the drawings for explaining the embodiments, members having the same function are denoted by the same or related reference numerals, and repetitive description thereof is omitted. In addition, when there are a plurality of similar members (portions), symbols may be added to the generic term reference numerals to indicate individual or specific portions. In the following embodiments, descriptions of the same or similar parts will not be repeated in principle except when particularly necessary.
In the drawings used in the embodiments, hatching may be omitted even in the case of cross-sectional view in order to make the drawings easier to see. In addition, even plan view may be hatched to make the drawings easier to understand. Also, in cross-sectional view and plan view, the size of each part does not correspond to the actual device. In addition, in some cases, a specific site is displayed relatively large for clarity of the drawings. In addition, even when cross-sectional view and plan view correspond to each other, a particular portion may be displayed relatively large in order to make the drawing easy to understand.
(Structure)
As shown in
The structure of a third wiring M3 and its upper layer in the first embodiment will be described with reference to
The conductive film AL is made of, for example, a material containing aluminum as a main component. Specifically, it is made of an aluminum film, or an aluminum-alloy film (Al—Si film, Al—Si—Cu film, or the like). A thickness of the conductive film AL is about 1.5 μm to 9.5 μm.
The first barrier metal film BM1 and the second barrier metal film BM2 are made of, for example, a material containing titanium nitride as a main component. Specifically, it is formed of a titanium nitride film or a laminated film of the titanium nitride film and a titanium film. A thickness of each of the first barrier metal film BM1 and the second barrier metal film BM2 are about 100 nm to 300 nm.
Here, the second barrier metal film BM2 can be omitted from the laminated film constituting the pad electrode PAD. Since the second barrier metal film BM2 is removed from the bonding region BAR, a function of the bonding region BAR as the pad electrode PAD is not affected even if the second barrier metal film BM2 is not formed in the bonding region BAR.
On the interlayer insulating film IL4, the laminated film in which the first surface protective film IF1 and the second surface protective film IF2 are laminated in this order is formed so as to cover the pad electrode PAD.
A first protective film IF1 is made of, for example, the silicon oxide film or a silicon nitride film. The second surface protective film IF2 is made of, for example, an organic resin film such as a polyimide film. The first protective film IF1 may be a silicon oxynitride film or a silicon oxycarbide film. The second surface protective film IF2 may be the silicon nitride film in addition to the silicon nitride film.
However, since the first surface protective film IF1 is embedded between a plurality of pad electrodes PAD, it is preferable to apply a forming method and a material having good embeddability. The silicon oxide film formed by HDP-CVD (High-Density Plasma Chemical Vapor Deposition) method has an advantage of good embeddability. On the other hand, since the second surface protective film IF2 functions as a passivating film for protecting a surface of the semiconductor device SD, it is preferable to apply a material having a high step coverage. The polyimide film has an advantage of good function as passivation film due to their high step coverage performance. Note that, in the first embodiment, a configuration in which the surface protective film is the laminated film of two layers has been described, but a configuration of a single layer may be used, and a configuration of three or more layers may be used.
A thickness of the first protective film IF1 is about 300 nm to 2 μm. And a thickness of the second surface protective film IF2 is about 2 μm to 5 μm.
The laminated film composed of the first surface protective film IF1 and the second surface protective film IF2 has the opening OP which is partially exposed on the pad electrode PAD. That is, the opening OP has reached the upper surface of the pad electrode PAD through the laminated film. More specifically, the opening OP has reached an upper surface of the conductive film AL of the pad electrode PAD through the laminated film and the second barrier metal film BM2. On the other hand, an end portion of the pad electrode PAD is covered with the laminated film.
An upper surface of the pad electrode PAD in the opening OP, that is, the upper surface of the conductive film AL has the bonding region BAR which is an area for bonding the bonding wire BW.
The conductive film AL is exposed in the bonding region BAR. In other words, the second barrier metal film BM2 of the pad electrode PAD is removed from the pad electrode PAD in the bonding region BAR. Then, the bonding wire BW (not shown) is connected to the bonding region BAR.
In order to improve a reliability of the junction between the bonding wire BW and the pad electrode PAD, a palladium (Pd) layer, a gold (Au) layer, or a nickel (Ni) layer may be provided between the bonding wire BW and the upper surface of the pad electrode PAD (the upper surface of the conductive film AL).
As shown in
(Manufacturing Method of the Semiconductor Device According to the First Embodiment)
Next, an exemplary manufacturing method of the semiconductor device SD according to the first embodiment will be described.
First, as shown in
Subsequently, after introducing impurities into the semiconductor substrate SUB to form well (not shown), a MISFETQ1 and a MISFETQ2 comprising a gate electrode formed on the well (not shown) through a gate dielectric film and a source-drain region formed in the well (not shown), respectively.
Subsequently, as shown in
Subsequently, as shown in
Subsequently, as shown in
Thereafter, by repeating the same process, an interlayer insulating film IL3, a plug (via) V2, and the third wiring M3 are formed. As a result, the multilayer wiring structure shown in
Next, as shown in
Subsequently, the plug (via) V3 is formed by embedding, for example, a barrier conductor film containing titanium (Ti) or titanium nitride (TiN), and for example, a main conductor film made of tungsten (W). The plug (via) V3 is connected to an upper surface of the third wiring M3.
Subsequently, the first barrier metal film BM1, the conductive film AL, and the second barrier metal film BM2 are sequentially stacked by a CVD method or a sputtering method.
Next, as shown in
Subsequently, by performing a dry etching process using the photoresist pattern PR1 as a mask, the second barrier metal film BM2, the conductive film AL and the first barrier metal film BM1 are sequentially removed. Thus, the interlayer insulating film IL4 other than the region where the pad electrode PAD is formed is exposed. As a result, the pad electrode PAD is formed.
Next, after the photoresist pattern PR1 is removed by ashing, the first surface protective film IF1 is formed on the interlayer insulating film IL4 so as to cover the pad electrode PAD. The first surface protective film IF1 is an insulating film formed by using, for example, the HDP-CVD method, and is made of, for example, the silicon oxide film or the silicon nitride film.
Next, as shown in
Subsequently, by performing a dry etching process using the photoresist pattern PR2 as a mask, the first surface protective film IF1, the second barrier metal film BM2 and a part of the conductive film AL are sequentially removed. At this time, a groove formed by the dry etching process penetrates the first surface protective film IF1 and the second barrier metal film BM2, but does not penetrate the conductive film AL. That is, the dry etching process is finished in a middle of the conductive film AL.
Next, after the photoresist pattern PR2 is removed by ashing, the second surface protective film IF2 is formed on the first surface protective film IF1 so as to cover the pad electrode PAD. The second surface protective film IF2 is made of, for example, the organic resin film such as the polyimide film. The polyimide film is formed, for example, by spin coating a photosensitive polyimide precursor solution and drying them. The polyimide film on the pad electrode PAD is partially removed by exposing and developing the polyimide film. And a heat treatment is performed to cure the polyimide film. As the result, the opening OP is formed.
Subsequently, by performing a dry etching process using the second surface protective film IF2 as a mask, the first surface protective film IF1 and the second barrier metal film BM2 in the opening OP, the conductive film AL in the groove GR are removed. By the dry etching process, the conductive film AL is exposed in the opening OP, penetrates the conductive film AL and exposes the upper surface of the first barrier metal film BM1 in the groove GR. At this time, a part of the first barrier metal film BM1 may be removed by over etching in the groove GR. Incidentally, in the opening OP, a region where the conductive film AL is exposed becomes the bonding region BAR.
Through the above steps, the structure shown in
After that, in post process steps, the semiconductor substrate SUB is divided a plurality of the semiconductor chips CHP by dicing or the like, and then, arranged on the die pad DP of a lead frame. after that, the pad electrode PAD and one end of the lead LD is connected by the bonding wire BW. Next, sealing body MR is formed so as to cover the semiconductor chip CHP and the bonding wire BW. The sealing body MR is made of, for example, an epoxy resin, and contains, for example, a reactant of a silane coupling agent.
Through the above steps, the semiconductor device SD of the first embodiment is manufactured.
(Effects of the First Embodiment)
The periphery of the pad electrode PAD is covered with the first surface protective film IF1. The first protective film IF1 is, for example, the silicon oxide film or the silicon nitride film. These films have low fracture toughness, for this reason, when the load or the impact applied at the time of wire bonding is directly transmitted to the first surface protective film IF1, there is a problem that cracks occur in the first surface protective film IF1. In particular, a portion of the first surface protective film IF1 covering an end portion of the pad electrode PAD is easily cracked. This is because a thickness of the portion of the first surface protective film IF1 is locally thin.
Here, it can be considered that the groove GR is formed in the pad electrode PAD outside the inner peripheral edge of the opening OP, that is, in the region where the pad electrode PAD is covered with the first surface protective film IF1. However, in this case, the bonding region BAR and the first surface protective film IF1 are in contact with each other. Therefore, the load or the impact applied during wire bonding is directly transmitted to the first surface protective film IF1. As the results, the cracks occur in the portion of the first surface protective film IF1 covering the end portion of the pad electrode PAD.
For the above reason, it is preferable to form the groove GR between the inner peripheral edge of the opening OP and the outer peripheral edge of the bonding region BAR. In this structure, it is possible to block the impact applied during wire bonding to the end portion of the pad electrode PAD. Then, it is possible to prevent the impact from being transmitted to the first surface protective film IF1.
The impact applied during wire bonding is transmitted to the interlayer insulating film IL3 via the interlayer insulating film IL4 and the plug (via) V3 which are in contact with a bottom of the pad electrode PAD. However, by forming the groove GR so as to surround a periphery of the bonding region BAR along the inner peripheral edge of the opening OP, side surfaces of the conductive film AL are released by the groove GR. As a result, the conductive film AL has a structure that can be elastically deformed in a horizontal direction. It is possible to reduce the transmission of the impact in a thickness direction of the conductive film AL by absorbing the impact applied at the time of wire bonding by elastic deformation.
Also, in this case, the groove GR is preferably formed between the inner peripheral edge of the opening OP and the outer peripheral edge of the bonding region BAR. This is because the groove GR is not covered with the first surface protective film IF1 and the side surfaces of the conductive film AL is completely opened.
Hereinafter, the semiconductor device according to a second embodiment will be described with reference to
As shown in
In the second embodiment, a depth of the groove GR is, for example, about ½ to ⅔ of a film thickness of the conductive film AL. The remaining of the conductive film AL is not divided by the groove GR, it is connected.
(Manufacturing Method of the Semiconductor Device According to the Second Embodiment)
Manufacturing method of the semiconductor device according to the second embodiment is similar as manufacturing method of semiconductor device for the first embodiment. However, manufacturing method of the second embodiment is different from manufacturing method of the first embodiment in that it does not penetrate the conductive film AL and does not expose the upper surface of the first barrier metal film BM1 when dry etching is performed using the second surface protective film IF2 as a mask.
(Effects of the Second Embodiment)
The impact applied to the end portion of the pad electrode PAD during wire bonding is transmitted by elastically deforming the conductive film AL in the horizontal direction. Then, the impact is transmitted mainly through a vicinity of the upper surface of the conductive film AL. Therefore, even in a structure that does not penetrate the conductive film AL as in the groove GR of the second embodiment, the groove GR has a function of blocking the impact applied to the end portion of the pad electrode PAD.
And a part of the side surfaces of the conductive film AL are released by the groove GR. Thus, the conductive film AL has a structure that can be elastically deformed in the horizontal direction. Therefore, also in the second embodiment, by absorbing the impact applied during wire bonding by elastic deformation, it is possible to reduce the transmission of the impact in the thickness direction of the conductive film AL.
Furthermore, since the groove GR of the second embodiment has the structure that does not penetrate the conductive film AL, the conductive film AL is not divided by the groove GR. That is, a bottom surface of the conductive film AL and the upper surface of the first barrier metal film BM1 are connected to face each other over the entire surface of the pad electrode PAD. With this structure, it is possible to prevent the pad electrode PAD from peeling at the interface between the bottom surface of the conductive film AL and the upper surface of the first barrier metal film BM1 when the conductive film AL elastically deforms during wire bonding.
Hereinafter, the semiconductor device according to a third embodiment will be described with reference to
As shown in
That is, the plurality of grooves GR of the third embodiment extends in the first direction extending along the outer peripheral edge of the bonding region BAR and are arranged at the predetermined interval in the second direction perpendicular to the first direction.
Here, in the third embodiment, an example is shown in which the plurality of grooves GR are formed for each of four sides of the opening OP, but a structure is not limited to this, and for example, the plurality of grooves GR may be formed one for each of the four sides of the opening OP and may not be connected at each corner of the opening OP.
Hereinafter, the semiconductor device according to a fourth embodiment will be described with reference to
As shown in
That is, the groove GR of the fourth embodiment is formed in triangles in the corner of the opening OP. The triangle region defined two adjacent sides of the inner peripheral edge of the opening OP each other and a traversed imaginary line traversed two adjacent sides of the inner peripheral edge of the opening OP. In other ward, each triangle has intersection points. One is intersection point intersected two adjacent sides of the inner peripheral edge of the opening OP. Others are intersection points intersected an imaginary line and these two sides. The imaginary line is intersected so as to travers these two sides.
Hereinafter, the semiconductor device according to a fifth embodiment will be described with reference to
As shown in
(Effects of the Third, the Fourth and the Fifth Embodiments)
Also in the structures of the third, the fourth and the fifth embodiments, since the plurality of grooves GR is formed between the inner peripheral edge of the opening OP and the outer peripheral edge of the bonding region BAR, the plurality of grooves GR can reduce the impact applied during wire bonding. Then, it is possible to suppress the transmission of the impact to the first surface protective film IF1.
Further, the conductive film AL of the third, the fourth and the fifth embodiments, in a plan view, is not divided by the plurality of grooves GR. Therefore, as compared with the structure completely surrounding the periphery of the bonding region, it is possible to suppress a rigidity of the pad electrode PAD is reduced.
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments described so far, and various modifications can be made without departing from the gist thereof.
For example, in each of the above embodiments, the region where the conductive film AL and the bonding wire BW is connected may be spaced apart from the outer peripheral edge of the bonding region BAR, it may coincide with the outer peripheral edge of the bonding region BAR. That is, the bonding wire BW may be connected to the conductive film AL so that its connecting end covers a portion of the groove GR.
Although the pad electrode PAD has been described a case in which a rectangular in plan view, a shape of the pad electrode PAD is not limited to the rectangular. That is, the shape of the pad chip PAD may be a polygon, such as eight squares, or may be a circle shape. By the shape of the pad electrode PAD and the polygonal or circular, it is possible to disperse the impact concentrated on corners of the pad electrode PAD during wire bonding.
