Patent Application
20220051962
The present disclosure generally relates to semiconductor devices, and more particularly relates to semiconductor device assemblies and systems with internal thermal barriers and methods for making the same.
Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include one or more semiconductor dies mounted on a substrate and encased in a protective covering or capped with a heat-conducting lid. In operation, semiconductor dies can generate heat, which can pose a challenge for package design as the number of devices and the power density thereof increases. Various approaches to managing the generated heat include providing heat dissipating structures such as lids or heat sinks over the semiconductor dies to assist with heat exchange between the package and the environment in which it operates. Additional approaches to better manage heat generated by packaged semiconductor dies are desired.
Specific details of several embodiments of semiconductor devices, and associated systems and methods, are described below. A person skilled in the relevant art will recognize that suitable stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
In the assembly 100 of
To address this limitation, in the embodiments described below, semiconductor device assemblies can include a layer of thermal barrier material between a first semiconductor device (e.g., a logic die or other heat-generating device) and a second semiconductor device (e.g., a memory die or other device whose performance may be improved in a lower-temperature environment). The layer of thermal barrier material can reduce the conduction of the heat generated by the first semiconductor device towards the second semiconductor device.
To improve the thermal performance of the assembly 200, a layer of thermal barrier material 211 is disposed between the first semiconductor die 202 and a lowermost one of the second semiconductor dies 203a. The thermal barrier material of the layer 211 can have a low thermal conductivity κ (i.e., a high thermal resistivity RA). For example, the thermal barrier material of the layer 211 can have a thermal conductivity K of less than 5 W/(m ° K), less than 2 W/(m ° K), less than 1 W/(m ° K), or less than 0.5 W/(m ° K) in the z-direction (e.g., in the direction along which the first and second semiconductor die are spaced) to reduce or prevent the conduction of heat generated by the first semiconductor die 202 towards the second semiconductor dies 203a-203d. In this regard, the layer of thermal barrier material 211 can be configured to provide a rate of heat transfer towards the package substrate 201 that is greater than a rate of heat transfer towards the second semiconductor dies 203a-203d. According to one aspect of the present disclosure, during operation of the assembly 200, a temperature gradient across the layer of thermal barrier material 211 may be greater than a temperature gradient from a portion (e.g., an upper surface, a lower surface, an intermediate point) of the first semiconductor die 202 and a portion (e.g., an upper surface, a lower surface, an intermediate point) of the package substrate 201. In accordance with one aspect of the present disclosure, the thermal barrier material of the layer 211 can be a different material than the encapsulant material 209 and can have a thermal conductivity less than that of the encapsulant material 209. The layer of thermal barrier material 211 can comprise one or more of a number of materials with the requisite thermal conductivity, including a silicon oxide glass (κ=0.5-1.2 W/(m ° K)), thick tetraethoxysilane (TEOS) (κ=0.1 W/(m ° K)), polyimide (κ=0.2-2.0 W/(m ° K)), ceramic (e.g., AlOx) or the like.
In accordance with one aspect of the present disclosure, the layer of thermal barrier material 211 can have a thickness of between about 2 μm and 50 μm. Accordingly, the contribution of the layer of thermal barrier material 211 to the overall package height of the semiconductor device assembly 200 can be minimal. In other embodiments, the thickness of the layer of thermal barrier material can be greater or lesser than this range, depending upon the desired overall package height, the properties of the thermal barrier material used, and the amount of heat generated by the first semiconductor die. For example, in some embodiments in which silicon oxide glass is used as the thermal barrier material, the layer of thermal barrier material 211 can have a thickness of less than 10 μm and still provide a significant thermal barrier in the z-direction. In other embodiments in which a material with an even lower thermal conductivity κ is used, such as polyimide, the thickness of the layer of thermal barrier material 211 can be even less (e.g., less than 5 μm). In accordance with one aspect of the present disclosure, the thickness of a layer of thermal barrier material may correspond to its thermal conductivity (e.g., thinner layers of a material with lower thermal conductivity may be capable of substantially the same reductions in heat conduction in the z-direction as thicker layers of a material with higher thermal conductivity).
In one embodiment, the layer of thermal barrier material 211 can be provided on the backside of the first semiconductor die 202 while multiple such dies are still in wafer form (e.g., in back-end processing). The layer of thermal barrier material 211 can be provided by any one of a number of deposition processes readily known to those skilled in the art, including sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), liquid application followed by curing, spin coating, tape application, attachment with adhesives, etc. Because back-side processing is usually completed after the front-side fabrication of the active layer of a die (e.g., formation of the semiconductor device structures therein), in some embodiments the deposition process can be constrained to a temperature sufficiently low to avoid causing heat-induced damage to the semiconductor device structures in the dies (e.g., at temperatures below about 300° C., or below about 250° C., or even below about 200° C.).
In accordance with one aspect of the present disclosure, providing a layer of thermal barrier material 211 over the first semiconductor die 202 can reduce the conduction of heat generated by the first semiconductor die 202 in an undesirable direction (e.g., towards the stack of second semiconductor dies 203a-203d). The heat generated by the first semiconductor die 211 will therefore preferentially conduct in other more desirable directions (e.g., laterally through the package towards the vertical side edges thereof, downwards through the substrate of the package). To further improve the conduction of heat generated by the first semiconductor die 202 in a preferred direction, in some embodiments of the present disclosure heat conducting structures may also be provided.
To improve the thermal performance of the assembly 300, a layer of thermal barrier material 311 is disposed between the first semiconductor die 302 and a lowermost one of the second semiconductor dies 303a, as set forth in greater detail above with respect to
In accordance with one aspect of the present disclosure, the inclusion of both a layer of thermal barrier material disposed over a die and one or more thermal conducting structures disposed in the substrate under a die can preferentially conduct the majority of the heat generated by a die in a desired direction (e.g., through the thermal conducting structures and out of the assembly). In this regard, depending upon the size, thickness, and composition of the layer of thermal barrier material and the size, number, and composition of the thermal conducting structures, the majority (e.g., more than 50%, more than 66%, more than 75%, or even more than 90%) of the heat generated by the die can be conducted away from other dies in the assembly.
Although in the foregoing example embodiment semiconductor device assemblies have been illustrated and described in which layers of thermal barrier are illustrated as approximately coextensive in size with the die whose generated heat they are configured to manage, in other embodiments layers of thermal barrier material having different sizes may also be used. For example,
To improve the thermal performance of the assembly 400, a layer of thermal barrier material 411 is disposed between the first semiconductor die 402 and a lowermost one of the second semiconductor dies 403a. Unlike the layer of thermal barrier material 311 illustrated in
In yet another embodiment, a layer of thermal barrier material may be provided just over that portion of those portions of a semiconductor die where a high density of power consuming circuits are located, rather than over the whole surface of a die.
To improve the thermal performance of the assembly 500, a layer of thermal barrier material 511 is over a portion of the first semiconductor die 502. Unlike the layer of thermal barrier material 311 illustrated in
Although the foregoing example embodiments have been illustrated and described with reference to package assemblies including a stack of memory dies provided over a logic die, in other embodiments package assemblies with other arrangements can likewise benefit from the aforementioned techniques for improved thermal performance. For example,
To improve the thermal performance of the assembly 600, a layer of thermal barrier material 611 is disposed over the first semiconductor die 602. In one embodiment, the layer of thermal barrier material 611 can be provided on the backside of the first semiconductor die 602 while multiple such dies are still in wafer form (e.g., in back-end processing). In accordance with one aspect of the present disclosure, providing a layer of thermal barrier material 611 over the first semiconductor die 602 can reduce the conduction of heat generated by the first semiconductor die 602 in an undesirable direction (e.g., into the encapsulant material 609). The heat generated by the first semiconductor die 611 will therefore preferentially conduct in other more desirable directions (e.g., downwards through the substrate of the package). To further improve the conduction of heat generated by the first semiconductor die 602 in a preferred direction, in some embodiments of the present disclosure heat conducting structures may also be provided.
To improve the thermal performance of the assembly 700, a layer of thermal barrier material 711 is disposed over the first semiconductor die 702. To further improve thermal performance of the assembly, thermal conducting structures 712 (e.g., vias, heat pipes, metal plugs, etc.) are also provided in substrate 701, to conduct heat generated by the first semiconductor die 202 downwardly through the substrate 701. The thermal conducting structures 712 may extend from an upper surface of the substrate 701 to a lower surface thereof, and may optionally be connected to thermally conductive interconnects (e.g., solder balls 704, 710) that are electrically isolated from the circuits of the first semiconductor device (e.g., “dummy” bumps). Alternatively, the interconnects to which the thermal conducting structures 712 are connected may serve double-duty as “live” interconnects (e.g., providing power, grounding, or signals to the first semiconductor device). By connecting thermal conducting structures 712 to a package interconnect 710 on the lower surface of the substrate 701, a thermal circuit can be formed with the system-level board to which the assembly 700 is connected, and which can be provided with heat dissipation structures (e.g., heat sinks, heat fins, etc.) to further improve the thermal management of assembly 700.
Although the foregoing example embodiments have been illustrated and described with a single layer of thermal barrier material on a die, in other embodiments a die could be provided with multiple layers of thermal barrier material to further reduce the conduction of heat generated in an assembly in an undesirable direction. For example, in one embodiment, a die could be provided with a stack of layers of thermal barrier material on a back side thereof. The layers could each comprise the same material, or could include different materials (e.g., depending upon the various design constraints of total package height, processing temperature limitations, etc.).
In accordance with one aspect of the present disclosure, although the foregoing example embodiments have been illustrated and described with reference to semiconductor device assemblies including multiple semiconductor dies and a substrate, in still other embodiments semiconductor device assemblies can include different arrangements. For example, package assemblies with different numbers and arrangements of dies can likewise benefit from the thermal management techniques described above. In this regard, a single device package (SDP) could include a single die disposed over a substrate, with a single layer of thermal barrier material disposed either between the die and the substrate, or over a side of the die opposing the substrate, depending upon the desirable and undesirable directions of heat conduction. In another embodiment, a substrate-free package could include multiple dies in a stack with one or more layers of thermal barrier material between adjacent dies. In still another embodiment, a substrate-free package with a single die (e.g., chip-scale packaging) could include a single die with one or more layers of thermal barrier material disposed thereon. In yet another embodiment, a discrete semiconductor died (e.g., not provided in a package) could be provided with one or more layers of thermal barrier material disposed thereon.
Any one of the semiconductor devices and semiconductor device assemblies described above with reference to
The devices discussed herein, including a memory device, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.
The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.
As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”
As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation.
It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.
