SEMICONDUCTOR DEVICE COMPRISING SOI TRANSISTORS AND BULK TRANSISTORS AND A METHOD OF FORMING THE SAME

Abstract

By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1f schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages for forming SOI-like transistors and bulk transistors in adjacent device regions starting from an SOI substrate and re-growing relevant portions of a semiconductor material on the basis of a crystalline portion of the substrate according to illustrative embodiments of the present invention;

FIG. 1 g schematically illustrates a top view of a plurality of transistor elements formed as SOI devices and bulk devices, respectively, wherein the transistor width of the bulk devices may be reduced compared to equivalent SOI devices according to the present invention;

FIGS. 2 a-2d schematically illustrate cross-sectional views during the formation of first and second crystalline semiconductor regions for SOI devices and bulk devices, respectively, in which additional material removal processes, such as chemical mechanical polishing (CMP), may be used according to other illustrative embodiments;

FIGS. 3 a-3b schematically illustrate cross-sectional views of the formation of SOI regions and bulk regions on the basis of an implantation process according to yet other illustrative embodiments; and

FIGS. 4 a-4c schematically illustrate cross-sectional views of a substrate and a donator substrate for forming corresponding SOI regions and bulk regions on the substrate according to yet other illustrative embodiments of the present invention.

Claims

1. A method, comprising: forming a first plurality of transistors of an electronic circuit in an SOI region formed on a substrate; andforming a second plurality of transistors of said electronic circuit in bulk region formed on said substrate.

2. The method of claim 1, wherein at least some of said second plurality of transistors are formed so as to define a memory cell.

3. The method of claim 1, wherein forming said first and second plurality of transistors comprises providing said substrate having formed thereon a buried insulating layer and a semiconductor material formed on said buried insulating layer, patterning said semiconductor material and said buried insulating layer to form a first crystalline semiconductor region on said insulating layer and to expose a portion of said substrate, and forming a second crystalline semiconductor region on said exposed portion of said substrate.

4. The method of claim 3, wherein forming said second crystalline semiconductor region on said exposed portion of said substrate comprises epitaxially growing said second semiconductor region using said exposed portion as a growth template.

5. The method of claim 4, wherein epitaxially growing said second crystalline semiconductor region comprises covering said first crystalline semiconductor region and forming said second crystalline semiconductor region by a selective epitaxial growth process.

6. The method of claim 5, wherein covering said first crystalline semiconductor region comprises forming a mask layer above said semiconductor material, patterning said mask layer and using said patterned mask layer as a mask for forming said first and second semiconductor regions.

7. The method of claim 3, wherein forming said second crystalline semiconductor region comprises depositing a semiconductor material and re-crystallizing said deposited semiconductor material using said exposed portion of said substrate as a crystal template.

8. The method of claim 7, further comprising removing excess material of said deposited semiconductor material.

9. The method of claim 1, wherein forming said first and second pluralities of transistors comprises providing said substrate having formed thereon a semiconductor layer, and selectively forming a buried insulating layer in said semiconductor layer to define said SOI region.

10. The method of claim 9, wherein selectively forming said buried insulating layer comprises selectively introducing a species by ion implantation and performing a heat treatment to form said buried insulating layer on the basis of said species.

11. The method of claim 10, wherein selectively introducing said species comprises forming an implantation mask covering said bulk region.

12. The method of claim 1, wherein forming said first and second pluralities of transistors comprises forming a crystalline portion and an insulating portion in a surface layer of a donator substrate, bonding said donator substrate with said surface layer to said substrate and removing excess material of said donator substrate so as to maintain material as said SOI region on said insulating portion and to use said crystalline portion as said bulk region.

13. The method of claim 12, wherein said excess material is removed by cleaving said donator substrate.

14. The method of claim 12, wherein said insulating portion is formed by forming a recess in said surface layer and filling said recess with an insulating material.

15. A method, comprising: providing a substrate comprising a buried insulating layer formed on a first crystalline layer and a second crystalline layer formed on said buried insulating layer;removing a portion of said second crystalline layer and said buried insulating layer so as to expose a portion of said first crystalline layer; andforming a crystalline bulk region by performing a selective epitaxial growth process using said exposed portion of the first crystalline layer as a growth template.

16. The method of claim 15, further comprising forming a mask exposing said portion, wherein removing said portion and performing said selective epitaxial growth process is performed on the basis of said mask.

17. The method of claim 15, wherein said crystalline bulk region is a region for receiving a plurality of memory cells of an integrated circuit to be formed above said substrate.

18. A semiconductor device, comprising: a substrate comprised of a plurality of SOI regions and a plurality of bulk regions;a first plurality of transistors in said SOI regions; anda second plurality of transistors in said bulk regions.

19. The semiconductor device of claim 18, wherein said first plurality of field effect transistors represent a logic circuit and said second plurality of field effect transistors represent a memory block.

20. The semiconductor device of claim 19, wherein said second plurality of field effect transistors are commonly connectable to a common reference potential.