Patent Application
20190035922
This application claims the benefit of Japanese Priority Patent Application JP 2016-009797 filed Jan. 21, 2016, the entire contents of which are incorporated herein by reference.
The present disclosure relates to semiconductor devices, electronic parts, electronic apparatuses, and methods for fabricating a semiconductor device.
In recent years, as a semiconductor device employing compound semiconductors, a high electron mobility transistor (HEMT) has attracted attention.
The high electron mobility transistor is a field effect transistor in which a two-dimensional electron gas layer formed by a heterojunction of compound semiconductors is used as a channel. The two-dimensional electron gas layer has a high electron mobility and a high sheet electron density. Therefore, the high electron mobility transistor is a semiconductor device which can perform a low-resistance, high-speed, and high-breakdown-voltage operation.
For example, a high electron mobility transistor has a structure in which a barrier layer is provided on a channel layer, and a source electrode and a drain electrode are provided on the barrier layer. In such a high electron mobility transistor, the barrier layer having a wide band gap serves as a potential barrier, and therefore, the contact resistances between the source and drain electrodes, and the two-dimensional electron gas layer, which is a channel, are high.
Therefore, in order reduce the contact resistances between the source and drain electrodes and the two-dimensional electron gas layer, a technique of alloying the source and drain electrodes and the barrier layer by high-temperature annealing has been proposed. Also, as disclosed in Patent Literature 1 below, a technique for decreasing the contact resistances by selectively regrowing a high-concentration layer doped with impurities at a high concentration in regions which are in contact with the source electrode and the drain electrode, has been proposed.
PTL 1: JP 2011-159795A
However, in the technique disclosed in Patent Literature 1, there is a limit on the decrease of the resistance of the high electron mobility transistor during operation (also referred to as an “on-resistance”). This is because the on-resistance of the field effect transistor is determined by the sum of the contact resistances between the source and drain electrodes and the channel and the channel resistance depending on the distance between the source electrode and the drain electrode, and in the technique disclosed in Patent Literature 1, it is difficult to reduce the distance between the source electrode and the drain electrode.
Therefore, there has been a demand for a semiconductor device in which the on-resistance can be further reduced, an electronic part and electronic apparatus including the semiconductor device, and a method for fabricating the semiconductor device.
According to an embodiment of the present disclosure, there is provided a semiconductor device including: a substrate; a first contact layer of a first conductivity type provided on the substrate; a channel layer provided on the first contact layer; a gate electrode provided on a side surface of the channel layer with a barrier layer being interposed between the gate electrode and the side surface of the channel layer; a second contact layer of the first conductivity type provided on the channel layer; a first electrode provided on the first contact layer; and a second electrode provided on the second contact layer.
According to an embodiment of the present disclosure, there is provided an electronic part including: a semiconductor device. The semiconductor device includes a substrate, a first contact layer of a first conductivity type provided on the substrate, a channel layer provided on the first contact layer, a gate electrode provided on a side surface of the channel layer with a barrier layer being interposed between the gate electrode and the side surface of the channel layer, a second contact layer of the first conductivity type provided on the channel layer, a first electrode provided on the first contact layer, and a second electrode provided on the second contact layer.
According to an embodiment of the present disclosure, there is provided an electronic apparatus including: a semiconductor device. The semiconductor device includes a substrate, a first contact layer of a first conductivity type provided on the substrate, a channel layer provided on the first contact layer, a gate electrode provided on a side surface of the channel layer with a barrier layer being interposed between the gate electrode and the side surface of the channel layer, a second contact layer of the first conductivity type provided on the channel layer, a first electrode provided on the first contact layer, and a second electrode provided on the second contact layer.
According to an embodiment of the present disclosure, there is provided a method for fabricating a semiconductor device, including: epitaxially growing a first contact layer of a first conductivity type on a substrate; epitaxially growing a channel layer on the first contact layer; epitaxially growing a channel layer on the first contact layer; epitaxially growing a second contact layer of the first conductivity type on the first contact layer; etching the channel layer and the second contact layer into an island shape in planar view; forming a barrier layer and a gate electrode material layer successively on the first contact layer and the second contact layer; forming a gate electrode on a side surface of the channel layer by anisotropically etching the gate electrode material layer; and forming a first electrode and a second electrode on the first contact layer and the second contact layer, respectively.
According to an embodiment of the present disclosure, the distance between the source electrode and the drain electrode can be reduced without using state-of-the-art fabrication equipment.
As described above, according to an embodiment of the present disclosure, the on-resistance of a semiconductor device can be further reduced.
Note that the effects described above are not necessarily limitative. With or in the place of the above effects, there may be achieved any one of the effects described in this specification or other effects that may be grasped from this specification.
Hereinafter, (an) embodiment(s) of the present disclosure will be described in detail with reference to the appended drawings. In this specification and the appended drawings, structural elements that have substantially the same function and structure are denoted with the same reference numerals, and repeated explanation of these structural elements is omitted.
Note that description will be provided in the following order.
0. Technical background of the present disclosure
1.1. Structure of semiconductor device
1.2. Method for fabricating semiconductor device
6.1. First structure example
6.2. Second structure example
6.3. Third structure example
Firstly, the technical background of the present disclosure will be described with reference to
As shown in
The substrate 50 is formed of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or the like.
The buffer layer 51 is formed of a compound semiconductor material, and is for epitaxially growing the channel layer 30 and the barrier layer 31 on the substrate 50. Specifically, the buffer layer 51 is formed of a compound semiconductor material the grating constant of which is appropriately controlled, and can be used to control the crystal orientation and crystalline state of the channel layer 30 provided on the buffer layer 51. As a result, even when the substrate 50 and the channel layer 30 have significantly different grating constants, the channel layer 30 can be epitaxially grown.
The channel layer 30 is formed of a compound semiconductor material, and the barrier layer 31 is formed of a compound semiconductor material different from that of the channel layer 30. The different compound semiconductor materials are joined together at an interface between the channel layer 30 and the barrier layer 31, so that an electron layer called the two-dimensional electron gas layer 32 is formed.
Note that the channel layer 30 in which the two-dimensional electron gas layer 32 is formed may be formed of an i-type (i.e., undoped) compound semiconductor. When the channel layer 30 is of the i-type, impurity scattering is reduced, and therefore, the two-dimensional electron gas layer 32 can be used as a high-mobility channel. Also, the barrier layer 31 may be formed of either an i-type or n-type compound semiconductor if the barrier layer 31 allows formation of the two-dimensional electron gas layer 32. The barrier layer 31 may be formed of an n-type compound semiconductor in order to increase the electron density of the two-dimensional electron gas layer 32 which is a channel.
A compound semiconductor transistor which includes such a two-dimensional electron gas layer (32) as a channel is also called a “high electron mobility transistor (HEMT).”
Examples of the combination of compound semiconductor materials which form such a heterojunction include GaAs and AlGaAs, GaN and AlGaN, GaAs and InGaP, GaN and AlInN, and the like.
The gate electrode 40 is formed of a metal such as nickel (Ni), titanium (Ti), gold (Au), or the like. The gate electrode 40 and the barrier layer 31 form a Schottky junction, which forms, in the barrier layer 31, a depletion layer extending from the gate electrode 40. Meanwhile, in the barrier layer 31, the two-dimensional electron gas layer 32 formed in the channel layer 30 forms a depletion layer extending from the channel layer 30.
In the compound semiconductor transistor 10, the electron concentration of the two-dimensional electron gas layer 32 can be controlled by controlling a voltage applied to the gate electrode 40 so that the compound semiconductor transistor 10 functions as an field effect transistor in which a two-dimensional electron gas layer is a channel.
The source electrode 21 and the drain electrode 11 are formed of a metal such as titanium (Ti), aluminum (Al), or the like. Also, the source electrode 21 and the drain electrode 11 are formed to provide an ohmic contact with the channel layer 30.
Here, in the compound semiconductor transistor 10, the resistance during operation (also called an “on-resistance”) is high. This is because the barrier layer 31, which is a high potential barrier, is interposed between each of the source electrode 21 and the drain electrode 11, and the two-dimensional electron gas layer 32 which is a channel, so that the contact resistance is high.
Therefore, in order to reduce the contact resistance, for example, a technique of reducing the potential barrier by replacing a portion of the barrier layer 31 with a layer doped with impurities at a high concentration, has been proposed. Also, in order to reduce the contact resistance, a technique of alloying a metal of which the source electrode 21 and the drain electrode 11 are formed, and the barrier layer 31, by high-temperature annealing, has been proposed.
However, when the contact resistance is only reduced, there is a limit on the decrease of the on-resistance of the compound semiconductor transistor 10. This is because the on-resistance of the compound semiconductor transistor 10 includes a channel resistance depending on the distance between the source electrode 21 and the drain electrode 11.
The channel resistance may be reduced by, for example, employing a fabrication process capable of further miniaturization and thereby reducing the distance between the source electrode 21 and the drain electrode 11. However, when a fabrication process capable of further miniaturization is employed, the fabrication cost increases significantly. Therefore, it has been difficult to further reduce the on-resistance of the compound semiconductor transistor 10 while inhibiting the increase of the fabrication cost.
The present inventors have extensively studied the above circumstances to find the technology according to the present disclosure. A semiconductor device according to one embodiment of the present disclosure has a novel and improved structure in which the distance between the source electrode and the drain electrode can be reduced so that the on-resistance is further reduced.
The above semiconductor device according to one embodiment of the present disclosure will now be described in detail.
<1.1. Structure of Semiconductor Device>
Firstly, a multilayer structure of a semiconductor device according to a first embodiment of the present disclosure will be described with reference to
As shown in
Note that the semiconductor device 1 according to this embodiment is a high electron mobility transistor. A two-dimensional electron gas layer 320 which is a channel is formed in the vicinity of an interface of the channel layer 300 which is in contact with the barrier layer 310, substantially perpendicularly to the substrate 500.
The substrate 500 is formed of a compound semiconductor material. Specifically, the substrate 500 is formed of a group III-V compound semiconductor material. For example, the substrate 500 may be a semi-insulating monocrystalline gallium nitride (GaN) substrate. Also, when the buffer layer 510 described below is provided, the substrate 500 may be formed of a material which has a grating constant different from that of the first contact layer 100 provided on the substrate 500. In such a case, the substrate 500 may, for example, be a silicon (Si) substrate, silicon carbide (SiC) substrate, sapphire substrate, or the like.
The buffer layer 510 is provided on the substrate 500, and is formed of an epitaxially grown compound semiconductor material. Specifically, the buffer layer 510 is formed of a compound semiconductor material having an appropriate grating constant based on the grating constants of the substrate 500 and the first contact layer 100. When the substrate 500 and the first contact layer 100 have different grating constants, the grating constant of the buffer layer 510 can be controlled so that the first contact layer 100 can have a good crystalline state and the warpage of the semiconductor device 1 is controlled. For example, when the substrate 500 is a Si substrate, and the first contact layer 100 is formed of GaN, the buffer layer 510 can be formed of AlN, AlGaN, GaN, or the like.
The first contact layer 100 is provided on the buffer layer 510, and is formed of a compound semiconductor material doped with an impurity at a high concentration. Specifically, the first contact layer 100 may be formed of the same compound semiconductor material as that of the channel layer 300 described below that is doped with an n-type impurity at a high concentration. The first contact layer 100, the resistance of which is reduced by the high-concentration doping, can reduce the contact resistance between the first contact layer 100 and the first electrode 110. For example, when the channel layer 300 is formed of GaN, the first contact layer 100 may be formed of epitaxially grown GaN which is doped with silicon (Si) or germanium (Ge). Also, the concentration of the impurity for the doping may be 1.0×1018/cm3 or more.
The channel layer 300 is provided in an island shape on a partial region of the first contact layer 100, and is formed of a compound semiconductor material in which carriers are accumulated due to a heterojunction between the channel layer 300 and the barrier layer 310. Also, the two-dimensional electron gas layer 320 is formed on a side surface of the channel layer 300, in a direction substantially perpendicular to the substrate 500. Specifically, the channel layer 300 may be formed of a compound semiconductor material which is not doped with an impurity, i.e., an i-type (i.e., undoped) compound semiconductor material. In such a case, in the channel layer 300, carrier scattering caused by impurities is inhibited, and therefore, carrier mobility can be improved in the two-dimensional electron gas layer 320. For example, the channel layer 300 may be formed of epitaxially grown GaN.
Also, the two-dimensional electron gas layer 320 is epitaxially grown and formed on the side surface of the channel layer 300 so that the C-axis direction of the crystal is substantially perpendicular to the side surface of the channel layer 300. For example, in the case of GaN, a two-dimensional electron gas layer is formed on the polar c-plane (0001) of the crystal. Therefore, the crystal orientation of the channel layer 300 may be appropriately controlled so that the two-dimensional electron gas layer 320 is formed on the side surface of the channel layer 300. Note that, as long as the two-dimensional electron gas layer 320 can be formed on the side surface of the channel layer 300, the C-axis of the crystal orientation of the channel layer 300 may not be perpendicular to the side surface, and may be inclined in any direction by up to about 55°. Note that when the angle of the inclination is large, it is difficult to form the two-dimensional electron gas layer 320 on the side surface, and therefore, the inclination angle of the C-axis of the crystal may be within 10° or less in any direction with respect to the normal direction of the side surface.
The second contact layer 200 is provided on the channel layer 300, and is formed of a compound semiconductor material doped with an impurity at a high concentration. Specifically, the second contact layer 200 may be formed of the same compound semiconductor material as that of the channel layer 300 that is doped with an n-type impurity at a high concentration. The second contact layer 200, the resistance of which is reduced by the high-concentration doping, can reduce the contact resistance between the second contact layer 200 and the second electrode 210. For example, when the channel layer 300 is formed of GaN, the second contact layer 200 may be formed of epitaxially grown GaN which is doped with silicon (Si) or germanium (Ge). Also, the concentration of the impurity for the doping may be 1.0×1018/cm3 or more.
The barrier layer 310 is provided on the first contact layer 100 and the second contact layer 200, and is formed of a compound semiconductor material which causes carriers to be accumulated in the channel layer 300 due to a heterojunction between the barrier layer 310 and the channel layer 300. Specifically, the barrier layer 310 is formed of a compound semiconductor material different from that of the channel layer 300. Also, the barrier layer 310 may be formed of a compound semiconductor material which is not doped with an impurity, i.e., an i-type (i.e., undoped) compound semiconductor material. In such a case, the barrier layer 310 can inhibit carrier scattering caused by impurities in the channel layer 300, and therefore, the carrier mobility of the two-dimensional electron gas layer 320 can be improved. For example, when the channel layer 300 is formed of GaN, the barrier layer 310 may be formed of epitaxially grown Al1-x-yGaxInyN (0≤x<1, 0≥y<1, excluding x=y=0).
Note that, as long as the two-dimensional electron gas layer 320 is formed by a heterojunction, the channel layer 300 and the barrier layer 310 may be formed of respective compound semiconductor materials a combination of which is different from that described above. For example, the channel layer 300 and the barrier layer 310 may be formed of GaAs and AlGaAs, GaAs and InGaP, or GaN and AlInN, respectively.
The gate electrode 400 is provided on the side surface of the channel layer 300 with the barrier layer 310 being interposed therebetween. Also, the gate electrode 400 is formed of a metal which forms a Schottky junction between the gate electrode 400 and the barrier layer 310. For example, the gate electrode 400 may be formed by successively forming a layer of nickel (Ni) and a layer of gold (Au) on top of each other, where the nickel layer is closer to the barrier layer 310. As a result, the concentration of the two-dimensional electron gas layer 320 can be controlled by controlling a voltage applied to the gate electrode 400.
Note that, as shown in
The insulating layer 520 is formed of an insulating material, and is provided to cover the entire surfaces of the barrier layer 310 and the gate electrode 400. The insulating layer 520 insulates the barrier layer 310 and the gate electrode 400 from other electrodes, interconnects, and the like, and protects the barrier layer 310 and the gate electrode 400 from impurities such as ions and the like. The insulating layer 520 may be a monolayer film of, for example, SiN, Si3N4, SiO, SiO2, Al2O3, or the like, or a multilayer film thereof.
The first electrode 110 is configured to be coupled to the first contact layer 100, while the second electrode 210 is configured to be coupled to the second contact layer 200. For example, the first electrode 110 and the second electrode 210 may be formed by successively forming a layer of titanium (Ti) and a layer of aluminum (Al), or the like, on top of each other, where the titanium layer is closer to the first contact layer 100 and the second contact layer 200. Also, the first electrode 110 may be a source electrode, while the second electrode 210 may be drain electrode, or vice versa, of course.
In the semiconductor device 1 according to this embodiment, the two-dimensional electron gas layer 320 is formed in the channel layer 300 by a heterojunction between the channel layer 300 and the barrier layer 310, substantially perpendicularly to the substrate 500. An upper end of the two-dimensional electron gas layer 320 is coupled to the second electrode 210 with the second contact layer 200 being interposed therebetween, while a lower end of the two-dimensional electron gas layer 320 is coupled to the first electrode 110 with the first contact layer 100 being interposed therebetween. In other words, in the semiconductor device 1, the two-dimensional electron gas layer 320 forms a current path between the first electrode 110 and the second electrode 210.
Also, in the semiconductor device 1, a current flowing between the first electrode 110 and the second electrode 210 can be modulated by the concentration of the two-dimensional electron gas layer 320 being modulated by a Schottky junction formed between the barrier layer 310 and the gate electrode 400. Specifically, when a positive bias is applied to the gate electrode 400, a current flowing between the first electrode 110 and the second electrode 210 is generated by electrons accumulated in the two-dimensional electron gas layer 320. Meanwhile, when a negative bias is applied to the gate electrode 400, the Schottky junction depletes electrons in the two-dimensional electron gas layer 320 of the channel layer 300 facing the gate electrode 400, so that a current does not flow between the first electrode 110 and the second electrode 210. Such an operation allows the semiconductor device 1 to function as a field effect transistor. As also shown in
Next, a planar structure of the semiconductor device 1 according to this embodiment will be described with reference to
As shown in
Also, each component of the semiconductor device 1 is provided in the device region 600. A region outside the device region 600 has a high resistance so that the semiconductor device 1 is electrically separated from other semiconductor devices provided on the substrate 500. The high resistance may be imparted to the region outside the device region 600 by, for example, injecting impurity ions such as boron (B) ions or the like into the first contact layer 100, or by burying an insulating material in an opening formed by removal of the first contact layer 100 using etching or the like. Note that, as described above, the control electrode 401 which is coupled to the gate electrode 400 and is used to control a voltage applied to the gate electrode 400, is provided in the region outside the device region 600.
In such a planar structure of the semiconductor device 1, the two-dimensional electron gas layer 320 can be formed on the side surface of the channel layer 300 (specifically, a surface substantially perpendicular to the C-axis of the crystal), and therefore, the current density can be higher than that of the compound semiconductor transistor 10 shown in
In the semiconductor device 1 having the above structure, the thickness of the channel layer 300 corresponds to a distance between the source electrode and the drain electrode. The thickness of the channel layer 300 can be controlled on the nanometer scale without using state-of-the-art fabrication equipment, and therefore, in the semiconductor device 1, the distance between the source electrode and the drain electrode can be reduced irrespective of the miniaturization capability of the fabrication process. Therefore, in the semiconductor device 1 according to this embodiment, the reduction of the distance between the source electrode and the drain electrode can reduce the channel resistance, resulting in a reduction in the on-resistance.
Also, in the semiconductor device 1 according to this embodiment, the thickness of the channel layer 300 also corresponds to the gate length. Therefore, the gate length can be similarly reduced irrespective of the miniaturization capability of the fabrication process, whereby the semiconductor device 1 can operate at higher speed. In addition, in the semiconductor device 1 according to this embodiment, the side surface of the channel layer 300 formed in an island shape can be used as a channel to provide a higher current density, and therefore, the semiconductor device can have a size smaller than those of field effect transistors having other structures (e.g., the compound semiconductor transistor 10 shown in
<1.2. Method for Fabricating Semiconductor Device>
Next, a method for fabricating the semiconductor device 1 according to this embodiment will be described with reference to
Initially, as shown in
For example, the substrate 500 may be a silicon (Si) substrate. Also, the buffer layer 510 is formed of, for example, AlN, AlGaN, or GaN, while the first contact layer 100 and the second contact layer 200 may be formed of, for example, n-type GaN doped with silicon (Si). Note that the channel layer 300 may be formed of, for example, undoped GaN so that the C-axis of the crystal faces in a direction substantially perpendicular to the thickness direction of the substrate 500. In order to control the crystal orientation of the channel layer 300, for example, the plane orientation of a surface of the substrate 500 on which the semiconductor device 1 is to be formed may be appropriately controlled.
Next, as shown in
Here, although not shown, after the patterning has been performed on the channel layer 300 and the second contact layer 200, an isolation step is performed in order to separate semiconductor devices on the substrate 500 from each other. For example, the isolation may be achieved by injecting impurity ions such as boron (B) ions or the like into the first contact layer 100 so that the region outside the device region 600 on which the semiconductor device 1 is formed has a high resistance. Alternatively, the isolation may be achieved by removing the first contact layer 100 in the region outside the device region 600 on which the semiconductor device 1 is formed, using etching or the like, and then burying an insulating material.
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
The above fabrication steps can be used to fabricate the semiconductor device 1 according to this embodiment. In the semiconductor device 1 according to this embodiment, the gate electrode 400 can be formed only on the side surface of the channel layer 300 protruding on the first contact layer 100 by so-called self-alignment without using a mask or the like. Therefore, according to the above fabrication method, the semiconductor device 1 according to this embodiment can be easily fabricated without the need of a large additional cost. In view of
Next, a semiconductor device 2 according to a second embodiment of the present disclosure will be described with reference to
As shown in
The gate insulating layer 410 is formed of an insulating material. For example, the gate insulating layer 410 may be formed of SiO2 or Al2O3 using atomic layer deposition (ALD). In the semiconductor device 2 according to this embodiment, an MIS gate is formed by the gate insulating layer 410 being provided between the barrier layer 310 and the gate electrode 400.
In the MIS gate, by applying a voltage to the gate electrode 400, the carrier concentration or band state of the barrier layer 310 is modulated. Therefore, in the semiconductor device 2 according to this embodiment, by applying a voltage to the gate electrode 400, the electron concentration of the two-dimensional electron gas layer 320 can be controlled so that a current flowing between the first electrode 110 and the second electrode 210 is modulated.
In the semiconductor device 2 having such an MIS gate, the breakdown resistance of the gate structure is improved, compared to the semiconductor device 1 having a Schottky gate shown in
Next, a semiconductor device 3 according to a third embodiment of the present disclosure will be described with reference to
As shown in
The semiconductor layer 420 is formed of a second conductivity type (e.g., p-type) semiconductor. For example, the semiconductor layer 420 may be formed by epitaxially growing GaN doped with Mg, which is a p-type impurity, on the barrier layer 310. In the semiconductor device 3 according to this embodiment, a second conductivity type (p-type) gate is formed by the semiconductor layer 420 being provided between the barrier layer 310 and the gate electrode 400. Also, the semiconductor layer 420 may be formed by doping all or a portion of the barrier layer 310 which is in contact with the gate electrode 400 with Mg, which is a p-type impurity.
In the second conductivity type (p-type) gate, by applying a voltage to the gate electrode 400, the carrier concentration or band state of the barrier layer 310 is modulated through the p-n junction. Therefore, in the semiconductor device 3 according to this embodiment, by applying a voltage to the gate electrode 400, the electron concentration of the two-dimensional electron gas layer 320 can be controlled so that a current flowing between the first electrode 110 and the second electrode 210 is modulated.
In the semiconductor device 3 having such a second conductivity type (p-type) gate, the threshold voltage can be higher than that of the semiconductor device 1 having a Schottky gate shown in
Next, a semiconductor device 4 according to a fourth embodiment of the present disclosure will be described with reference to
As shown in
In the semiconductor device 4 having such a second conductivity type (p-type) channel layer (301), the potential barrier between the first electrode 110 and the second electrode 210 can be higher than that of the semiconductor device 1 including the i-type (i.e., undoped) channel layer 300 shown in
Next, a semiconductor device 5 according to a fifth embodiment of the present disclosure will be described with reference to
As shown in
In the semiconductor device 5 according to this embodiment, a two-dimensional electron gas layer which is formed by a heterojunction of compound semiconductors is not formed, and the inversion layer formed by the MIS gate operates as a channel as in a typical field effect transistor. The semiconductor device 5 can be fabricated using a fabrication process easier than that for the semiconductor device 1 shown in
Next, a semiconductor device according to a sixth embodiment of the present disclosure will be described with reference to
In the semiconductor device according to this embodiment, a capacitance reduction region is provided in the first contact layer 100 below the channel layer 300 so that a parasitic capacitance (also called an “off-capacitance”) during non-operation which occurs by the first contact layer 100 and the second contact layer 200, which have a low resistance, facing each other, can be reduced.
Note that the capacitance reduction region is provided in a region smaller than a region where the channel layer 300 is provided in planar view. This is because when the capacitance reduction region is formed in a region having at least the same size as that of the region where the channel layer 300 is provided in planar view, it is difficult to electrically couple the two-dimensional electron gas layer 320 formed on the side surface of the channel layer 300 to the first contact layer 100.
A specific configuration of the capacitance reduction region included in the semiconductor device according to this embodiment will now be specifically described in greater detail by illustrating the first to third structure examples.
<6.1. First Structure Example>
Firstly, the first structure example will be described with reference to
The low permittivity region 121 is formed of a material having a permittivity lower than that of the first contact layer 100. For example, the low permittivity region 121 may be formed of an insulating material or a cavity. Specifically, the low permittivity region 121 may be formed by removing all or a portion of the first contact layer 100 in the corresponding region using etching or the like, and then forming the channel layer 300 on that region. Alternatively, the low permittivity region 121 may be formed by burying an insulating material such as SiO2 or the like in a region where the first contact layer 100 has been removed by etching or the like. Still alternatively, the low permittivity region 121 may be formed by etching all or a portion of the first contact layer 100 in the corresponding region from the back surface. In such a case, in addition to the first contact layer 100, a portion of the channel layer 300 may also be removed by etching from the back surface. According to the first structure example, the off-capacitance formed by the first contact layer 100 and the second contact layer 200 facing each other can be reduced.
In particular, when all the first contact layer 100 below the channel layer 300 is removed to form a cavity, a parasitic capacitance can be reduced (or alternatively, prevented) from occurring between the first contact layer 100 and the second contact layer 200.
<6.2. Second Structure Example>
Next, the second structure example will be described with reference to
The low carrier region 122 is configured to have an impurity concentration lower than that of the first contact layer 100. For example, the low carrier region 122 may be a layer formed of the same compound semiconductor material as that of the first contact layer 100 that is doped with an n-type impurity (Si, etc.) at a concentration lower than that of the first contact layer 100. Alternatively, the low carrier region 122 may be a layer the resistance of which is increased by doping the first contact layer 100 with a p-type impurity (Mg, etc.).
Specifically, the low carrier region 122 may be formed by removing all or a portion of the first contact layer 100 in the corresponding region using etching or the like, and regrowing a compound semiconductor at a concentration of an n-type impurity (Si, etc.) lower than that of the first contact layer 100. Alternatively, the low carrier region 122 may be formed by additionally doping the first contact layer 100 excluding the low carrier region 122 with an n-type impurity (Si, etc.) by ion injection or the like. Still alternatively, the low carrier region 122 may be formed by doping the low carrier region 122 with a p-type impurity (Mg, etc.) by ion injection or the like, and thereby increasing the resistance of the low carrier region 122. According to the second structure example, an off-capacitance formed by the first contact layer 100 and the second contact layer 200 facing each other can be reduced.
<6.3. Third Structure Example>
Next, the third structure example will be described with reference to
The depletion layer 123 is formed by a second conductivity type (e.g., p-type) depleted region 130 which is provided in the first contact layer 100. The depleted region 130 is obtained by, for example, doping the same compound semiconductor material as that of the first contact layer 100 with a p-type impurity (Mg, etc.). Specifically, the depleted region 130 may be formed by doping the corresponding region of the first contact layer 100 with a p-type impurity (Mg, etc.) by ion injection or the like.
Here, by providing the depleted region 130, the depletion layer 123 in which carriers are depleted by a p-n junction is formed below the channel layer 300. Note that the depletion layer 123 is formed, extending on both the first contact layer 100 and depleted region 130. In the depletion layer 123, the carrier density is reduced. Therefore, according to the third structure example, an off-capacitance formed by the first contact layer 100 and the second contact layer 200 facing each other can be reduced, as in the second structure example. Note that the depleted region 130 may be floating, although a bias voltage more negative than that of the second electrode 210 may be applied to the depleted region 130 by being in contact with a region outside the device region 600.
As described in detail, in a semiconductor device according to one embodiment of the present disclosure, the thickness of the channel layer 300 is the distance between the source electrode and the drain electrode, and therefore, the distance between the source electrode and the drain electrode can be reduced without using state-of-the-art fabrication equipment. Therefore, in the semiconductor device according to one embodiment of the present disclosure, the channel resistance and the on-resistance can be reduced.
Also, in a semiconductor device according to one embodiment of the present disclosure, the thickness of the channel layer 300 is the gate length, and therefore, the gate length can be reduced without using state-of-the-art fabrication equipment. Therefore, the semiconductor device can operate at higher speed.
Moreover, in a semiconductor device according to one embodiment of the present disclosure, the side surface of the channel layer 300 formed in an island shape serves as a channel, and therefore, the current density can be increased. As a result, the size of the semiconductor device according to one embodiment of the present disclosure can be reduced, compared to field effect transistors having other structures.
A semiconductor device according to one embodiment of the present disclosure can be applied to electronic parts such as, for example, a radio frequency (RF) module, a power conversion module which uses a high voltage, and the like. Also, a semiconductor device according to one embodiment of the present disclosure can improve the performance of electronic apparatuses including the above electronic parts such as an alternating current (AC) adaptor, power conditioner, smartphone, mobile telephone, and the like.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Further, the effects described in this specification are merely illustrative or exemplified effects, and are not limitative. That is, with or in the place of the above effects, the technology according to the present disclosure may achieve other effects that are clear to those skilled in the art based on the description of this specification.
Additionally, the present technology may also be configured as below.
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| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-009797 | Jan 2016 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2017/001014 | 1/13/2017 | WO | 00 |
