Patent Application
20070243701
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-112194, filed Apr. 14, 2006, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an annealing step of semiconductor device fabrication steps and, more particularly, to a semiconductor device fabrication method which uses an ultra-rapid thermal annealing step whose heating/cooling rate is 1×105° C./sec or more, in order to form a semiconductor element having, in at least a portion, an impurity diffusion layer whose junction depth is smaller than 20 nm.
2. Description of the Related Art
The performance of a semiconductor device, particularly, an LSI can be improved by increasing the integration density, i.e., by micropatterning elements forming the LSI. As the degree of micropatterning of elements increases, however, the parasitic resistance and short-channel effect of a MOSFET increase. Therefore, the formation of a shallow low-resistance impurity diffusion layer is becoming more and more important.
A known method of forming a shallow impurity diffusion layer is to optimize ion implantation at low acceleration energy and an annealing step performed after that. On the other hand, to decrease the resistance of the impurity diffusion layer described above, annealing for activating the impurity must be performed at a high temperature.
Unfortunately, a normally used impurity such as boron (B), phosphorus (P), or arsenic (As) has a large diffusion coefficient in silicon (Si), so an RTA (Rapid Thermal Annealing) process using a halogen lamp causes in-diffusion and out-diffusion of impurity ions. This gradually makes it difficult to form shallow impurity diffusion layers.
The in-diffusion and out-diffusion described above can be suppressed by lowering the annealing temperature. If the annealing temperature is lowered, however, the activation yield of an impurity significantly decreases. This makes it difficult for the RTA process using a halogen lamp to form a low-resistance impurity diffusion layer having a shallow junction of 20 nm or less.
To solve these problems, therefore, as a method of instantaneously supplying energy necessary for impurity activation, an annealing method using a flash lamp in which a rare gas such as xenon (Xe) is sealed is being studied in recent years (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2003-59854 or 2003-309079). The flash lamp can emit light with a pulse width of 100 msec or less, and the smallest pulse width is sub-msec. Annealing performed for this short time period can activate impurity ions implanted into the major surface of a wafer while the distribution of the impurity ions remains almost unchanged.
The conventional flash lamp annealing method, however, requires a large irradiation energy of 20 J/cm2 or more in order to well activate an impurity. Consequently, an abrupt temperature rise occurs on the wafer surface; the wafer surface temperature instantaneously reaches 1,200° C. or more. This produces a large temperature difference between the upper and lower surfaces of the wafer, and increases the internal thermal stress of the wafer. This increase in thermal stress causes damages such as slip dislocations, fracture, and deformation of the wafer, thereby decreasing the fabrication yield.
As described above, the present flash lamp annealing method has a narrow process window, and this makes it difficult to form a shallow impurity diffusion layer without damaging the wafer.
According to an aspect of the present invention, there is provided a semiconductor device fabrication method comprising ion-implanting an impurity into a major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm−3, a bulk microdefect size smaller than 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm−3, and annealing the Si substrate at a heating/cooling rate higher than 1×105° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.
According to another aspect of the present invention, there is provided a semiconductor device fabrication method comprising performing annealing for fixation on an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm−3, a bulk microdefect size of 10 to 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm−3 for a time during which an annealing temperature T and an annealing time t have a relationship indicated by t=2×104 exp (−0.0124T), in order to suppress changes in bulk microdefect density and bulk microdefect size, ion-implanting an impurity into a major surface of the Si substrate, and annealing the Si substrate at a heating/cooling rate of 1×105° C./sec to 1×107° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.
According to still another aspect of the present invention, there is provided a semiconductor device fabrication method comprising ion-implanting an impurity into a major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm−3, a bulk microdefect size of 10 to 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm−3 in at least a region not more than 2 mm from an outer periphery, and annealing the Si substrate at a heating/cooling rate of 1×105° C./sec to 1×107° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.
The process of consideration reaching the present invention will be explained first, and then semiconductor device fabrication methods according to the first and second embodiments will be explained.
Bit-like microdefects (Crystal Originated Particles: COPs) as the formation marks of voids exist on the surface of an Si substrate grown by the Czochralski: CZ) method, and have an adverse effect on the device characteristics. A known method of reducing these microdefects is to perform high-temperature annealing in a hydrogen or argon ambient. This method can form a defect-free layer from the major surface of a substrate to a device active layer having a depth exceeding 10 μm.
Also, in a wafer fabrication process of the CZ method, a large amount of oxygen elutes from a crucible made of quartz and becomes entrapped as interstitial oxygen in Si crystals. This interstitial oxygen condenses in the high-temperature annealing process described above, and forms oxygen deposits (Bulk Microdefects: BMDs) in a bulk portion having a depth of 10 μm or more. These BMDs formed inside the substrate presumably have a gettering function. Conventionally, the BMDs are formed at a high density in order to increase the device yield.
On the other hand, the present inventors inspected, by speculation and experiments, the conventionally unexamined relationship between the concentration of the interstitial oxygen, the density and size of the bulk microdefects, and the heating/cooling rate of ultra-rapid thermal annealing. Consequently, the present inventors have established a method of ensuring wafer strength by suppressing slip dislocations and brittle fracture by a fabrication method which optimizes the density and size of oxygen deposits of an Si substrate and the heating/cooling rate of annealing when forming a low-resistance impurity diffusion layer having a shallow junction.
The semiconductor device fabrication methods according to the first and second embodiments of the present invention will now be explained by taking MOSFET fabrication steps as an example.
The semiconductor device fabrication method according to the first embodiment of the present invention will be explained below by taking fabrication steps (post-extension process) of a MOSFET as a basic element forming an LSI as an example.
First, an Si substrate 1 having a bulk microdefect (BMD) density of 5×106 to 5×107 cm−3, a BMD size smaller than 100 nm, and a dissolved oxygen concentration (Oi) of 1.1×1018 to 1.2×1018 cm−3 is prepared. As shown in
Then, a gate insulating film 3 made of SiO2 or SiON (N concentration in surface layer <15%) is formed on the major surface of the Si substrate 1. A polysilicon (poly-Si) layer or polysilicon germanium (poly-SiGe) layer having a thickness of 50 to 150 nm is formed on the gate insulating film 3 by LP-CVD. The Ge concentration in the polysilicon germanium layer is 10% to 30%. P or As is ion-implanted into the polysilicon layer or polysilicon germanium layer when forming an n-channel MOSFET, and B is ion-implanted into the layer when forming a p-channel MOSFET, at a concentration of 3×1015 to 8×1015 cm−2. The obtained layer is patterned into the shape of a gate electrode 4 by using photolithography and reactive ion etching.
Subsequently, an SiO2 film and Si3N4 film are formed on the entire surface and selectively left behind on the side surfaces of the gate electrode 4 by etch back using reactive ion etching. This step forms sidewall spacers 5 and 6 made of SiO2 and Si3N4. The sidewall spacers 5 and 6 prevent a silicide reaction in a subsequent step.
After that, the method of post-extension process is used to ion-implant a desired amount of a desired impurity into source/drain regions 7 and their extended portions (extension regions) 8. In this step, the ions are implanted into the gate electrode 4 as well. Finally, the gate electrode 4 contains the impurity P or impurities As and B of the principal conductivity type at a concentration of about 5×1015 to 1×1016 cm−2.
Then, a flash lamp or laser is used to perform ultra-rapid thermal annealing whose heating/cooling rate is higher than 1×105° C./sec, thereby electrically activating the impurity doped into the source/drain regions 7, extension regions 8, and gate electrode 4. In this ultra-rapid thermal annealing step, as shown in
Consequently, as shown in
Note that in the above explanation, the impurity doped into the source/drain regions 7, extension regions 8, and gate electrode 4 is electrically activated by ultra-rapid thermal annealing. However, it is also possible to perform annealing at a low temperature for a relatively long time by using the existing RTA apparatus before the formation of the extension regions 8, thereby diffusing and activating the implanted impurity in the source/drain regions 7 and gate electrode 4. After that, the impurity is ion-implanted into the extension regions 8, and the implanted impurity in the extension regions 8 is diffused and activated by performing ultra-rapid thermal annealing under the above-mentioned conditions. In this fabrication method, the RTA process removes defects produced by the ion implantation of the impurity into the source/drain regions 7. This reduces the variations in fabrication and stabilizes the characteristics of the MOSFET.
Although fabrication steps after that are not shown, an Ni film, a Co film, a Pt film, a Pd film, or a metal film mainly containing an alloy of these metals is vapor-deposited to have a thickness of 10 nm or less in a salicide step, thereby selectively forming NiSi, NiSi2, CoSi, CoSi2, PtSi, or Pd2Si in the exposed portions of Si or SiGe. Subsequently, unreacted Ni is removed by hydrolysis by addition of sulfuric acid, a silicon oxide film serving as an interlayer dielectric film is deposited, and contact holes are formed in those portions of the silicon oxide film which correspond to the source/drain regions 7 and gate electrode 4. Then, a metal layer or the like is formed on the silicon oxide film and in the contact holes and patterned to form interconnections connecting to the gate electrode 4 and source/drain regions 7 through the contact holes.
A semiconductor device in which the MOSFET having the shallow extension regions (impurity diffusion layers) 8 of 20 nm or less is formed is completed by the fabrication steps as described above.
The semiconductor device (MOSFET) formed by the fabrication method of the first embodiment and Comparative Examples 1 to 5 in which similar semiconductor devices were formed by using Si substrates different in bulk microdefect density, bulk microdefect size, and dissolved oxygen concentration will be explained below.
A MOSFET was formed on an Si substrate having a bulk microdefect [BMD] density of 7×107 cm−3 or more, a BMD size of 100 nm or less, and a dissolved oxygen concentration [Oi] of 1.3×1018 cm−3 or more.
A MOSFET was formed on an Si substrate having a bulk microdefect [BMD] density of 3×107 cm−3 or more, a BMD size of 100 nm or less, and a dissolved oxygen concentration [Oi] of 1.1×1018 cm−3 or less.
A MOSFET was formed on an Si substrate having a bulk microdefect [BMD] density of 1×106 to 1×107 cm−3, a BMD size of 100 nm or less, and a dissolved oxygen concentration [Oi] of 1.3×1018 cm−3 or more.
A MOSFET was formed on an Si substrate having a bulk microdefect [BMD] density of 1×107 cm−3 or less, a BMD size of 100 nm or less, and a dissolved oxygen concentration [Oi] of 1.1×1018 cm−3 or less.
A MOSFET was formed on an Si substrate having a bulk microdefect [BMD] density of 1×107 cm−3 or more, a BMD size of 100 nm or more, and a dissolved oxygen concentration [Oi] of 1.1×1018 cm−3 or more.
(Evaluation)
When the MOSFETs were formed on the Si substrates of the first embodiment and Comparative Examples 1 to 5, deformation or slip dislocations were found in the Si substrates of Comparative Examples 1 to 5 in the ultra-rapid thermal annealing step (in this embodiment, the flash lamp annealing step), and this increased the probability of breakage. In the first embodiment, however, none of deformation, slip dislocations, and wafer cracking occurred in the Si substrate, so it was possible to form a micropatterned MOSFET having high driving power.
The following findings were obtained by analyzing the semiconductor device fabrication method according to the first embodiment and the Si substrates of the comparative examples after the flash lamp annealing step.
When the Si substrate which was processable without any cracking at a BMD density of 1×108 cm−3 or more was evaluated by an X-ray topograph, fine white brilliant points were observed at a high density, indicating the occurrence of X-ray scattering. When the brilliant points were observed with a sectional TEM, a large number of dislocation-like defects were observed in the <111> direction, and these defects reached a depth of 100 μm or more from the surface. In addition, the deformation amount of the Si substrate increased as the BMD density and BMD size increased.
The differences between the obtained results will be theoretically considered below by comparing the first embodiment with the comparative examples.
In the Si substrate (
In the Si substrate (
Generally, when the dissolved oxygen concentration in an Si substrate increases, oxygen diffuses or adheres and effectively stops the advance or movement of slip dislocations.
This presumably has influence on wafer cracking in the Si substrate having a low dissolved oxygen concentration [Oi] of 1.1×1018 cm−3 or less as in [Comparative Example 2] or [Comparative Example 4].
However, wafer cracking was serious in the Si substrate having a high dissolved oxygen concentration [Oi] of 1.3×1018 cm−3 or more as in [Comparative Example 1] or [Comparative Example 3] as well. This is so perhaps because in the heating step, before the ultra-rapid thermal annealing step using the flash lamp, of the semiconductor device fabrication steps, oxygen condensed and deposited inside the substrate to increase the BMD density or accelerate the growth of BMDs, thereby adversely affecting wafer cracking.
The above results indicate that when performing ultra-rapid thermal annealing whose heating/cooling rate is higher than 1×105° C./sec, the BMD density and dissolved oxygen concentration inside the Si substrate have influence on wafer cracking if they are too low or too high, so it is probably favorable to maintain each value at a value controlled within a certain range. It is also favorable to maintain the BMD density and BMD size at values controlled within certain ranges.
The results of the experiments demonstrate that a hatched region 14 shown in
On the other hand, the dissolved oxygen concentration is preferably high because dissolved oxygen has a function of increasing the crystal strength and adhering slip dislocations. If the dissolved oxygen concentration is too high, however, dissolved oxygen often condenses and deposits (to form BMD seeds) in a high-temperature annealing process during the course of LSI fabrication. Accordingly, a favorable application range of the dissolved oxygen concentration [Oi] is probably 1.1×1018 cm−3<[Oi]<1.2×1018 cm−3.
The range of the heating/cooling rate [T1] of ultra-rapid thermal annealing described above is preferably 1×105° C.<[α]<1×107° C. for the following reasons. That is, if this heating/cooling rate is 1×105° C. or less, impurity diffusion increases to become no longer negligible. If the heating/cooling rate is 1×107° C. or more, the load on the annealing apparatus increases to make ultra-rapid thermal annealing difficult to perform.
Furthermore, the range of the temperature [T2] of the major surface of the Si substrate 1 resulting from ultra-rapid thermal annealing is preferably 1,000° C.<[T2]<1,400° C. If this temperature is 1,000° C. or less, no desired high-concentration activation can be expected. If the temperature is 1,400° C. or more, the Si substrate 1 melts.
The BMD size [SZ] preferably falls within the range of 10 nm<[SZ]<100 nm. If the BMD size is 10 nm or less, BMDs do not act as slip dislocation sources. When the BMD size is larger than 10 nm, BMDs act as slip dislocation sources and achieve the capability of inhibiting the advance of slip dislocations and the gettering effect. If the BMD size is 100 nm or more, however, BMDs act as slip dislocation sources but cannot inhibit the movement of slip dislocations any longer.
A semiconductor device fabrication method according to the second embodiment of the present invention will be explained below. The second embodiment differs from the first embodiment in that a semiconductor element (MOSFET) is fabricated after a pre-processing step (fixation annealing) for maintaining a state in which the BMD density of an Si substrate 1 is 5×106 to 5×107 cm−3 and the BMD size of the substrate is smaller than 100 nm is performed in a step before flash lamp annealing.
As explained in the first embodiment described above, even when an Si substrate in which the BMD density is controlled within a certain range is used, BMDs may change in the heating step performed before flash lamp annealing during the process of fabricating a semiconductor device. Generally, interstitial oxygen dissolved in the Si substrate 1 condenses and deposits through a high-temperature, long-time heating step. That is, the heating step accelerates the nucleation and growth of BMDs and increases the density and size of the BMDs as shown in
In the semiconductor device fabrication method according to the second embodiment, therefore, fixation annealing is performed at a temperature of 600° C. to 800° C. for 3 hrs or less in order to suppress changes in BMD density and BMD size particularly in a step before flash lamp annealing. An annealing temperature of about 600° C. is necessary to fabricate a high-quality LSI (having high driving power and high reliability). An annealing temperature of 800° C. or less is too low to cause the growth of BMD nuclei. If the annealing temperature is 800° C. or more, both the BMD density and size increase.
As shown in
In semiconductor device fabrication steps, various annealing steps are performed to, e.g., densify STI and activate an impurity in addition to CVD steps for forming a gate insulating film, gate polysilicon, gate sidewall spacers, and the like. Conventionally, a thermal budget irrelevant to BMD suppression is assumed. However, the second embodiment performs a thermal budget in a nitrogen gas ambient at a temperature of 600° C. to 800° C. for 3 hrs or less. This suppresses the formation and growth of BMDs, and makes it possible to fabricate a semiconductor device without any technical difficulty (e.g., a wafer annealing step can be changed from furnace batch processing to single wafer processing).
By setting the process conditions as described above, as shown in
Note that the first and second embodiments described above have explained the annealing apparatus using the xenon flash lamp as a light source for emitting light. However, the present invention is not limited to these embodiments. For example, the present invention is also applicable to flash lamps using another rare gas, mercury, and hydrogen, and light sources such as an arc discharge lamp, excimer laser, Ar laser, N2 laser, YAG laser, titanium sapphire laser, CO laser, and CO2 laser.
Also, the present invention has been explained by taking the MOSFET fabrication method as an example. However, the present invention is similarly applicable to all semiconductor elements having, in at least a portion, a low-resistance impurity diffusion layer with a shallow junction of 20 nm or less.
Furthermore, when an Si substrate is annealed at a heating/cooling rate of 1×105° C./sec to 1×107° C./sec in the LSI fabrication process, slip dislocations or crack-like marks easily form in a region 2 mm from the outer periphery of the Si substrate (see the temperature distribution shown in
As described above, one aspect of the present invention can ensure wafer strength against slip dislocations and brittle fracture caused by ultra-rapid thermal annealing. This makes it possible to widen the process window and stabilize the process. Also, a shallow low-resistance diffusion layer can be formed without any damage. Since this facilitates micropatterning, a high-performance MOSFET can be fabricated. This increases the fabrication yield and stabilizes the operation of fabrication steps.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-112194 | Apr 2006 | JP | national |
