1. Field of the Invention
The present invention relates to a power semiconductor device, and more particularly, to a power semiconductor device capable of improving voltage spike effect produced during switching and stability of the manufacturing process.
2. Description of the Prior Art
A trench power transistor is a typical semiconductor device in power management application, such as switching power supplies, power control ICs of computer systems or peripherals, power supplies of backlight, motor controllers, etc. With the high switching speed of the trench power transistor, a voltage spike effect produced during switching may affect operating performance. Therefore, to solve the above-mentioned problem, the ratio of the input capacitance to the reverse transfer capacitance of the trench power transistor needs to be enhanced to an optimal value for suppressing the voltage spike effect.
In order to improve the voltage spike effect produced during switching, the prior art provides modifications on the structure of the trench power transistor to optimize the ratio of the input capacitance to the reverse transfer capacitance. For example, U.S. Pat. No. 7,253,473, U.S. Pat. No. 7,037,788, U.S. Pat. No. 6,809,349, U.S. Pat. No. 6,806,548, and U.S. Pat. No. 6,777,295 disclose trench semiconductor devices which form a gate electrode upon the trench surface by reducing the trench depth, so as to enhance the ratio of the input capacitance to the reverse transfer capacitance of the trench power transistor. However, through the above-mentioned structures, several problems, such as non-uniform implant or unusual P-N junction avalanche, often occur.
It is therefore a primary objective of the claimed invention to provide a power semiconductor device.
The present invention discloses a power semiconductor device, which comprises a backside metal layer, a substrate, a semiconductor layer, and a frontside metal layer. The substrate is formed on the backside metal layer. The semiconductor layer is formed on the substrate, which comprises a first trench structure, a second trench structure, a p-base region, a plurality of n+ source regions, and a dielectric layer. The first trench structure comprises a gate oxide layer formed around a first trench with poly-Si implant. The second trench structure comprises a gate oxide layer formed around a second trench with poly-Si implant. The p-base region is formed between the first trench structure and the second trench structure. The plurality of n+ source regions is formed on the p-base region and between the first trench structure and the second trench structure. The dielectric layer is formed on the first trench structure, the second trench structure, and the plurality of n+ source regions. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source regions on the p-base region.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
a) is a top-view diagram illustrating a layout of the trench power transistor according to an embodiment of the present invention.
b) is a 3D structural diagram illustrating a layout of the trench power transistor according to an embodiment of the present invention.
a) is a top-view diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
b) is a 3D structural diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
a) is a top-view diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
b) is a 3D structural diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
a) is a top-view diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
b) is a 3D structural diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
a) is a top-view diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
b) is a 3D structural diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
a) is a top-view diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
b) is a 3D structural diagram illustrating a layout of the trench power transistor according to another embodiment of the present invention.
Please refer to
In the semiconductor layer 104, the first trench structure 201 and the second trench structure 202 form gates of the trench power transistor 10, the n+ source regions n_1˜n_k form sources of the trench power transistor 10, and the backside metal layer 101 forms a drain of the trench power transistor 10. Preferably, the first trench structure 201 includes a top end extension region P extended from top end of the first trench 210 to both sides of the first trench 210 with poly-Si implant. In addition, the gaps formed by the plurality of n+ source regions n_1˜n_k on the p-base region 204 are separated from the top end extension region P and not overlapped with the top end extension region P. In an embodiment of the present invention, after the substrate 102 and the semiconductor layer 104 are formed in the manufacturing process of the trench power transistor 10, the first trench structure 201 and the second trench structure 202 are formed on the semiconductor layer 104. Again, the p-base region 204 and the plurality of n+ source regions n_1˜n_k are formed with tilt implant respectively. Finally, the etching process is performed to form contact holes for completing the backside metal layer 101 and the frontside metal layer 106. Preferably, the material of the frontside metal layer 106 can be aluminum (Al).
The embodiment of the present invention can improve non-uniform implant caused by mask offset or alignment error, while forming the p-base region 204 and the plurality of n+ source regions n_1˜n_k with tilt implant. Please refer to
Note that, the layout of the trench power transistor 10 in
In summary, through changing the layout approach and structure mode of the trench power transistor 10, the present invention can improve the miller effect for reducing voltage spike effect produced during switching and avoid non-uniform implant for reducing unusual P-N junction avalanche and enhancing stability of manufacturing process.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Number | Date | Country | Kind |
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097143307 | Nov 2008 | TW | national |