Patent Application
20250015149
The present disclosure relates to a semiconductor device for power amplification.
Patent Literature (PTL) 1 discloses a high-electron-mobility transistor (HEMT) that uses two-dimensional electron gas (2DEG) as a channel.
The properties of semiconductor devices such as high-electron-mobility transistors degrade due to heat generated during operation.
In view of this, the present disclosure provides a semiconductor device for power amplification that is capable of reducing property degradation due to heat.
A semiconductor device for power amplification according to one aspect of the present disclosure comprising: a substrate; a lower electrode provided below the substrate; a semiconductor layer that is provided above the substrate and includes a plurality of active layers comprising group-III nitride, and in which two-dimensional electron gas is produced in a hetero interface of the plurality of active layers; a source electrode and a drain electrode that are provided above the semiconductor layer, spaced apart from each other, and electrically connected to the two-dimensional electron gas; a gate electrode that is spaced apart from the source electrode and the drain electrode and is in contact with the semiconductor layer; a gate finger that is in contact with and covers all of a plurality of gate electrodes arranged linearly in a first direction, the plurality of gate electrodes each being the gate electrode; and a drain finger that is in contact with and covers all of a plurality of drain electrodes arranged linearly in the first direction, the plurality of drain electrodes each being the drain electrode, wherein a plurality of gate fingers are arranged in a second direction orthogonal to the first direction and supplied with a same electric potential, the plurality of gate fingers each being the gate finger, in a plan view of the substrate, the semiconductor layer is divided into an active region containing the two-dimensional electron gas and an isolation region not containing the two-dimensional electron gas, in the plan view, a channel region includes a plurality of unit channel regions that are separated by the isolation region and arranged in the first direction, the channel region being an overlapping portion of the active region and the plurality of gate electrodes, the source electrode includes a plurality of unit source electrodes each of which faces a corresponding one of the plurality of unit channel regions, a plurality of unit source regions each include at least one source via that contains a conductor that penetrates through the substrate and the semiconductor layer and is in contact with the lower electrode that is supplied with a same electric potential as an electric potential supplied to the source electrode, the plurality of unit source regions each including a corresponding one of the plurality of unit source electrodes, and in the plan view, a length of a side of a minimum rectangular region in the second direction is greater than a length of a side of the minimum rectangular region in the first direction, the minimum rectangular region surrounding the at least one source via.
A semiconductor device for power amplification according to the present disclosure makes it possible to reduce property degradation due to heat.
These and other advantages and features will become apparent from the following description thereof taken in conjunction with the accompanying Drawings, by way of non-limiting examples of embodiments disclosed herein.
Hereinafter, an embodiment is described in detail with reference to the Drawings.
It should be noted that the embodiment described below shows a generic or specific example. The numerical values, shapes, materials, constituent elements, the arrangement and connection of constituent elements, steps, the order of steps, etc. indicated in the following embodiment are mere examples and are not intended to limit the present disclosure. In addition, among the constituent elements in the following embodiment, constituent elements not recited in any one of the independent claims are described as arbitrary constituent elements.
Moreover, the respective figures are schematic diagrams and are not necessarily precise illustrations. Accordingly, the figures are not necessarily to scale etc. Furthermore, for example, in each figure, the thickness, size, etc. of a constituent element may be exaggerated for the sake of easy-to-understand explanation. Additionally, the same reference signs are assigned to substantially identical elements in the respective figures, and overlapping descriptions thereof are omitted or simplified.
Moreover, in this Specification, terms indicating the relationship between elements such as parallel or orthogonal, terms indicating the shape of elements such as rectangular or circular, and numerical ranges are not expressions that indicate only the strict meaning but are expressions that mean a substantially equivalent range, and include, for example, an error of approximately several percent.
Furthermore, in this Specification, the terms “above” and “below” do not refer to the upward (vertically upward) direction and downward (vertically downward) direction in terms of absolute spatial recognition, and are used as terms defined by relative positional relationships based on the stacking order of a stacked configuration. In addition, the terms “above” and “below” are applied not only when two constituent elements are arranged at intervals without another constituent element located between the two constituent elements, but also when two constituent elements are arranged adjacent to each other.
Moreover, in this Specification and the drawings, an X-axis, a Y-axis, and a Z-axis represent three axes in a three-dimensional orthogonal coordinate system. In each embodiment, a Z-axis direction is defined as the thickness direction of a substrate. In addition, in this Specification, the “thickness direction” means the thickness direction of a substrate and refers to a direction perpendicular to the principal surface of the substrate. A Y-axis direction is an example of a first direction, and is a direction in which a gate finger and a drain finger extend. An X-axis direction is an example of a second direction, and is a direction in which a source electrode, a gate electrode, and a drain electrode are arranged in stated order. Additionally, unless otherwise noted, a “plan view” refers to a view from the direction perpendicular to the principal surface of the substrate.
Furthermore, in this Specification, a layer that comprises group-III nitride is a semiconductor layer that contains at least one type of group-III elements and nitrogen. Examples of a group-III element include aluminum (AI), gallium (Ga), and indium (In). Examples of group-III nitride include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group-III nitride may contain at least one type of elements other than a group-III element, such as silicon (Si) and phosphorus (P). It should be noted that, in the following description, unless otherwise noted, when group-III nitride is expressed as AlInGaN, such an expression means that the group-III nitride contains all of Al, In, Ga, and N. The same applies to other expressions such as AlGaN and GaN.
Moreover, a layer that comprises group-III nitride means that the layer contains substantially only the group-III nitride. However, the layer may contain, as impurities, other elements such as elements the mixing of which is inevitable in manufacturing, at a rate of at most 1%.
Furthermore, in this Specification, unless otherwise noted, the ordinal such as “first” and “second” does not mean the number or order of constituent elements, and is used for the purpose of avoiding confusion about constituent elements of the same type and distinguishing them from each other.
First, a configuration of a semiconductor device for power amplification according to an embodiment is described with reference to
Semiconductor device for power amplification 1 shown in
Semiconductor device for power amplification 1 according to the embodiment is used as, for example, a high-frequency transistor. For example, semiconductor device for power amplification 1 is applicable to a mobile phone and a power amplifier of a communication device included in a base station etc.
Semiconductor device for power amplification 1 has a configuration in which single unit portions of a transistor are repeatedly arranged in a matrix in a two-dimensional plane (specifically an XY plane). A single unit portion of the transistor is a portion that includes unit channel region 90, gate electrode 40, drain electrode 50, and unit source region 92 (specifically source electrode 60, source via 70, etc.) shown in
As shown in
Substrate 10 is a Si (silicon) substrate, but is not limited to this example. Substrate 10 may be a sapphire substrate, a SiC (silicon carbon) substrate, or a GaN substrate.
Semiconductor layer 20 is provided above substrate 10 and includes a plurality of active layers that comprise group-III nitride. The group-III nitride is, for example, GaN nitride. Two-dimensional electron gas 22 is produced in a hetero interface of the plurality of active layers. It should be noted that two-dimensional electron gas 22 is schematically indicated by the dashed line in
The plurality of active layers are, for example, two GaN semiconductor layers each of which has a different band gap. As shown in
Semiconductor layer 20 includes a channel region that contains at least part of two-dimensional electron gas 22. The channel region is an overlapping portion of active region 31 and the plurality of gate electrodes 40 in the plan view. The channel region is a portion of a current pathway between drain electrode 50 and source electrode 60 in semiconductor device for power amplification 1, and is a region the conduction and non-conduction of which is controlled by gate electrode 40. The channel region includes a plurality of unit channel regions 90 that are separated by isolation region 30 and arranged in the X-axis direction.
It should be noted that semiconductor layer 20 may include a layer other than the plurality of active layers. For example, the layer other than the plurality of active layers is a layer that comprises GaN, AlGaN, InGaN, InAlGaN, AlN, or InN, etc. For example, semiconductor layer 20 may include a buffer layer disposed between substrate 10 and GaN layer 24. Such a buffer layer makes it possible to improve the film quality of GaN layer 24 and AlGaN layer 26. Each layer included in semiconductor layer 20 is formed by an epitaxial growth method.
Isolation region 30 is a region not containing two-dimensional electron gas 22. Isolation region 30 separates the channel region of semiconductor layer 20 into the plurality of unit channel regions 90 that are arranged in the Y-axis direction. A unit channel region may be referred to as a separated channel region. As shown in
Isolation region 30 is formed in a region that includes at least a hetero interface between GaN layer 24 and AlGaN layer 26 that have been epitaxially grown, that is, a region in which two-dimensional electron gas 22 is produced. Isolation region 30 is formed by inactivating a portion of semiconductor layer 20 by ion implantation. For example, isolation region 30 is formed by implanting ions of Ar (argon), B (boron), He (helium), etc. into the region including at least the hetero interface between GaN layer 24 and AlGaN layer 26 that have been epitaxially grown. Two-dimensional electron gas 22 is not produced in isolation region 30.
Alternatively, isolation region 30 may be formed by removing, by etching, GaN layer 24 and AlGaN layer 26 that have been epitaxially grown, to at least a depth at which two-dimensional electron gas 22 is produced. For example, isolation region 30 may be an insulating layer formed in a portion removed from GaN layer 24 and AlGaN layer 26.
Gate electrode 40 is spaced apart from source electrode 60 and drain electrode 50, and is in contact with semiconductor layer 20. In addition, gate electrode 40 is electrically connected to gate finger 42, and is disposed between gate finger 42 and semiconductor layer 20. Specifically, gate electrode 40 is an electrode in Schottky contact with semiconductor layer 20. Gate electrode 40 is a control electrode of semiconductor device for power amplification 1. Specifically, semiconductor device for power amplification 1 is capable of switching between conduction and non-conduction of unit channel region 90 according to a gate electric potential applied to gate electrode 40 via gate finger 42. When semiconductor device for power amplification 1 is operating, for example, a gate electric potential ranging from −1.5 V to approximately −3 V is applied to gate electrode 40. It should be noted that the magnitude of a gate electric potential is not particularly limited as long as the gate electric potential enables semiconductor device for power amplification 1 to operate.
In the present embodiment, the plurality of gate electrodes 40 are linearly arranged in the Y-axis direction. Each of the plurality of gate electrodes 40 is in an elongated shape in the Y-axis direction and lies on a straight line in the Y-axis direction. In other words, the plurality of gate electrodes 40 are obtained by separating one long gate electrode that extends in the Y-axis direction into a plurality of gate electrodes that are spaced apart. For this reason, gate electrode 40 can be also referred to as a separated gate electrode or a unit gate electrode.
Moreover, the plurality of gate electrodes 40 are provided for each gate finger 42. To put it another way, the plurality of gate electrodes 40 are arranged not only in the Y-axis direction but also in the X-axis direction. In short, gate electrodes 40 are repeatedly arranged in a matrix in a two-dimensional plane (specifically an XY plane).
Gate electrode 40 is formed using a conductive material. For example, gate electrode 40 is a single layer or a stack that comprises a metal, an alloy, or conductive metal nitride. Examples of the metal include Ti (titanium), Ta (tantalum), W (tungsten), Ni (nickel), Pd (palladium), Au (gold), and Al. Examples of the conductive metal nitride include TiN and TaN. Gate electrode 40 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc.
Gate finger 42 is provided above semiconductor layer 20 and extends in the Y-axis direction. Gate finger 42 is provided above the plurality of gate electrodes 40 linearly arranged in the Y-axis direction, and is in contact with and covers all of the plurality of gate electrodes 40. In the present embodiment, as shown in
Gate finger 42 has, for example, a cross-sectional area of an XZ cross section larger than that of gate electrode 40. For example, as shown in
Gate finger 42 is formed using a conductive material. For example, gate finger 42 may be formed using a material having a conductivity higher than that of the material of gate electrode 40. Accordingly, it is possible to further reduce gate resistance Rg. As an example, gate finger 42 is formed using Al, Au, or Cu (copper). Gate finger 42 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc.
In the present embodiment, the plurality of gate fingers 42 are arranged in the X-axis direction and supplied with the same electric potential. For example, the plurality of gate fingers 42 are parallel to each other and arranged at prescribed intervals. As an example, the plurality of gate fingers 42 are arranged to cause gate pitches (see
Gate bus 44 is an integrating line that integrates the plurality of gate fingers 42 and extends in the X-axis direction. Gate bus 44 may be integrally formed using the same material as the material of the plurality of gate fingers 42. Gate bus 44 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc.
Although gate bus 44 is provided on the negative side of the Y-axis direction in the present embodiment, gate bus 44 may be provided on a positive side of the Y-axis direction or on both the positive and negative sides of the Y-axis direction.
Drain electrode 50 is provided above semiconductor layer 20, and is electrically connected to two-dimensional electron gas 22. In addition, drain electrode 50 is electrically connected to drain finger 52, and is disposed between drain finger 52 and semiconductor layer 20. Specifically, drain electrode 50 is an electrode that is ohmic connected to two-dimensional electron gas 22 of semiconductor layer 20. A drain electric potential is supplied to drain electrode 50 via drain finger 52. When semiconductor device for power amplification 1 is operating, for example, a drain electric potential of approximately 150 V at most may be applied to drain electrode 50. It should be noted that the magnitude of a drain electric potential is not particularly limited as long as the drain electric potential enables semiconductor device for power amplification 1 to operate.
In the present embodiment, the plurality of drain electrodes 50 are linearly arranged in the Y-axis direction. Each of the plurality of drain electrodes 50 is in an elongated shape in the Y-axis direction and lies on a straight line in the Y-axis direction. In other words, the plurality of drain electrodes 50 are obtained by separating one long drain electrode that extends in the Y-axis direction into a plurality of drain electrodes that are spaced apart. For this reason, drain electrode 50 can be also referred to as a separated drain electrode or a unit drain electrode.
Moreover, the plurality of drain electrodes 50 are provided for each drain finger 52. To put it another way, the plurality of drain electrodes 50 are arranged not only in the Y-axis direction but also in the X-axis direction. In short, drain electrodes 50 are repeatedly arranged in a matrix in a two-dimensional plane (specifically the XY plane).
Drain electrode 50 is formed using a conductive material. For example, drain electrode 50 is a single layer or a stack that comprises a metal or an alloy. Examples of the metal include Ti, Al, and Au. Drain electrode 50 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc.
Drain finger 52 is provided above semiconductor layer 20 and extends in the Y-axis direction. Drain finger 52 is provided above the plurality of drain electrodes 50 linearly arranged in the Y-axis direction, and is in contact with and covers all of the plurality of drain electrodes 50. Drain finger 52 is a line for supplying a drain electric potential to drain electrode 50. To put it another way, drain finger 52 can be referred to as a drain drive line for driving drain electrode 50.
Drain finger 52 has, for example, a cross-sectional area of an XZ cross section larger than that of drain electrode 50. For example, as shown in
Drain finger 52 is formed using a conductive material. For example, drain finger 52 may be formed using a material having a conductivity higher than that of the material of drain electrode 50. Accordingly, it is possible to further reduce drain resistance Rd. As an example, drain finger 52 is formed using Al, Au, or Cu. Drain finger 52 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc.
In the present embodiment, the plurality of drain fingers 52 are arranged in the X-axis direction and supplied with the same electric potential. For example, the plurality of drain fingers 52 are parallel to each other and arranged at regular intervals. An end portion of each of the plurality of drain fingers 52 on the positive side of the Y-axis direction is connected to drain bus 54 (see
Drain bus 54 shown in
Although drain bus 54 is provided on the positive side of the Y-axis direction in the present embodiment, drain bus 54 may be provided on the negative side of the Y-axis direction or on both the positive and negative sides of the Y-axis direction. Drain but 54 may be provided on the same side as gate bus 44.
Source electrode 60 is provided above semiconductor layer 20, spaced apart from drain electrode 50, and electrically connected to two-dimensional electron gas 22. Source electrode 60 is disposed to sandwich gate electrode 40 between source electrode 60 and drain electrode 50. Specifically, source electrode 60 is an electrode that is ohmic connected to two-dimensional electron gas 22 of semiconductor layer 20. A source electric potential is supplied to source electrode 60 via lower electrode 64, source via 70, and source connector 62. A source electric potential is, for example, an electric potential lower than a drain electric potential. When semiconductor device for power amplification 1 is operating, for example, a source electric potential of 0 V is applied to source electrode 60. It should be noted that the magnitude of a source electric potential is not particularly limited as long as the source electric potential enables semiconductor device for power amplification 1 to operate.
In the present embodiment, the plurality of source electrodes 60 are arranged in the Y-axis direction. Each of the plurality of source electrodes 60 is in an elongated shape in the Y-axis direction and lies on a straight line in the Y-axis direction. In other words, the plurality of source electrodes 60 are obtained by separating one long source electrode that extends in the Y-axis direction into a plurality of source electrodes that are spaced apart. For this reason, source electrode 60 can be also referred to as a separated source electrode or a unit source electrode.
The plurality of source electrodes 60 are provided for each unit channel region 90. Specifically, source electrode 60 is provided for each unit source region 92 that faces unit channel region 90. In the present embodiment, the plurality of source electrodes 60 are arranged not only in the Y-axis direction but also in the X-axis direction. In short, source electrodes 60 are repeatedly arranged in a matrix in a two-dimensional plane (specifically the XY plane).
Here, the term “face” means being located in front when a direction from unit channel region 90 parallel to a gate length direction, that is, the X-axis direction is viewed. Specifically, the length and position of unit source region 92 in the Y-axis direction correspond with the length and position of unit channel region 90 in the Y-axis direction. Respective portions of the outline of unit source region 92 on a positive side and a negative side of the X-axis direction are defined by a portion of the outline of source electrode 60 on the positive side of the X-axis direction and a portion of the outline of one of source via 70 or source connector 62 located on the most negative side of the X-axis direction. For example, unit source region 92 is defined as a rectangular region as indicated by the thick dash-double-dot line in
Source electrode 60 is formed using a conductive material. For example, source electrode 60 is a single layer or a stack that comprises a metal or an alloy. Examples of the metal include Ti, Al, and Au. Source electrode 60 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc. It is possible to form source electrode 60 using the same material as the material of drain electrode 50 in the same process as a process for drain electrode 50.
It should be noted source electrode 60 may be provided across isolation region 30 from semiconductor layer 20. In other words, a portion of source electrode 60 may be provided above isolation region 30.
Source connector 62 is provided to connect the plurality of source electrodes 60. Source connector 62 is a line for supplying a source electric potential to source electrode 60. Source connector 62 can be referred to as a source drive line for driving source electrode 60.
In the present embodiment, as shown in
In the plan view, source connector 62 includes a portion that overlaps source via 70, and a portion that does not overlap source via 70. In this case, the portion overlapping source via 70 in the plan view is regarded as an upper portion higher than the top face of metal coating 74 of source via 70. It should be noted that when source via 70 does not include metal coating 74, a portion overlapping source via 70 in the plan view is regarded as an upper portion higher than the top face of isolation region 30.
It should be noted that source connector 62 may be provided to enable electrical conduction between (i) the plurality of source vias 70 and (ii) the plurality of source electrodes 60 and the plurality of plate drive lines 82. For example, in the plan view, source connector 62 may be provided in contact with a portion of a lateral face of source via 70, a portion of a lateral face of source electrode 60, and a portion of a lateral face of plate drive line 82, without overlapping any of source via 70, source electrode 60, and plate drive line 82. It should be noted that when source electrode 60 and plate drive line 82 are electrically conducted by being in contact with each other, source connector 62 may be in contact with one of source electrode 60 or plate drive line 82, and need not be in contact with the other of source electrode 60 or plate drive line 82.
Source connector 62 is formed using a conductive material. For example, source connector 62 is a single layer or a stack that comprises a metal or an alloy. Examples of the metal include Ti, Al, and Au. It is possible to form source connector 62 by, for example, plating, using the same material as the material of metal filler 72 of source via 70 in the same process as the process for metal filler 72 of source via 70. Alternatively, source connector 62 may be formed using the same material as the material of source electrode 60 or metal coating 74 of source via 70 in the same process as a process for source electrode 60 or metal coating 74. For example, source connector 62 may be formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc.
Lower electrode 64 is provided below substrate 10. Lower electrode 64 may be also referred to as a back source electrode. Specifically, lower electrode 64 is provided on the entire bottom face of substrate 10. Lower electrode 64 is supplied with the same electric potential as an electric potential supplied to source electrode 60. Specifically, lower electrode 64 is connected to source via 70 and supplies a source electric potential to each of the plurality of source electrodes 60 via source via 70 and source connector 62.
Lower electrode 64 is formed using a conductive material. For example, lower electrode 64 is a single layer or a stack that comprises a metal or an alloy. Examples of the metal include Au, Sn (tin), and Ag (silver). It should be noted that semiconductor device for power amplification 1 is mounted on, for example, a submount substrate using silver paste, solder, or a metal bonding material, etc. Lower electrode 64 also serves as a connecting electrode for the submount substrate etc.
Source via 70 includes a conductor that penetrates through substrate 10 and semiconductor layer 20 and is in contact with lower electrode 64. Source via 70 electrically connects lower electrode 64 and source electrode 60. Source via 70 is provided in at least one of the plurality of unit source regions 92. In the present embodiment, source via 70 and unit source region 92 are provided on a one-to-one basis. In other words, one source via 70 is provided in each of the plurality of unit source regions 92. To put it another way, the number of at least one source via 70 included in unit source region 92 is one. Only one source via 70 provided in one unit source region 92 can be referred to as a single source via.
Source via 70 includes a conductor that is filled in via hole 71 that penetrates through semiconductor layer 20 and isolation region 30. As shown in
Metal filler 72 is a conductive component that fills via hole 71. Metal filler 72 is also referred to as a filled via. In the present embodiment, metal filler 72 is provided to completely fill via hole 71.
Metal coating 74 is a conductive thin film that is in contact with and covers a lateral face of via hole 71. As shown in
Source via 70 is formed by, for example, forming metal coating 74 and metal filler 72 in stated order by plating etc. after via hole 71 is formed by etching etc. Via hole 71 may be formed from a top face side or a bottom face side of substrate 10.
Moreover, source via 70 may include only one of metal filler 72 or metal coating 74. In other words, filling with a metal material need not be performed after metal coating 74 is formed in via hole 71. Alternatively, filling with a metal material may be performed to form metal filler 72 without forming metal coating 74 in via hole 71.
Field plate 80 is provided above semiconductor layer 20 and between gate electrode 40 and drain electrode 50 in the plan view. Field plate 80 is supplied with the same electric potential as the electric potential supplied to source electrode 60. Field plate 80 is provided to mitigate an electric field between gate electrode 40 and drain electrode 50 by being fixed to a source electric potential.
In the present embodiment, field plate 80 includes a plurality of unit plates 81 that face the plurality of unit channel regions 90. The plurality of unit plates 81 can be each referred to as a separated field plate electrode into which field plate 80 is separated. In the present embodiment, as shown in
Field plate 80 is formed using a conductive material. For example, field plate 80 is a single layer or a stack that comprises a metal or an alloy. Examples of the metal include Al, Au, or Cu. Field plate 80 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc.
Plate drive line 82 is a line for suppling a source electric potential to field plate 80. At least one plate drive line 82 is provided for each unit plate 81. In the present embodiment, as shown in
Plate drive line 82 extends from a corresponding source electrode 60 side in the X-axis direction, and is connected to corresponding unit plate 81. Plate drive line 82 electrically connects corresponding unit plate 81 and source connector 62. Plate drive line 82 supplies a source electric potential to each of the plurality of unit plates 81. As shown in
Plate drive line 82 is provided within isolation region 30 in the plan view. Specifically, plate drive line 82 is provided above isolation region 30. In the present embodiment, as shown in
Plate drive line 82 extends in the X-axis direction. As shown in
Field drive line 82 is formed using a conductive material. For example, plate drive line 82 is a single layer or a stack that comprises a metal or an alloy. Plate drive line 82 may be formed using the same material as the material of field plate 80. Plate drive line 82 is formed in a prescribed shape by, for example, film formation by vapor deposition, sputtering, etc. and patterning by etching etc. [2. Characteristic Configuration, Advantageous Effects, etc.]
Subsequently, a characteristic configuration, advantageous effects, etc. of semiconductor device for power amplification 1 according to the present embodiment are described by comparing with a comparative example.
First, a configuration of and problems with a semiconductor device for power amplification according to the comparative example are described with reference to
As shown in
In semiconductor device for power amplification 1x according to the comparative example, as shown in
Moreover, isolation region 30 is not provided in semiconductor device for power amplification 1x according to the comparative example. To put it another way, a channel region of semiconductor layer 20x is not separated into a plurality of unit channel regions 90.
Furthermore, source electrode 60x also extends in the Y-axis direction and is not separated. One source via 70x is provided in an end portion of each source electrode 60x on the negative side of the Y-axis direction.
In semiconductor device for power amplification 1x, the channel region and an area in the vicinity of the channel region are a heat source. Specifically, the heat source can be regarded as a region from immediately below each gate electrode 40x toward drain electrode 50x. In
In
When heat generated in the vicinity of gate electrode 40x diffuses in semiconductor layer 20x in the thickness direction (the Z-axis direction), the heat also spreads in the lateral direction (the X-axis direction and the Y-axis direction). The spread angle of the heat can be schematically regarded as 45 degrees. Since gate electrodes 40x are arranged in the X-axis direction, when heat generated in the vicinity of one of two adjacent gate electrodes 40x overlaps heat generated in the vicinity of an other of two adjacent gate electrodes 40x before reaching substrate 10x, a region that has a high temperature locally is created. For this reason, it is necessary to leave a large space (referred to as a gate pitch) between gate electrodes 40x in the X-axis direction. It should be noted that, in
From the above, in semiconductor device for power amplification 1x according to the comparative example, a plurality of gate electrodes 40x are arranged with a large gate pitch left therebetween, and the length of gate bus 44x in the X-axis direction is increased. Since increasing gate bus 44x in length results in an increase in gate resistance Rg and parasitic inductance components, the high-frequency property of semiconductor device for power amplification 1x is degraded. For example, the gain, efficiency, and saturation power of semiconductor device for power amplification 1x are each decreased.
Moreover, source via 70x is provided in the end portion on the negative side of the Y-axis direction, and a source electric potential is supplied to source electrode 60x from an off-center position. For this reason, since a variation in source electric potential is more likely to occur in a plane, and there is a possibility that the transistor operation of semiconductor device for power amplification 1x becomes unstable.
Furthermore, when a field plate is disposed between gate electrode 40x and drain electrode 50x, a source electric potential supplied to the field plate also becomes unstable. Since an impedance of a portion of the field plate away from a power feeder becomes higher, electric potential fixing by the field plate is weakened. For this reason, it may not be possible to sufficiently mitigate an electric field between gate electrode 40x and drain electrode 50x, and the properties and reliability of semiconductor device for power amplification 1x are degraded.
In order to reduce a variation in source electric potential, it is necessary to control the length of source electrode 60x in the Y-axis direction. In this case, since a gate width (a channel width) is decreased, in order to ensure a necessary amount of drain current, it is necessary to increase the number of sets of gate electrode 40x, drain electrode 50x, and source 60x. As a result, the length of gate bus 44x in the X-axis direction is increased, and, as stated above, the high-frequency property of semiconductor device for power amplification 1x is degraded.
Although the details are described later in the description of advantageous effects etc. of source via 70, it is possible to cause source via 70x to contribute to heat dissipation. In semiconductor device for power amplification 1x, however, since source via 70x is provided in an off-center position, it is hardly possible to cause source via 70x to contribute to the improvement of heat dissipation performance.
With regard to the above problems, it is intended to improve the high frequency property of semiconductor device for power amplification 1 according to the present embodiment by disposing the plurality of unit channel regions 90, the plurality of source vias 70 each of which is elongated in the X-axis direction, and the plurality of plate drive lines 82 that extend in the X-axis direction in semiconductor device for power amplification 1. It should be noted that at least one of source via 70 or plate drive line 82 is not an essential element in the present embodiment. Hereinafter, advantageous effects achieved by each of unit channel region 90, source via 70, and plate drive line 82 are described in detail.
First, the advantageous effects etc. achieved by unit channel region 90 are described with reference to
In semiconductor device for power amplification 1 according to the present embodiment, unit channel region 90 and an area in the vicinity of unit channel region 90 are a heat source. Specifically, the heat source can be regarded as a region from immediately below gate electrode 40 toward drain electrode 50. For the sake of easy-to-understand explanation, unit channel region 90 may be regarded as the heat source in what follows.
In the present embodiment, the plurality of unit channel regions 90 correspond to the plurality of gate electrodes 40 on a one-to-one basis, and are arranged in the Y-axis direction. In the Y-axis direction, isolation region 30 that does not serve as a channel, that is, does not become a current pathway is provided between two adjacent unit channel regions 90. For this reason, as indicated by the thick dashed lines in
Subsequently, the advantageous effects etc. achieved by source via 70 are described with reference to
Source via 70 is provided in unit source region 92 (see
As a result, since it is possible to narrow a gate pitch, it is possible to decrease the length of gate bus 44 in the X-axis direction. It should be noted that the “gate pitch” is a distance (a distance in the X-axis direction) between two gate electrodes 40 that are adjacent to sandwich source electrode 60 without sandwiching drain electrode 50.
Accordingly, it is possible to reduce gate resistance Rg and parasitic inductance components, and reduce the degradation of the high-frequency property of semiconductor device for power amplification 1. For example, it is possible to reduce a decrease in gain, efficiency, and saturation power of semiconductor device for power amplification 1.
Moreover, as shown in
Furthermore, as shown in
Specifically, Lvy>Lcy is satisfied, where the length of unit channel region 90 in the Y-axis direction is denoted by Lcy. In other words, source via 70 that is greater in width than the heat source is disposed close to the heat source. For this reason, source via 70 makes it possible to efficiently dissipate heat that spreads in the Y-axis direction included in heat generated in unit channel region 90.
In the present embodiment, source via 70 is provided to correspond to unit channel region 90 on a one-to-one basis. In other words, one source via 70 is provided for each of a plurality of heat sources. For this reason, since source vias 70 are provided evenly in a plane, it is possible to reduce the aggravation of local heat dissipation performance. Accordingly, it is possible to improve the heat dissipation performance of semiconductor device for power amplification 1.
Moreover, it is possible to supply a source electric potential to each of the plurality of source electrodes 60 in substantially the shortest distance from lower electrode 64. Accordingly, it is possible to stabilize the source electric potential of each of the plurality of source electrodes 60. In addition, since it is possible to reduce parasitic inductance components, it is possible to reduce high-frequency loss.
As stated above, semiconductor device for power amplification 1 according to the present embodiment includes: substrate 10; lower electrode 64 provided below substrate 10; semiconductor layer 20 that is provided above substrate 10 and includes a plurality of active layers comprising group-III nitride, and in which two-dimensional electron gas 22 is produced in a hetero interface of the plurality of active layers; source electrode 60 and drain electrode 50 that are provided above semiconductor layer 20, spaced apart from each other, and electrically connected to two-dimensional electron gas 22; gate electrode 40 that is spaced apart from source electrode 60 and drain electrode 50 and is in contact with semiconductor layer 20; gate finger 42 that is in contact with and covers all of a plurality of gate electrodes 40 arranged linearly in a Y-axis direction, the plurality of gate electrodes 40 each being gate electrode 40; and drain finger 52 that is in contact with and covers all of a plurality of drain electrodes 50 arranged linearly in the Y-axis direction, the plurality of drain electrodes 50 each being drain electrode 50. A plurality of gate fingers 42 are arranged in an X-axis direction orthogonal to the Y-axis direction and supplied with a same electric potential, the plurality of gate fingers 42 each being gate finger 42. In a plan view of substrate 10, semiconductor layer 20 is divided into active region 31 containing two-dimensional electron gas 22 and isolation region 30 not containing two-dimensional electron gas 22. In the plan view, a channel region includes a plurality of unit channel regions 90 that are separated by isolation region 30 and arranged in the Y-axis direction, the channel region being an overlapping portion of active region 31 and the plurality of gate electrodes 40. Source electrode 60 includes a plurality of unit source electrodes each of which faces a corresponding one of the plurality of unit channel regions 90. A plurality of unit source regions 92 each include at least one source via 70 that contains a conductor that penetrates through substrate 10 and semiconductor layer 20 and is in contact with lower electrode 64 that is supplied with a same electric potential as an electric potential supplied to source electrode 60, the plurality of unit source regions 92 each including a corresponding one of the plurality of unit source electrodes. In the plan view, a length of a side of a minimum rectangular region in the X-axis direction is greater than a length of a side of the minimum rectangular region in the Y-axis direction, the minimum rectangular region surrounding the at least one source via 70.
Accordingly, since the plurality of unit channel regions 90 are arranged in the Y-axis direction, heat sources are dispersedly disposed in the Y-axis direction, and it is possible to improve heat dissipation performance in the Y-axis direction. Additionally, since source via 70 is disposed in unit source region 92 that faces unit channel region 90, it is also possible to improve heat dissipation performance in the X-axis direction. Consequently, it is possible to improve the heat dissipation performance of semiconductor device for power amplification 1, and reduce property degradation due to heat.
Moreover, it is possible to stabilize a source electric potential of source electrode 60 by disposing source electrode 60 and source via 70 close to each other. In addition, it is possible to reduce parasitic inductance components of a source line. Accordingly, it is possible to reduce high-frequency loss of semiconductor device for power amplification 1.
It should be noted that the number of at least one source via 70 is one in the present embodiment. In the plan view, the length of the opening outline of source via 70 in the X-axis direction is greater than the length of the opening outline of source via 70 in the Y-axis direction. For this reason, the lengths of a minimum rectangular region in the X-axis direction and the Y-axis direction are equal to length Lvx and length Lvy of the opening outline of source via 70 in the X-axis direction and the Y-axis direction shown in
Accordingly, it is possible to further improve the heat dissipation performance in the X-axis direction.
Furthermore, for example, in the Y-axis direction, the length of the opening outline of source via 70 is greater than the length of unit channel region 90.
Accordingly, it is possible to further improve the heat dissipation performance in the Y-axis direction. In addition, since the area of source via 70 is increased, it is possible to contribute to an increase in stability of the source electric potential and the reduction of the parasitic inductance components.
Moreover, for example, at least one source via 70 is provided in each of the plurality of unit source regions 92.
Accordingly, since source vias 70 are disposed in a plane in a balanced manner, it is possible to reduce local heat concentration. Additionally, it is possible to reduce an in-plane variation in source electric potential.
Subsequently, the advantageous effects etc. achieved by plate drive line 82 are described.
As shown in
As stated above, source electrode 60 is stably supplied with the source electric potential from lower electrode 64 through source via 70 and source connector 62 provided in corresponding unit source region 92. For this reason, plate drive line 82 provided for each unit plate 81 makes it possible to supply a stable source electric potential to unit plate 81. In other words, since a variation in electric potential of unit plate 81 is reduced in the XY plane, it becomes easier to evenly mitigate an electric field between gate electrode 40 and drain electrode 50 in a plane. Accordingly, it is possible to increase the saturation power of semiconductor device for power amplification 1.
Moreover, since the source electric potential is supplied to unit plate 81 from the X-axis direction, it is possible to arrange many unit plates 81 in the Y-axis direction in a state in which the stability of the source electric potential is increased. In other words, it is possible to increase the length of gate finger 42 in the Y-axis direction. As a result, it is possible to decrease the length of gate bus 44 in the X-axis direction, and reduce the number of drain fingers 52. For this reason, since it is possible to reduce capacitance Cds between drain electrode 50 and source electrode 60, it is possible to improve efficiency performance of semiconductor device for power amplification 1.
As stated above, semiconductor device for power amplification 1 according to the present embodiment includes: substrate 10; lower electrode 64 provided below substrate 10; semiconductor layer 20 that is provided above substrate 10 and includes a plurality of active layers comprising group-III nitride, and in which two-dimensional electron gas 22 is produced in a hetero interface of the plurality of active layers; source electrode 60 and drain electrode 50 that are provided above semiconductor layer 20, spaced apart from each other, and electrically connected to two-dimensional electron gas 22; gate electrode 40 that is spaced apart from source electrode 60 and drain electrode 50 and is in contact with semiconductor layer 20; field plate 80 that is provided between gate electrode 40 and drain electrode 50 above semiconductor layer 20 and supplied with a same electric potential as an electric potential supplied to source electrode 60; gate finger 42 that is in contact with and covers all of a plurality of gate electrodes 40 arranged linearly in a Y-axis direction, the plurality of gate electrodes 40 each being gate electrode 40; and drain finger 52 that is in contact with and covers all of a plurality of drain electrodes 50 arranged linearly in the Y-axis direction, the plurality of drain electrodes 50 each being drain electrode 50. In a plan view of substrate 10, semiconductor layer 20 is divided into active region 31 containing two-dimensional electron gas 22 and isolation region 30 not containing two-dimensional electron gas 22. In the plan view, a channel region includes a plurality of unit channel regions 90 that are separated by isolation region 30 and arranged in the Y-axis direction, the channel region being an overlapping portion of active region 31 and the plurality of gate electrodes 40. Source electrode 60 includes a plurality of unit source electrodes each of which faces a corresponding one of the plurality of unit channel regions 90. Field plate 80 includes a plurality of unit plates 81 each of which faces a corresponding one of the plurality of unit channel regions 90. At least one of a plurality of plate drive lines 82 is provided, for each of the plurality of unit plates 81, within isolation region 30, the plurality of plate drive lines 82 extending in an X-axis direction orthogonal to the Y-axis direction and electrically connecting the plurality of unit source electrodes and the plurality of unit plates 81.
Accordingly, since the plurality of unit channel regions 90 are arranged in the Y-axis direction, heat sources are dispersedly disposed in the Y-axis direction, and it is possible to improve heat dissipation performance in the Y-axis direction. Consequently, it is possible to improve the heat dissipation performance of semiconductor device for power amplification 1, and reduce property degradation due to heat.
Furthermore, it is possible to supply a stable source electric potential to each of the plurality of unit plates 81 from the X-axis direction via plate drive line 82. Since it is possible to decrease an impedance of field plate 80 (unit plate 81), and a variation in electric potential of unit plate 81 is reduced in the XY plane, it becomes easier to evenly mitigate an electric field between gate electrode 40 and drain electrode 50 in a plane. Accordingly, it is possible to increase the saturation power of semiconductor device for power amplification 1.
Moreover, since it is possible to arrange many unit plates 81 in the Y-axis direction in a state in which the stability of the source electric potential is increased, it is possible to increase the length of gate finger 42 in the Y-axis direction. For this reason, it is possible to decrease the length of gate bus 44 in the X-axis direction, and reduce the number of drain fingers 52. Since it is possible to reduce capacitance Cds between drain electrode 50 and source electrode 60, it is possible to improve efficiency performance of semiconductor device for power amplification 1.
Furthermore, for example, the plurality of plate drive lines 82 are in contact with isolation region 30.
Accordingly, plate driver line 82 is located close to unit channel region 90, and it is possible to use plate driver line 82 as a path for releasing heat. For this reason, it is possible to improve the heat dissipation performance of semiconductor device for power amplification 1.
Moreover, for example, gate finger 42 is provided above and apart from the plurality of plate drive lines 82.
Accordingly, since it becomes easier to increase a distance between gate finger 42 and plate drive line 82 supplied with the source electric potential, it is possible to reduce gate-source capacitance Cgs. As an example, when plate drive line 82 has a thickness of 0.2 μm, a distance between the bottom face of gate finger 42 and the top face of plate drive line 82 is 0.8 μm. By reducing gate-source capacitance Cgs, it is possible to improve gain performance of semiconductor device for power amplification 1.
Furthermore, by keeping the distance long, for example, it becomes easier to increase the cross-sectional area of gate finger 42. As a result, since it is also possible to reduce gate resistance Rg, for example, it is possible to reduce a variation in gate electric potential in a plane, and stabilize transistor operation.
Moreover, for example, the plurality of unit source regions 92 each include at least one source via 70 that contains a conductor that penetrates through substrate 10 and semiconductor layer 20 and is in contact with lower electrode 64 that is supplied with the same electric potential as an electric potential supplied to source electrode 60, the plurality of unit source regions 92 each including a corresponding one of the plurality of unit source electrodes.
Accordingly, since source via 70 is disposed in unit source region 92 that faces unit channel region 90, it is possible to improve heat dissipation performance in the X-axis direction. Consequently, it is possible to improve the heat dissipation performance of semiconductor device for power amplification 1, and reduce property degradation due to heat.
Furthermore, by disposing source electrode 60, plate drive line 82, and source via 70 close to each other, it is possible to stabilize the source electric potential of source electrode 60 and the source electric potential of each unit plate 81 supplied via plate drive line 82. In addition, it is possible to reduce parasitic inductance components of a source line. Accordingly, it is possible to reduce high-frequency loss of semiconductor device for power amplification 1.
Moreover, for example, unit plate 81 and unit channel region 90 correspond to each other on a one-to-one basis.
Accordingly, since it is possible to reduce a variation in electric field mitigation performance in a plane, it is possible to improve the uniformity of the transistor operation of semiconductor device for power amplification 1.
Subsequently, a plurality of variations of semiconductor device for power amplification 1 according to the embodiment are described. The following description focuses mainly on differences from the embodiment, and omits or simplifies points in common with the embodiment.
As shown in
Drain electrode 50 is provided in contact with the lateral face of recessed portion 50r. Source electrode 60 is provided in contact with the lateral face of recessed portion 60r. In the example shown in
It should be noted that only one of recessed portions 50r and 60r may be provided. For example, recessed portion 50r is not provided, and, as with the embodiment, drain electrode 50 may be disposed on the surface of semiconductor layer 20. Alternatively, recessed portion 60r is not provided, and source electrode 60 may be disposed on the surface of semiconductor layer 20.
As shown in
Accordingly, it becomes easier to keep a long distance between plate drive line 82 and gate finger 42. For this reason, since it is possible to reduce gate-source capacitance Cgs, it is possible to improve gain performance of semiconductor device for power amplification 3.
As shown in
Contact layers 28d and 28s are formed by reducing the resistance of a portion of semiconductor layer 20 by ion implantation. Specifically, contact layers 28d and 28s are formed by implanting ions of Si etc. into a region that includes at least the hetero interface between GaN layer 24 and AlGaN layer 26 that have been epitaxially grown, that is, a region in which two-dimensional electron gas 22 is produced. Contact layers 28d and 28s are formed by annealing after the ion implantation.
Alternatively, contact layers 28d and 28s may be formed by crystal regrowth after GaN layer 24 and AlGaN layer 26 that have been epitaxially grown are removed by being etched at least to a depth at which two-dimensional electron gas 22 is produced. For example, contact layers 28d and 28s may be epitaxially grown low-resistance semiconductor layers in portions removed from GaN layer 24 and AlGaN layer 26.
After contact layers 28d and 28s are formed, drain electrode 50 and source electrode 60 are formed. Specifically, drain electrode 50 is provided in contact with the top face of contact layer 28d. Source electrode 60 is provided in contact with the top face of contact layer 28s.
As stated above, in semiconductor device for power amplification 4 according to the present variation, semiconductor layer 20 includes contact layer 28s that electrically connects two-dimensional electron gas 22 and source electrode 60 in the surface of semiconductor layer 20.
Accordingly, since the presence of contact layer 28s leads to a decrease in substantial gate-source distance Lgs, it is possible to reduce source resistance. It should be noted that only for the purpose of decreasing gate-source distance Lgs, it is conceivable to dispose source electrode 60 itself close to gate electrode 40. In this case, however, since gate-source capacitance Cgs is increased, a high-frequency property is degraded. The present variation makes it possible to reduce the source resistance while reducing an increase in gate-source capacitance Cgs due to the presence of contact layer 28s.
Moreover, in the present variation, since contact layer 28d is provided, the same applies to drain electrode 50. With regard to drain electrode 50, since field plate 80 supplied with a source electric potential is provided, it is possible to reduce drain resistance while reducing an increase in source-drain capacitance Cds.
It should be noted that only one of contact layers 28s and 28d may be provided. For example, contact layer 28s is provided, and contact layer 28d need not be provided.
As shown in
As with Variation 3, the present variation makes it possible to reduce source resistance while reducing an increase in gate-source capacitance Cgs. Additionally, it is possible to reduce drain resistance while reducing an increase in source-drain capacitance Cds.
As shown in
In the plan view, for example, isolation region 32 is located at the center of semiconductor device for power amplification 6 in the Y-axis direction. In semiconductor device for power amplification 6, heat concentrates more easily at the center than in the outer periphery. By increasing isolation region 32 in a portion at which heat concentrates easily, it is possible to mitigate heat concentration and improve heat dissipation performance.
Subsequently, a plurality of variations of source via 70 are described with reference to
First, a low-filled source via is described with reference to
A low-filled source via is a source via that does not completely fill via hole 71 that penetrates through substrate 10 and semiconductor layer 20, that is, has a filling rate of less than 100%. The filling rate is a ratio of the volume of a metal material disposed in via hole 71 to the capacity of via hole 71.
As shown in
Space 75 penetrates, for example, from the top face of semiconductor layer 20 into the bottom face of substrate 10. An opening of space 75 in the bottom face of substrate 10 is covered with lower electrode 64. It should be noted that portions of the metal material included in metal filter 72 or metal coating 74 may be discretely located in space 75. Although the details are described later, a method for manufacturing a semiconductor device for power amplification includes polishing the bottom face of substrate 10. A portion of metal filler 72 or metal coating 74 that is scraped at the time of polishing may remain in space 75. Metal filler 72 may include a porous structure.
Moreover, although
In the present variation, source via 70 has a filling rate of at least 50%. To put it another way, a conductor inside source via 70 accounts for at least a half of the opening volume of source via 70.
Accordingly, it is possible to improve heat dissipation performance using a metal component having a high heat conductivity. For example, an Si substrate has a thermal resistance higher than that of an SiC substrate. However, since it is possible to improve the heat dissipation performance using source via 70 including a filled metal component, even when the Si substrate is used as substrate 10, it is possible to sufficiently exhibit the properties of semiconductor device for power amplification 1.
Next, a connected source via is described with reference to
The connected source via has a configuration in which at least two adjacent source vias are connected. Specifically, as shown in
A method for forming source vias 70 connected and via connector 76 is similar to a method for forming a plurality of source vias spaced apart from each other, except for a different shape of via hole 71 that penetrates through semiconductor layer 20 and substrate 10. For example, after via hole 71 that extends over a plurality of unit source regions 92 and is in an elongated shape in the Y-axis direction is formed, the lateral faces of via hole 71 are covered with metal coating 74. Subsequently, by filling an area surrounded by metal coating 74 with a metal material, it is possible to form source vias 70 connected and via connector 76.
As stated above, source vias 70 included in adjacent respective unit source regions 92 (not shown in
Accordingly, since it is possible to increase a volume occupied by a metal having a high heat conductivity by source vias 70 being connected, it is possible to further improve the heat dissipation performance.
Next, a group source via is described with reference to
The group source via has a configuration in which a plurality of source vias are provided in one unit source region 92. The plurality of source vias are arranged in a two-dimensional array.
In the examples shown in
In the example shown in
In the example shown in
The planar shape of a source via provided in one unit source region 92 need not be the rectangular shape elongated in the X-axis direction. In the examples shown in
In the example shown in
It should be noted that the arrangements shown in
Although the shape and size of the plurality of source vias included in one unit source region 92 are identical in the examples shown in
In the example shown in
In the example shown in
As stated above, for example, the number of at least one source via 70A, 70B, or 70C included in unit source region 92 may be at least two. In this case, minimum rectangular region 94 is a region that surrounds all source vias 70A, 70B, or 70C provided in unit source region 92 in the plan view.
Accordingly, since the shape of each of source vias 70A, 70B, and 70C is reduced, it is easy to perform metal filling. Since the metal filling rate of each of source vias 70A, 70B, and 70C is increased, it is possible to further improve the heat dissipation performance.
In each of the examples shown in
The length of minimum rectangular region 94 in the X-axis direction is denoted by Lmx, and the length of minimum rectangular region 94 in the Y-axis direction is denoted by Lmy. Here, Lmx>Lmy is satisfied. Accordingly, as with the single source via (specifically source via 70), it is possible to improve the heat dissipation performance in the X-axis direction.
Moreover, for example, at least one source via 70A, 70B, or 70C is arranged in a two-dimensional matrix in the plan view.
For this reason, it is possible to prevent heat from concentrating locally, and improve the heat dissipation performance.
It should be noted that
Subsequently, a plurality of variations of plate drive line 82 are described with reference to
In the example shown in
Connecting line 84 is formed using a conductive material. For example, it is possible to form connecting line 84 integrally using the same material as the material of plate drive line 82. Alternatively, connecting line 84 may be integrally formed using the same material as the material of field plate 80. In other words, it is possible to regard connecting line 84 as a portion of plate drive line 82 or a portion of field plate 80.
The example shown in
As stated above, the semiconductor device for power amplification according to the embodiment or each of the variations may include connecting line 84 that connects two adjacent unit plates 81. Connecting line 84 may be located between gate finger 42 and drain finger 52 in the plan view.
By connecting the plurality of unit plates 81 in the Y-axis direction, it is possible to reduce wiring resistance of field plate 80. Accordingly, it becomes easier to ensure in-plane uniformity of a source electric potential of field plate 80.
The example shown in
Accordingly, since this further increases an area that contributes to heat dissipation, it is possible to further enhance a heat dissipation effect.
It should be noted that the location of source via 70 may be changed in the example shown in
Accordingly, since this makes it easier for heat diffused via connecting line 84 to be conducted to source via 70, it is possible to further enhance the heat dissipation effect.
It should be noted that, in the examples shown in
Subsequently, a method for manufacturing each of the semiconductor devices for power amplification according to the embodiment and the variations described above is described with reference to
First, as shown in
Moreover, although not shown in the figure, isolation region 30 is formed by performing ion implantation on a prescribed region of semiconductor layer 20 after growth. Furthermore, contact layers 28d and 28s shown in
Next, as shown in
Then, as shown in
After that, as shown in
Next, as shown in
Moreover, in the example shown in
Then, as shown in
After that, as shown in
Each of the semiconductor devices for power amplification according to the embodiment and the variations described above is manufactured through the above processes.
It should be noted that, as shown in
Although one or more semiconductor devices for power amplification according to one or more aspects have been described based on the embodiment, the variations, etc. above, the present disclosure is not limited to the embodiment etc. Forms obtained by various modifications to the present embodiment that can be conceived by a person skilled in the art as well as forms created by combining constituent elements in different embodiments are included in the scope of the present disclosure, as long as they do not depart from the essence of the present disclosure.
For instance, although the example in which the plurality of gate electrodes 40, the plurality of drain electrodes 50, and the plurality of source electrodes 60 are arranged in the Y-axis direction is shown, the present disclosure is not limited to this example. In other words, the plurality of gate electrodes 40, the plurality of drain electrodes 50, and the plurality of source electrodes 60 need not be separated in the Y-axis direction. For example, the plurality of gate electrodes 40 arranged in the Y-axis direction may be one gate electrode obtained by connecting the plurality of gate electrodes 40. To put it another way, the one gate electrode may be provided not only on semiconductor layer 20 but also on isolation region 30. The same applies to the plurality of drain electrodes 50 and the plurality of source electrodes 60.
Moreover, although the example in which one source via 70 or the plurality of source vias 70A, 70B, or 70C are provided in each of the plurality of unit source regions 92 is shown, the present disclosure is not limited to this example. Unit source region 92 in which no source via 70, 70A, 70B, or 70C is provided may be present.
Alternatively, a source via need not be provided in any of the plurality of unit source regions 92. For example, as with semiconductor device for power amplification 1x according to the comparative example, source via 70x may be provided outside a source region.
Furthermore, although the example in which all of source vias 70, 70A, 70B, and 70C each include metal filler 72 and metal coating 74 is shown, the present disclosure is not limited to this example. Each of source vias 70, 70A, 70B, and 70C may include only metal filler 72 or may include only metal coating 72.
Moreover, when the plurality of unit plates 81 are connected to each other, the plurality of plate drive lines 82 need not be provided. In other words, a source electric potential may be supplied to each of the plurality of unit plates 81 in the Y-axis direction.
Furthermore, various changes, substitutions, additions, omissions, etc. can be carried out in each of the above embodiments within the scope of the claims or its equivalents.
Although only some exemplary embodiments of the present disclosure have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure.
The present disclosure can be used as a semiconductor device for power amplification that is capable of reducing property degradation due to heat, and can be used as a high-frequency transistor or can be used for various electronic devices such as a communication device.
This is a continuation application of PCT International Application No. PCT/JP2023/005730 filed on Feb. 17, 2023, designating the United States of America, which is based on and claims priority of U.S. Patent Application No. 63/324,387 filed on Mar. 28, 2022 and U.S. Patent Application No. 63/324,402 filed on Mar. 28, 2022. The entire disclosures of the above-identified applications, including the specifications, drawings and claims are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63324387 | Mar 2022 | US | |
| 63324402 | Mar 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/005730 | Feb 2023 | WO |
| Child | 18894473 | US |
