Claims
- 1. A semiconductor device comprising:
- a stepped portion formed on a semiconductor substrate;
- a first polycrystalline silicon layer having a first portion and a second portion located on and elevated by said stepped portion with respect to the first portion;
- a high-melting-point metal silicide layer formed on said first polycrystalline silicon layer; and
- an upper layer formed on said high-melting-point metal silicide layer and formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer, wherein
- said first polycrystalline silicon layer, said high-melting-point metal silicide layer and said upper layer form a gate electrode layer of a three-layer structure,
- said stepped portion is located at a side end of an element isolating and insulating film formed on a main surface of said semiconductor substrate,
- a side wall insulating film is formed in contact with at least side surfaces of said polycrystalline silicon layer and said high-melting-point metal silicide layer in a section along a channel length direction of said gate electrode layer, and
- a concavity is formed in the main surface of said semiconductor substrate located outside said side wall insulating film.
- 2. The semiconductor device according to claim 1, wherein
- said first polycrystalline silicon layer, said high-melting-point metal silicide layer and said upper layer form an interconnection layer of a three-layer structure, and
- said stepped portion is located at a surface of insulating film covering a conductive layer formed on said semiconductor substrate.
- 3. The semiconductor device according to claim 1, wherein
- said first polycrystalline silicon layer contains impurity of a first conductivity type,
- said upper layer is an amorphous silicon layer or a polycrystalline silicon layer, and
- said upper layer contains impurity of the same first conductivity type as said first polycrystalline silicon layer.
- 4. The semiconductor device according to claim 1, wherein
- said first polycrystalline silicon layer has a thickness not smaller than that of said high-melting-point metal silicide layer.
- 5. A semiconductor device comprising:
- a semiconductor substrate having a main surface;
- a pair of source/drain regions formed on the main surface of said semiconductor substrate and spaced by a predetermined distance from each other to define a channel region therebetween;
- a first polycrystalline silicon layer formed on said channel region with a gate insulating film therebetween;
- a high-melting-point metal silicide layer formed on said first polycrystalline silicon layer;
- an upper layer formed on said high-melting-point metal silicide layer and formed of one layer selected from the group consisting of an amorphous silicon layer, a TiN layer and a TiW layer;
- a side wall insulating film formed in contact with at least side surfaces of said first polycrystalline silicon layer and said high-melting-point metal silicide layer; and
- a concavity formed in the main surface of said semiconductor substrate located outside an end of a lower surface of said side wall insulating film.
- 6. The semiconductor device according to claim 5, wherein
- said first polycrystalline silicon layer contains impurity of a first conductivity type,
- said upper layer is an amorphous silicon layer, and
- said upper layer contains impurity of the same first conductivity type as said polycrystalline silicon layer.
- 7. The semiconductor device according to claim 5, wherein
- said first polycrystalline silicon layer has a thickness not smaller than that of said high-melting-point metal silicide layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-128066 |
May 1995 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 08/563,421 filed Nov. 28, 1995, now abandoned.
US Referenced Citations (7)
Foreign Referenced Citations (3)
Number |
Date |
Country |
63-76479 |
Apr 1988 |
JPX |
1-205468 |
Aug 1989 |
JPX |
5-21785 |
Jan 1993 |
JPX |
Non-Patent Literature Citations (3)
Entry |
Henry J. Geipel, Jr. et al., "Composite Silicide Gate Electrodes--Interconnections for VLSI Device Technologies," VLSI Metallisation: Phys. a Techn., 1991, pp. 172-179. |
Lee et al., "Antireflective Coating for Submicron Lithography Processes," IEDMS of ROC, 1992, pp. 437-441. |
"Recent Developments in Silicide Tecnique", Solid State Technology/Japanese Version/Nov. 1985. |
Continuations (1)
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Number |
Date |
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Parent |
563421 |
Nov 1995 |
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