SEMICONDUCTOR DEVICE HAVING DOPANT DEACTIVATION UNDERNEATH GATE

Abstract

A transistor includes a substrate. The transistor further includes a channel region comprising dopants of a first type. The transistor further includes a gate structure over the channel region. The transistor further includes a source comprising dopants of a second type. The transistor further includes a lightly doped drain (LDD) comprising dopants of the second type, wherein the LDD is over the source, and the channel region is in direct contact with the LDD. The transistor further includes a deactivated region in the channel region underneath the gate structure, wherein the deactivated region comprises a first region inside an epitaxial layer and a second region outside the epitaxial layer.

Description

TECHNICAL FIELD

The present disclosure relates generally to an integrated circuit and more particularly to a metal-oxide-semiconductor field-effect transistor (MOSFET).

BACKGROUND

Some MOSFET devices suffer from device variability issues, such as random dopant fluctuation (RDF) and threshold voltage variations. RDF depends on the device channel profile and the gate critical dimension variations are proportional to the threshold voltage roll-off slope. Reducing the RDF and threshold voltage roll-off slope will help reduce the total variability of the MOSFET device.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross section diagram of an exemplary MOSFET device with selective dopant deactivation in a region underneath the gate according to some embodiments;

FIG. 2 is a plot showing threshold voltage (Vt) roll-off slope comparison of NMOS devices with and without the selective dopant deactivation according to some embodiments;

FIG. 3 is a cross section diagram of an exemplary MOSFET device with selective dopant deactivation in a region underneath the gate and halo implant;

FIG. 4 is a plot showing Vt roll-off slope comparison of NMOS devices having the selective dopant deactivation with and without the halo implant;

FIGS. 5A-5G are schematic diagrams of intermediate steps of an exemplary fabrication process of a MOSFET device according to some embodiments; and

FIGS. 6A-6G are schematic diagrams of intermediate steps of another exemplary fabrication process of a MOSFET device according to some embodiments.

DETAILED DESCRIPTION

The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use, and do not limit the scope of the disclosure.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

FIG. 1 is a cross section diagram of an exemplary MOSFET device with selective dopant deactivation in a region underneath the gate according to some embodiments. The MOSFET device 100 includes a substrate 102, an upper substrate layer 103, a channel region 106, a lightly doped drain (LDD) 108, a source 110, a drain 112, a gate dielectric 114, and a gate 116 having a gate length 117. The substrate 102 comprises silicon or any other suitable material. The upper substrate layer 103 can be part of the substrate 102, or comprise a separate epitaxial layer such as silicon epitaxial (Si-Epi) layer in some embodiments. The LDD 108 is optional, and doped with lower dopant dosage to permit a device operation with a higher drain-source voltage.

The gate dielectric 114 that is disposed over a substrate surface 104 comprises silicon dioxide, high-k dielectric, or any other suitable material. The high-k dielectric material such as hafnium oxide, hafnium silicate, zirconium silicate, or zirconium dioxide has a higher dielectric constant compared to silicon dioxide. The gate 116 comprises metal, polysilicon, or any other suitable material. The source 110 and the drain 112 are doped with dopants. Acceptors such as boron or Indium are used as dopants for P-type MOSFET (PMOS), and donors such as phosphorus, arsenic, antimony are used for N-type MOSFET (NMOS). The channel region 106 is doped with dopants different from the source 110 and the drain 112. For example, if the source 110 and the drain 112 are doped with N-type material (donors), the channel region 106 is doped with P-type material (acceptors).

In the MOSFET device 100, dopants in a region 118 underneath the gate 116 are selectively deactivated to reduce the active dopants in and/or around the channel region 106. One way to perform the selective deactivation in NMOS is to use localized carbon implant in the region 118 underneath the gate 116 (in the channel region 106). The region 118 underneath the gate 116 has a depth ranging from 5 nm to 40 nm below the gate dielectric 114 in some embodiments. For example, the selectively deactivated region 118 is located at a depth of about 20 nm beneath the substrate surface 104 in one embodiment. Another way is to create a substrate recess followed by forming an epitaxial layer (e.g., Si-Epi) in the channel region 106 to directly remove the active dopants of the channel region 106 as described in FIGS. 6A-6G.

In some embodiments, an NMOS device having boron doping in the channel region 106, carbon is implanted in the region 118 underneath the gate 116. The carbon implantation is performed with an energy ranging from 2 KeV to 25 KeV and a dose ranging from 5e13 cm⁻² to 1e15 cm⁻² in some examples.

FIG. 2 is a plot showing threshold voltage (Vt) roll-off slope comparison of NMOS devices with and without the selective dopant deactivation according to some embodiments. A curve 202 is for an NMOS device without the selective dopant deactivation in the region 118 underneath the gate 116. A curve 204 is for an NMOS device having the selective dopant deactivation in the region 118 underneath the gate 116 as described above.

As the gate length 117 changes from 20 nm to 50 nm, the Vt changes about 0.3 V for the curve 202, and the Vt changes about 0.16 V for the curve 204. Compared to the Vt roll-off slope of the curve 202, the Vt roll-off slope of the curve 204 is significantly reduced. Since the selective deactivation region 118 is in the channel region 106, the deactivation has more Vt reduction for a long channel device compared to short channel device.

FIG. 3 is a cross section diagram of an exemplary MOSFET device 300 with selective dopant deactivation in a region 118 (underneath the gate 116) and halo implants 302 and 304. In the MOSFET device 300, further Vt roll-off slope improvement is achieved with halo implants 302 and 304 (e.g., using Indium or Boron for NMOS and arsenic or phosphorus for PMOS) in addition to the selective deactivation in the region 118 underneath the gate 116. The halo implant is a low energy/current implantation carried out at large incident angle so that implanted dopants penetrate underneath the edge of the gate 116. In one embodiment, indium halo implants 302 and 304 increases Vt of a short channel NMOS device 300.

FIG. 4 is a plot showing Vt roll-off slope comparison of NMOS devices having the selective dopant deactivation with and without the halo implant. A curve 402 is for an NMOS with carbon implant in the region 118 underneath the gate 116 for selective deactivation but without halo implants 302 and 304. A curve 404 is for an NMOS with carbon implant for selective deactivation and halo implants 302 and 304. As the gate length 117 changes from 20 nm to 50 nm, the Vt changes about 0.2 V for the curve 402, and the Vt changes about 0.13 V for the curve 404. The curve 404 shows reduced Vt roll-off slope compared to the curve 402.

FIGS. 5A-5G are schematic diagrams of intermediate steps of an exemplary fabrication process of a MOSFET device according to some embodiments. FIG. 5A shows a substrate 102 with shallow trench isolation (STI) 502. The substrate 102 comprises silicon or any other suitable material. The STI 502 is formed by etching trenches in the substrate 102, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization (CMP).

Dopants are implanted for a Vt/well implant operation over the substrate 102, particularly in where the channel region (106 in FIG. 1) will be formed. The dopants can be P-type dopants such as boron or other suitable species, or N-type dopants such as phosphorous, antimony, or arsenic, according to various embodiments.

As will be referred to hereinafter, the Vt implant introduces dopants of a first dopant type (either N-type or P-type). The Vt implant may use an implant energy of 5 KeV to 30 KeV for NMOS (P-type Vt implant such as BF₂) and 50 KeV to 130 KeV for PMOS (N-type Vt implant such as Arsenic) in some embodiments. Various suitable implantation powers and energies may be used. The Vt implant introduces impurities into the channel region to adjust the Vt (threshold voltage) applied to the device to open the channel to current flow and may also be referred to as a Vt adjust implant. An annealing operation that may be used to activate the introduced dopants, cure crystalline defects and cause diffusion and redistribution of dopants. Various annealing operations may be used and the annealing operations may drive the implanted dopants deeper into the substrate 102.

In FIG. 5B, an optional silicon epitaxial (Si-Epi) layer 103 is formed over the substrate 102 using epitaxial deposition or other suitable methods. The Si-Epi layer 103 is undoped and has a thickness of about 5 nm-20 nm in various embodiments. In one example, the Si-Epi layer 103 has a thickness of about 8 nm. In some embodiments, an undoped SiC layer (not shown) may be also epitaxially deposited between the substrate 102 and the Si-Epi layer 103 and may have a thickness of about 2 nm-20 nm in various embodiments. The Silicon carbide (SiC) retards dopant diffusion.

In FIG. 5C, a dummy gate 506 is formed, which may use any known methods in the art or later developed methods. A dummy gate dielectric (not shown) may be also formed below the dummy gate 506 in some embodiments. The dummy gate 506 comprises polysilicon or any other suitable material. Various patterning techniques may be used to pattern the dummy gate 506. With the dummy gate 506 in place, optional LDD and/or halo implant operations can be carried out. In some embodiments, LDD 108 is formed in the drain 112 area by lightly doping. Also, halo implants (e.g., 302 and 304 in FIG. 3, not shown in FIG. 5C for simplicity) can be performed in the source 110 area and drain 112 area.

Each of the LDD 108 and halo implant operations introduces dopants through upper surface of the Si-Epi layer 103 and/or the substrate 102. The LDD 108 is formed of a second dopant type, opposite the first dopant type of the Vt implant in FIG. 5A. According to one embodiment, the LDD 108 region may be N-type with the Vt implant operation being P-type. A halo implantation operation is an angled ion implantation process and can use any suitable method known in the art. The halo implantation operation introduces dopants of the same dopant type, as the Vt implantation into the source 110 area and the drain 112 area, but not the channel region (below the dummy gate 506).

According to one embodiment, the halo implantation operation may introduce P-type dopants although N-type dopants may be implanted in other embodiments. In one embodiment, the halo implantation operation may be used to introduce a mixture of indium and carbon, and in another embodiment, the halo implantation operation may be used to introduce indium and boron, such as present in BF₂.

Spacers 504 are formed using various methods known in the art and comprise oxide silicon nitride or any other suitable material. The source 110 and drain 112 are formed by source/drain implantation operation. The source 110 and drain 112 are formed of the same, second dopant type as LDD 108. In one embodiment, LDD 108 and source 110/drain 112 are N-type regions, for example.

In FIG. 5D, inter layer dielectric (ILD) 508 is formed over the Si-Epi 103 layer and/or the substrate 102 by depositing any suitable dielectric material and planarization, for example.

In FIG. 5E, the dummy (polysilicon) gate 506 is removed by etching, for example. Carbon implant operation is performed to selectively deactivate dopants in the region 118 underneath the gate 116 (in the channel region). In some embodiments, an NMOS device having boron doping in the channel region, carbon is implanted in the region 118 underneath the gate 116 with an energy ranging from 2 KeV to 25 KeV and a dose ranging from 5e13 cm⁻² to 1e15 cm⁻². An annealing operation may be performed to cure crystalline defects and cause diffusion and redistribution of carbon implants.

In FIG. 5F, a gate dielectric layer 510, e.g., a high-k dielectric, is formed over the surface of the Si-Epi layer 103 and/or the substrate 102. The gate dielectric layer 510 may be formed using various suitable dielectric deposition processes. According to one embodiment, hafnium oxide (HfO) may be used, but other suitable dielectric materials may be used for the gate dielectric layer 510 in other embodiments. The gate dielectric layer 510 using a high-k dielectric has a thickness of 2 nm in one embodiment, but may have a thickness that ranges from about 1 nm to 20 nm in various embodiments.

A metal gate layer 512 is formed over the gate dielectric layer 510 by depositing any suitable metal using conventional or later developed methods. Various patterning techniques may be used to pattern the metal gate layer 512 and the gate dielectric layer 510.

In FIG. 5G, a gate stack including a gate dielectric 114 and gate 116 is formed over the Si-Epi layer 103 and/or the substrate 102. The gate 116 comprises metal in this example, but may comprise polysilicon or any other suitable materials in other embodiments. By the process in FIGS. 5A-5G, a selective dopant deactivation is performed in the region 118 underneath the gate 116, e.g., by carbon implant on boron doped channel, and the Vt roll-off slope is reduced, which helps to reduce local device variability.

FIGS. 6A-6G are schematic diagrams of intermediate steps of another exemplary fabrication process of a MOSFET device according to some embodiments. FIG. 6A shows a substrate 102 with shallow trench isolation (STI) 502. The step in FIG. 6A is similar to the step in FIG. 5A. The substrate 102 comprises silicon or any other suitable material. The STI 502 is formed by etching trenches in the substrate 102, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization (CMP).

Dopants are implanted for a Vt/well implant operation over the substrate 102, particularly in where the channel region (106 in FIG. 1) will be formed. The Vt implant introduces dopants of a first dopant type (either N-type or P-type) and is a lower power implant. An annealing operation that may be used to activate the introduced dopants, cure crystalline defects and cause diffusion and redistribution of dopants. Various annealing operations may be used and the annealing operations may drive the implanted dopants deeper into the substrate 102.

In FIG. 6B, a dummy gate 506 and a dummy gate dielectric 601 are formed over the substrate 102, which may use any known methods in the art or later developed methods. The dummy gate 506 comprises polysilicon or any other suitable material. Various patterning techniques may be used to pattern the dummy gate 506. With the dummy gate 506 in place, optional LDD and/or halo implant operations can be carried out. In some embodiments, LDD 108 is formed in the drain 112 area by lightly doping. Also, halo implants (e.g., 302 and 304 in FIG. 3, not shown in FIG. 6B for simplicity) can be performed in the source 110 area and drain 112 area.

Each of the LDD 108 and halo implant operations introduces dopants through upper surface of the substrate 102. The LDD 108 is formed of a second dopant type, opposite the first dopant type of the Vt implant in FIG. 6A. According to one embodiment, the LDD 108 region may be N-type with the Vt implant operation being P-type. A halo implantation operation is an angled ion implantation process and can use any suitable method known in the art. The halo implantation operation introduces dopants of the same dopant type as the Vt implantation into the source 110 area and the drain 112 area, but not the channel region at the center (below the dummy gate 506).

According to one embodiment, the halo implantation operation may introduce P-type dopants although N-type dopants may be implanted in other embodiments. In one embodiment, the halo implantation operation may be used to introduce a mixture of indium and carbon, and in another embodiment, the halo implantation operation may be used to introduce indium and boron, such as present in BF₂.

Spacers 504 are formed using various methods known in the art and comprise oxide silicon nitride or any other suitable material. The source 110 and drain 112 are formed by source/drain implantation operation. The source 110 and drain 112 are formed of the same, second dopant type as LDD 108. In one embodiment, the LDD 108 and source 110/drain 112 are N-type regions, for example.

In FIG. 6C, inter layer dielectric (ILD) 508 is formed over the substrate 102 by depositing any suitable dielectric material and planarization, for example.

In FIG. 6D, the dummy gate 506, the dummy gate dielectric 601, and upper surface of the substrate 102 located between spacers 504 are removed to form a recess on the substrate 102 surface between the spacers 504 by etching, for example.

In FIG. 6E, a silicon epitaxial (Si-Epi) layer 602 is formed in the recess area over the substrate 102 located between the spacers 504, using epitaxial deposition or other suitable methods. The Si-Epi layer 602 is undoped and has a thickness of about 5 nm-40 nm in various embodiments. In some embodiments, an undoped SiC layer (not shown) may be also epitaxially deposited between the substrate 102 and the Si-Epi layer 601 and may have a thickness of about 2 nm-20 nm in various embodiments. The Silicon carbide (SiC) retards dopant diffusion.

In FIG. 6F, a gate dielectric 114, e.g., a high-k dielectric, is formed over the surface of the Si-Epi layer 602. The gate dielectric 114 may be formed using various suitable dielectric deposition processes. According to one embodiment, hafnium oxide (HfO) may be used, but other suitable dielectric materials may be used for the gate dielectric 114 in other embodiments. The gate dielectric 114 using a high-k dielectric has a thickness of 2 nm in one embodiment, but may have a thickness that ranges from about 1 nm to 20 nm in various other embodiments.

A metal gate layer 606 is formed over the gate dielectric 114 by depositing any suitable metal using conventional or later developed methods. Various patterning techniques may be used to pattern the metal gate layer 606 and the gate dielectric 114.

In FIG. 6G, a gate stack including the gate dielectric 114 and a gate 116 is defined by removing excess metal gate layer 606, e.g., using CMP. The gate 116 comprises metal in this example, but may comprise polysilicon or any other suitable materials in other embodiments. By the process in FIGS. 6A-6G, a selective dopant deactivation is performed in the region 118 underneath the gate 116, e.g., by replacing the doped upper substrate portion in the channel region (between spacers 504) with an undoped Si-Epi layer 602, and the Vt roll-off slope is reduced, which helps to reduce local device variability.

An aspect of this description relates to a transistor. The transistor includes a substrate. The transistor further includes a channel region comprising dopants of a first type. The transistor further includes a gate structure over the channel region. The transistor further includes a source comprising dopants of a second type. The transistor further includes a lightly doped drain (LDD) comprising dopants of the second type, wherein the LDD is over the source, and the channel region is in direct contact with the LDD. The transistor further includes a deactivated region in the channel region underneath the gate structure, wherein the deactivated region comprises a first region inside an epitaxial layer and a second region outside the epitaxial layer. In some embodiments, the LDD is in the epitaxial layer. In some embodiments, the gate structure overlaps the LDD. In some embodiments, the deactivated region extends lower than a bottommost surface of the LDD. In some embodiments, the channel region is in the epitaxial layer. In some embodiments, the transistor further includes a spacer along a sidewall of the gate structure. In some embodiments, the spacer is non-overlapping with the deactivated region.

An aspect of this description relates to a semiconductor device. The semiconductor device includes a substrate. The semiconductor device further includes a channel region comprising a doped region in the substrate and an undoped epitaxial layer over the doped region, wherein the doped region comprises dopants of a first type, and a bottom surface of the undoped epitaxial layer is below a top-most surface of the substrate. The semiconductor device further includes a gate structure over the channel region, wherein sidewalls of the gate structure are aligned with sidewalls of the undoped epitaxial layer. The semiconductor device further includes a source in the substrate, wherein the source comprises dopants of a second type, and the channel region is in direct contact with the source. The semiconductor device further includes a deactivated region in the substrate and underneath the gate structure, wherein the deactivated region includes the undoped epitaxial layer and a portion of the channel region. In some embodiments, the semiconductor device further includes a spacer along a sidewall of the gate structure. In some embodiments, the spacer overlaps the source. In some embodiments, the semiconductor device further includes an isolation structure in the substrate. In some embodiments, the source is between the isolation structure and the channel region. In some embodiments, the gate structure comprises a metal gate electrode. In some embodiments, the undoped epitaxial layer comprises silicon.

An aspect of this description relates to a semiconductor device. The semiconductor device includes a channel region comprising dopants of a first type in a substrate. The semiconductor device further includes an undoped epitaxial layer over the dopants of the channel region. The semiconductor device further includes a gate structure over the channel region. The semiconductor device further includes spacers along sidewalls of the gate structure. The semiconductor device further includes source/drain regions in the substrate on opposite sides of the gate structure, wherein each of the source/drain regions comprises dopants of second type, and an entirety of the spacers is over the source/drain regions. The semiconductor device further includes a deactivated region underneath the gate structure wherein dopants within the deactivated region are deactivated, and the deactivated region comprises the undoped epitaxial layer and a portion of the channel region. In some embodiments, the gate structure comprises a metal gate electrode. In some embodiments, the semiconductor device further includes an interlayer dielectric (ILD) over the substrate. In some embodiments, the ILD overlaps the source/drain regions. In some embodiments, the semiconductor device further includes an isolation structure in the substrate. In some embodiments, a maximum depth of the isolation structure is greater than a maximum depth of the source/drain regions.

The above method embodiment shows exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiment of the disclosure. Embodiments that combine different claims and/or different embodiments are within the scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure.

Claims

1. A transistor comprising: a substrate;a channel region comprising dopants of a first type;a gate structure over the channel region;a source comprising dopants of a second type;a lightly doped drain (LDD) comprising dopants of the second type, wherein the LDD is over the source, and the channel region is in direct contact with the LDD; anda deactivated region in the channel region underneath the gate structure, wherein the deactivated region comprises a first region inside an epitaxial layer and a second region outside the epitaxial layer.

2. The transistor of claim 1, wherein the LDD is in the epitaxial layer.

3. The transistor of claim 1, wherein the gate structure overlaps the LDD.

4. The transistor of claim 1, wherein the deactivated region extends lower than a bottommost surface of the LDD.

5. The transistor of claim 1, wherein the channel region is in the epitaxial layer.

6. The transistor of claim 1, further comprising a spacer along a sidewall of the gate structure.

7. The transistor of claim 6, wherein the spacer is non-overlapping with the deactivated region.

8. A semiconductor device, comprising: a substrate;a channel region comprising a doped region in the substrate and an undoped epitaxial layer over the doped region, wherein the doped region comprises dopants of a first type, and a bottom surface of the undoped epitaxial layer is below a top-most surface of the substrate;a gate structure over the channel region, wherein sidewalls of the gate structure are aligned with sidewalls of the undoped epitaxial layer;a source in the substrate, wherein the source comprises dopants of a second type, and the channel region is in direct contact with the source; and a deactivated region in the substrate and underneath the gate structure, wherein the deactivated region includes the undoped epitaxial layer and a portion of the channel region.

9. The semiconductor device of claim 8, further comprising a spacer along a sidewall of the gate structure.

10. The semiconductor device of claim 9, wherein the spacer overlaps the source.

11. The semiconductor device of claim 8, further comprising an isolation structure in the substrate.

12. The semiconductor device of claim 11, wherein the source is between the isolation structure and the channel region.

13. The semiconductor device of claim 8, wherein the gate structure comprises a metal gate electrode.

14. The semiconductor device of claim 8, wherein the undoped epitaxial layer comprises silicon.

15. A semiconductor device, comprising: a channel region comprising dopants of a first type in a substrate;an undoped epitaxial layer over the dopants of the channel region;a gate structure over the channel region;spacers along sidewalls of the gate structure;source/drain regions in the substrate on opposite sides of the gate structure, wherein each of the source/drain regions comprises dopants of second type, and an entirety of the spacers is over the source/drain regions; anda deactivated region underneath the gate structure wherein dopants within the deactivated region are deactivated, and the deactivated region comprises the undoped epitaxial layer and a portion of the channel region.

16. The semiconductor device of claim 15, wherein the gate structure comprises a metal gate electrode.

17. The semiconductor device of claim 15, further comprising an interlayer dielectric (ILD) over the substrate.

18. The semiconductor device of claim 17, wherein the ILD overlaps the source/drain regions.

19. The semiconductor device of claim 15, further comprising an isolation structure in the substrate.

20. The semiconductor device of claim 19, wherein a maximum depth of the isolation structure is greater than a maximum depth of the source/drain regions.