TREA

SEMICONDUCTOR DEVICE HAVING WORD LINE STRUCTURE

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Information

  • Patent Application
  • 20230299161
  • Publication Number
    20230299161
  • Date Filed
    March 21, 2022
    2 years ago
  • Date Published
    September 21, 2023
    8 months ago
Information
Abstract
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a word line structure. The semiconductor substrate has an active region. The word line structure is disposed in the active region of the semiconductor substrate. The word line structure includes a first work function layer, a second work function layer, and a buffer structure. The second work function layer is on the first work function layer. The buffer structure is between the first work function layer and the second work function layer.
Description
Claims
  • 1. A semiconductor device, comprising: a semiconductor substrate having an active region; anda word line structure disposed in the active region of the semiconductor substrate, the word line structure comprising: a first work function layer;a second work function layer on the first work function layer; anda buffer structure between the first work function layer and the second work function layer.
  • 2. The semiconductor device of claim 1, wherein the buffer structure directly contacts the second work function layer.
  • 3. The semiconductor device of claim 1, wherein the buffer structure surrounds a plurality of surfaces of the second work function layer.
  • 4. The semiconductor device of claim 1, wherein the buffer structure comprises: a first buffer layer between the first work function layer and the second work function layer; anda second buffer layer on the second work function layer.
  • 5. The semiconductor device of claim 4, wherein the buffer structure directly contacts a top surface, a bottom surface, and a plurality of lateral surfaces of the second work function layer.
  • 6. The semiconductor device of claim 1, wherein the word line structure further comprises: a barrier layer between the buffer structure and the first work function layer.
  • 7. The semiconductor device of claim 6, wherein the barrier layer directly contacts the buffer structure and the first work function layer.
  • 8. The semiconductor device of claim 1, wherein the word line structure further comprises: a dielectric layer surrounding the first work function layer and the second work function layer, wherein the buffer structure and the dielectric layer comprise a same material.
  • 9. The semiconductor device of claim 1, wherein the buffer structure has a thickness from about 1 nm to about 2 nm.
  • 10. The semiconductor device of claim 1, wherein the first function layer comprises metal, and the second work function layer comprises doped polysilicon.
  • 11. A semiconductor device, comprising: a semiconductor substrate having a trench; anda word line structure disposed in the trench of the semiconductor substrate, the word line structure comprising: a doped-polysilicon layer; anda buffer structure directly contacting a bottom surface of the doped-polysilicon layer.
  • 12. The semiconductor device of claim 11, wherein the word line structure further comprises: a conductive layer, wherein the buffer structure is between the conductive layer and the bottom surface of the doped-polysilicon layer.
  • 13. The semiconductor device of claim 11, wherein the word line structure further comprises a dielectric layer on an inner sidewall of the trench, wherein the buffer structure directly contacts the dielectric layer.
  • 14. The semiconductor device of claim 13, wherein the buffer structure and the dielectric layer comprise an oxide material.
  • 15. The semiconductor device of claim 11, wherein the buffer structure further comprises a portion directly contacting a top surface of the doped-polysilicon layer.
  • 16. The semiconductor device of claim 15, further comprising: a dielectric structure in the trench and over the doped-polysilicon layer.
  • 17. The semiconductor device of claim 16, wherein the dielectric structure comprises a portion directly contacting the portion of the buffer structure.
  • 18. The semiconductor device of claim 11, wherein the word line structure further comprises: a barrier layer directly contacting the buffer structure.
  • 19. The semiconductor device of claim 18, wherein the buffer structure is between the doped-polysilicon layer and the barrier layer.
  • 20. The semiconductor device of claim 11, wherein the buffer structure has a thickness from about 1 nm to about 2 nm.