Patent Application
20240128260
The present application claims priority to Korean Patent Application No. 10-2022-0133652, filed Oct. 18, 2022, the entire contents of which are incorporated herein for all purposes by this reference.
The present disclosure relates generally to a semiconductor device including a MOSFET and a diode and a manufacturing method thereof. More particularly, the present disclosure relates to a semiconductor device including a MOSFET and a diode and a manufacturing method thereof, including a silicon carbide (SiC) MOSFET and an integrated Schottky bather diode that reduced the forward voltage drop (Vf) and the device area, and prevent switching oscillation caused by parasitic inductance.
Silicon carbide (SiC) is a material having a wider energy bandgap, a higher dielectric field, a higher saturated electron drift velocity, and higher thermal conductivity than silicon. Due to these excellent properties, SiC is attracting attention as a semiconductor material for high-temperature, high-voltage device applications.
A typical power metal-oxide-semiconductor field-effect transistor (power MOSPET) device has a body diode and uses the body diode as a free-wheeling diode during switching, so the use of a Schottky bather diode is not essential. However, in the case of a SiC MOSFET device, it has higher forward voltage drop (Vf) characteristics than a Si MOSFET device due to its intrinsic high energy band gap and high built-in potential.
Due to such high forward voltage drop, the SiC MOSFET device consumes a relatively large amount of power during switching compared to a Si MOSPET of the same voltage rating, and power consumption inevitably increases as the voltage rating increases. Therefore, for applications where power consumption is important, a SiC Schottky bather diode may be connected in parallel with the SiC MOSPET device and used externally (see
To overcome the above problems, the present inventors have conceived a novel semiconductor device including a MOSPET and a diode and a manufacturing method thereof, which will be described in detail later.
The foregoing is intended merely to aid in the understanding of the background of the present disclosure, and is not intended to mean that the present disclosure falls within the purview of the related art that is already known to those skilled in the art.
Documents of Related Art:
Accordingly, the present disclosure has been made keeping in mind the above problems occurring in the related art, and an objective of the present disclosure is to provide a semiconductor device including a MOSPET and a diode and a manufacturing method thereof, including a silicon carbide (SiC) MOSPET and an integral Schottky bather diode that reduce the forward voltage drop (Vf) reduction, manufacturing cost, and product size (area), and stabilize the switching waveform and reduce oscillation by reducing or eliminating parasitic inductance.
Another objective of the present disclosure is to provide a semiconductor device including a MOSPET and a diode and a manufacturing method thereof, in which unit cells having a hexagonal shape (e.g., in a plan or layout view) form a honeycomb structure in order to compensate for the area loss due to the Schottky bather diode and increase the channel density.
Still another objective of the present disclosure is to provide a semiconductor device including a MOSPET and a diode and a manufacturing method thereof, including a JFET region surrounding lower portions of a well and a high concentration impurity region to distribute current through an additional current path and thus improve the resistance characteristics of the device.
In order to achieve the above objectives, according to one aspect of the present disclosure, there is provided a semiconductor device including a substrate having a MOSPET region and a Schottky bather diode (SBD) region; a lightly doped second conductivity type drift region on the substrate in the MOSPET region and the SBD region; a first conductivity type well in the drift region and in the MOSPET region; a heavily doped second conductivity type source in the well; a gate in the MOSPET region and including a gate insulating film on the drift region and a gate electrode on the gate insulating film; and a JFET region in the drift region and below the gate.
According to another aspect of the present disclosure, the JFET region may surround or be in contact with one sidewall and a lower portion (e.g., a lowermost surface) of the well.
According to another aspect of the present disclosure, the semiconductor device may further include a first high concentration impurity region in contact with the source and the well in the MOSFET region and the JFET region, the first high concentration impurity region having a first conductive type; and a first ohmic contact in contact with at least part of the source and the first high concentration impurity region.
According to another aspect of the present disclosure, the semiconductor device may further include a second high concentration impurity region in the drift region and in the SBD region, the second high concentration impurity region having the first conductivity type.
According to another aspect of the present disclosure, the semiconductor device may further include a second ohmic contact on the second high concentration impurity region in the SBD region.
According to another aspect of the present disclosure, the semiconductor device may further include a contact region on the drift region in the SBD region.
According to another aspect of the present disclosure, there is provided a semiconductor device including a substrate having a plurality of MOSPET regions and at least one Schottky bather diode (SBD) region; a lightly doped second conductivity type drift region on the substrate in the MOSPET region and the SBD region; and a plurality of unit cells having a first substantially hexagonal shape (e.g., in a plan or layout view) and at least partially having a honeycomb structure, the unit cells comprising the MOSPET regions; wherein the at least one SBD region is between at least two of the unit cells and has a second substantially hexagonal shape (e.g., in the plan or layout view).
According to another aspect of the present disclosure, each of the unit cells may include a gate having a third substantially hexagonal shape (e.g., in the plan or layout view); a well in the drift region and below the gate; a source in contact with the well in the drift region; a first high concentration impurity region surrounded by the source in the drift region, the first high concentration impurity region having a first conductivity type; and a JFET region in the drift region and below the gate.
According to another aspect of the present disclosure, the semiconductor device may comprise two or more of the SBD regions, and the SBD regions may not be in contact with each other.
According to another aspect of the present disclosure, each of the SBD regions may have six outer surfaces in contact with respective unit cells.
According to another aspect of the present disclosure, each of the SBD regions may include a second high concentration impurity region in the drift region, the second high concentration impurity region having the first conductivity type; and a second ohmic contact on the second high concentration impurity region.
According to another aspect of the present disclosure, the semiconductor device may further include a source metal or source electrode covering the gate (e.g., on the drift region); and a drain metal or drain electrode under the substrate.
According to another aspect of the present disclosure, there is provided a semiconductor device including a substrate having a plurality of MOSPET regions and at least one Schottky bather diode (SBD) region; a lightly doped second conductivity type drift region on the substrate in the MOSPET regions and the at least one SBD region; and a plurality of unit cells having a first substantially hexagonal shape (e.g., in a plan or layout view) and at least a partial honeycomb structure, and arranged in n columns, the unit cells comprising the MOSPET regions; wherein the at least one SBD region is between at least two of the unit cells, has a second substantially hexagonal shape (e.g., in the plan or layout view), and may not be in adjacent ones of the n columns.
According to another aspect of the present disclosure, each SBD region may be directly surrounded by a subset of the plurality of unit cells.
According to another aspect of the present disclosure, the semiconductor device may comprise a plurality of the SBD regions, and the SBD regions may alternate with the unit cells in at least one of the n columns.
According to another aspect of the present disclosure, the SBD regions may have an area equal to or less than 25% or less of a total area of an active region (e.g., of the semiconductor device).
According to another aspect of the present disclosure, the semiconductor device may further include a heavily doped first conductivity type impurity region in the drift region (or at a surface thereof) and in a center of each of the SBD regions.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including forming a drift region on a substrate; forming unit cells in n columns, the unit cells comprising MOSPET regions; and forming SBD regions, wherein forming the unit cells may include forming second conductivity type MET regions having a substantially hexagonal shape (e.g., in the plan or layout view) in the drift region and in the MOSPET regions; forming first conductivity type wells in the MET regions; forming first high concentration impurity regions in the MET regions at positions in contact with the wells, the first high concentration impurity regions having a first conductivity type; forming first heavily doped second conductivity type sources in the wells; forming second sources in the drift region; and forming gates having a substantially hexagonal shape (e.g., in the plan or layout view) on the MET regions, the wells, wherein the sources have at least a partial honeycomb structure.
According to another aspect of the present disclosure, the SBD regions may not be in contact with each other.
According to another aspect of the present disclosure, the SBD regions may not be in consecutive ones of the n columns.
The above configurations may provide the following effects.
The integral silicon carbide (SiC) MOSPET and Schottky bather diode reduce forward voltage drop (Vf), manufacturing cost, and product size/area, and stabilize switching waveforms and reduce oscillation by reducing or eliminating parasitic inductance (e.g., between the SiC MOSPET and the Schottky bather diode).
In addition, by providing the unit cells with a hexagonal shape and/or a honeycomb structure, one may compensate for any area loss resulting from the Schottky bather diode with an increase in the channel density.
By surrounding the lower portions of the well and the high concentration impurity region with the JFET region, current distribution through formation of an additional current path can be achieved, and thus, the resistance of the device can be improved.
Meanwhile, the effects of the present disclosure are not limited to those described above, and other effects not stated explicitly may be understood from the following description and claims.
The above and other objectives, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The embodiments of the present disclosure can be modified in various forms. Therefore, the scope of the present disclosure should not be construed as being limited to the following embodiments, but should be construed on the basis of the descriptions in the appended claims. The embodiments of the present disclosure are provided for complete disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
As used herein, the singular forms may include the corresponding plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” and/or “comprising”, etc. when used herein specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.
As used herein, when an element (or layer) is referred to as being on another element (or layer), it can be directly on the other element, or one or more intervening elements (or layers) may be therebetween. In contrast, when an element is referred to as being directly on or above another component, no intervening element is therebetween. Further, the terms “on”, “above”, “below”, “upper”, “lower”, “one side”, “side surface”, etc. are used to describe one element's positional relationship to one or more other elements illustrated in the drawings.
Meanwhile, when an embodiment can be implemented differently, functions or operations described herein may occur in a different way from that described herein. For example, two consecutive functions or operations may be performed simultaneously, or the functions or operations may be performed in reverse sequence.
Hereinafter, a “first conductivity type” may refer to P-type doping, and a “second conductivity type” may refer to N-type doping. Alternatively, in some cases, the first conductivity type may be N-type, and the second conductivity type may be P-type, but the present disclosure not limited thereto.
Hereinafter, the semiconductor device 1 including integrated MOSPET and diode regions according to one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Referring to
A first region A1 serving as a MOSPET region and a second region A2 serving as a Schottky bather diode region are in the device 1, which will be described later.
Referring to
A drift region 110 may be on the substrate 101. The drift region 110 may include, for example, a SiC epitaxial layer grown on the SiC single crystal substrate 101 that maintains a specific crystalline orientation with respect to the crystal lattice of the substrate 101. The drift region 110 may be formed by, for example, chemical vapor deposition (CVD), but is not limited thereto, and may be formed by various other processes such as molecular beam epitaxy (MBE), sublimation epitaxy, and liquid phase epitaxy.
In addition, the drift region 110 may be or comprise a lightly doped second conductivity type impurity region having a lower doping concentration than the substrate 101, and may include, for example, phosphorus as the second conductivity type impurity. The drift region 110 may be in both the first region A1 and the second region A2.
In the first region A1, a well 120 may be in a surface of the drift region 110 or a junction gate field-effect transistor (MET) region 160 which will be described later. The well 120 may be or comprise a first conductivity type doped impurity region. A channel region may form in the well 120. In addition, a source 130 may be in the well 120. The source 130 may be or comprise a heavily doped second conductivity type impurity region. Here, the source 130 may have a higher doping concentration than the drift region 110.
In addition, the source 130 may be in contact with a lower portion or a lowermost surface of a gate 140, which will be described later. The source 130 may be in the first region A1. When a MOSPET of the semiconductor device 1 operates, a channel may form in the well 120 to secure a path for movement of carriers (e.g., electrons). Thus, electrons from a source electrode (which will be described later) may move to a drain metal or drain electrode 180 which will be described later, through the source 130 and the well 120, below a gate electrode 143.
In addition, in the first region A1, the gate 140 may be on the substrate 101 or the drift region 110. The gate 140 may be on the drift region 110 and may at least partially overlap the well 120 and the source 130.
The gate 140 may include a gate oxide film 141 on the drift region 110 and the gate electrode 143 on the gate oxide film 141. Thus, a lowermost surface of the gate oxide film 141 may be in contact with the well 120 and the source 130. The gate electrode 143 may be or comprise, for example, polysilicon doped with an impurity. In addition, an insulating film 145 may surround or cover the gate electrode 143 and the gate oxide film 141. The insulating film 145 may also cover sidewalls of the gate electrode 143 and the gate oxide layer 141 and may at least partially cover an upper surface of the gate electrode 143. The gate 140 may have a hexagonal shape in a plan or layout view, rather than a rectangular shape, and a detailed description thereof will be described later.
Next, in the first region A1, a high concentration impurity region 150 may be in the drift region 110 or the MET region 160. The high concentration impurity region 150 may be in the drift region 110 and may be in contact with the well 120 and the source 130. For example, the high concentration impurity region 150 may be or comprise a heavily doped first conductivity type impurity region, and may be in contact with the sidewall of each of the well 120 and the source 130 distal from the gate 140. In addition, an ohmic contact 151 in contact with a source metal or source electrode 170 may be on at least portions of uppermost surfaces of the high concentration impurity region 150 and the source 130. The ohmic contact 151 may comprise, but is not limited to, Ti or TiN.
In addition, in the first region A1, the MET region 160 may be in the drift region 110. The MET region 160 may be below the gate 140 in the drift region 110. For example, the JFET region 160 may be or comprise a second conductivity type doped impurity region, and preferably has a higher doping concentration than the drift region 110, but a lower doping concentration than the source 130. In addition, the MET region 160 is preferably below the gate 140 and adjacent to the channel region of the well 120. That is, the MET region 160 may be in contact with a sidewall of the well 120 adjacent to the gate 140.
In addition, the JFET region 160 may surround the well 120 and the high concentration impurity region 150. That is, the JFET region 160 may be deeper than the lowermost surface of the well 120 and the high concentration impurity region 150 in the drift region 110, and may at least partially surround the well 120 and the high concentration impurity region 150. By forming the MET region 160 in this manner, when a current moves from the drain metal 180 to the source metal 170, the current can move through the MET region 160 along a path below the gate 140, as well as a path below the well 120 and the high concentration impurity region 150. The additional current path facilitates or improves current distribution. This results in improving resistance characteristics of the device 1.
In addition, the source metal or source electrode 170 may be on the substrate 101 or the drift region 110 in the first region A1 and the second region A2. The source metal 170 may be on the drift region 110 and may cover the insulating film 145 and the ohmic contact 151, and may extend to the second region A2. The source metal 170 may include, but is not limited to, A1 or an A1 alloy.
In addition, the drain metal or drain electrode 180 may be under or on an opposite surface of the substrate 101. The drain metal 180 may be electrically connected to a drain terminal D. The drain metal 180 may include, but is not limited to, Ni or Ag. The drain metal 180 may be in both the first region A1 and the second region A2.
In addition, a high concentration impurity region 210 may be in the drift region 110 in the second region A2. For convenience of description, the above-described high concentration impurity region 150 is referred to as a “first high concentration impurity region 150”, and the high concentration impurity region 210 in the second region A2 is referred to as a “second high concentration impurity region 210”. The second high concentration impurity region 210 may be formed substantially simultaneously with the first high concentration impurity region 150 (e.g., in the same processing steps), but is not limited thereto. Thus, the second high concentration impurity region 210 may be or comprise a heavily doped first conductivity type impurity region. However, it should be noted that the second high concentration impurity region 210 is not an essential component of the present disclosure.
In addition, an ohmic contact 220 may be on the second high concentration impurity region 210 or the drift region 110 in the second region A2. The ohmic contact 220 may include, but is not limited to, Ti or TiN. It should be also noted that the ohmic contact 220 is not an essential component of the present disclosure. For example, in the case of a merged pin Schottky (MPS) diode, the ohmic contact 220 may be on the second high concentration impurity region 210, but in the case of a junction bather Schottky (JBS) diode, the ohmic contact 220 may not be on the second high concentration impurity region 210.
In addition, a contact region 230 may be on the drift region 110 in the second region A2 at a position adjacent to or in contact with the ohmic contact 220. The contact region 230 may be or comprise a metal layer, and may include, but is not limited to, Ni and/or Ti. The contact region 230 may improve bonding between the drift region 110 and the source metal 170.
Hereinafter, the problems of a conventional SiC MOSPET semiconductor device and the structure of the semiconductor device 1 including the integrated MOSPET and diode regions according to the present disclosure for solving the problems will be described in more detail with reference to the accompanying drawings.
A typical power metal-oxide-semiconductor field-effect transistor (power MOSPET) device has a body diode and uses the body diode as a free-wheeling diode during switching, so the use of a Schottky bather diode is not essential. However, in the case of a SiC MOSPET device, it has higher forward voltage drop (Vf) characteristics than a Si MOSPET device due to its intrinsic high energy band gap and high built-in potential.
Due to such high forward voltage drop, the SiC MOSPET device consumes a relatively large amount of power during switching, compared to a Si MOSPET of the same voltage rating, and power consumption inevitably increases as the voltage rating increases. Therefore, for applications where power consumption is important, a SiC Schottky bather diode may be connected in parallel with the SiC MOSPET device and is used externally (see
Referring to
In the semiconductor device 1, the gate 140 may have a hexagonal shape (e.g., in the plan or layout view). Here, the semiconductor device 1 may include a plurality of hexagonal gates 140, which may be arranged in a honeycomb pattern, for example. With this structure, there may be no loss of space, so space utilization may increase. For example, when a plurality of unit cells C having a hexagonal shape are in contact with each other, they may form n columns.
All the unit cells C may have substantially the same shape in the plan or layout view and the same cross-sectional shape. In each of the unit cells C, the gate 140 may have, for example, a hexagonal shape (e.g., in the plan or layout view). In addition, the well 120 may be below the gate 140. In addition, the source 130 may be in the well 120 and in contact with the well 120. The source 130 may have, for example, a substantially hexagonal shape (e.g., in the plan or layout view). In addition, the first high concentration impurity region 150 may be in the center of the unit cell region C. The first high concentration impurity region 150 may have, for example, a substantially hexagonal shape (e.g., in the plan or layout view). Finally, the MET region 160 may be below the gate 140. The MET region 160 may have, for example, a substantially hexagonal shape (e.g., in the plan or layout view). However, it should be noted that the examples of the shape of each component in the plan or layout view (except for the gate 140) are not limited by the above examples.
Here, the second region A2 may not be in a specific column. That is, in an mth column (0<m<n), a plurality of unit cells C having substantially the same shape may repeat along the column direction.
In addition, the second region A2 may be in an m−1th and/or m+1th column adjacent to the unit cells C in the mth column. For example, the second region A2 and the first region A1 may alternate in the m−1th column and/or m+1th column along the column direction. That is, a column comprising sequential, alternating first regions A1 and second regions A2 may repeat, such that the outer surfaces of each hexagonal second region A2 are adjacent to or surrounded by respective unit cells C or first regions A1. However, the arrangement of the second regions A2 in the m−1th and/or m+1st column is not limited to the above example, and the second regions A2 may be at least partially repeated along the column direction. Alternatively, the first regions A1 may be repeated along the column direction.
With this structure, the MOSPET region A1 and the integral Schottky bather diode region A2 may reduce the forward voltage drop (Vf), the manufacturing cost, and the product area, and stabilize the switching waveform and reduce oscillation by reducing or eliminating parasitic inductance. In addition, the unit cells C having a hexagonal shape and/or a honeycomb structure may compensate for the area loss resulting from the Schottky bather diode region(s) A2 by an increase in the channel density.
Here, it is preferable that the area of the Schottky bather diode A2 is equal to less than 25% of the total area of an active region (e.g., of the semiconductor device 1), but the scope of the present disclosure is not limited by the numerical range.
Hereinafter, the method of manufacturing the semiconductor device 1 including the integrated MOSPET and diode regions according to embodiment(s) of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the sequence of the steps of the manufacturing method is not limited to the order described below.
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As described above, in the unit cell C, the gate 140 may have a hexagonal shape. In addition, the well 120 may be below the gate 140. In addition, the source 130 may be in the well 120 and in contact with the well 120. The source 130 may have, for example, a substantially hexagonal shape. In addition, the first high concentration impurity region 150 may be in the center of the unit cell C. The first high concentration impurity region 150 may have, for example, a substantially hexagonal shape. Finally, the JFET region 160 may be below the gate 140. The JFET region 160 may have, for example, a substantially hexagonal shape. As described above, it should be noted that the shape of each component is exemplary for description of the present disclosure.
The foregoing detailed description may be merely an example of the present disclosure. Also, the inventive concept is explained by describing various embodiments and may be used in various combinations, modifications, and environments. That is, the inventive concept may be amended or modified without departing from the scope of the technical idea and/or knowledge in the art. The foregoing embodiments are for illustrating various modes for implementing the technical idea of the present disclosure, and various modifications may be made therein according to specific application fields and/or uses of the present disclosure. Therefore, the foregoing detailed description of the present disclosure is not intended to limit the inventive concept to the disclosed embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0133652 | Oct 2022 | KR | national |
