The present disclosure is based on Japanese Patent Application No. 2011-210676 filed on Sep. 27, 2011 and Japanese Patent Application No. 2012-161523 filed on Jul. 20, 2012, the disclosures of which are incorporated herein by reference.
The present disclosure relates to a semiconductor device including a vertical semiconductor element.
In a semiconductor device including a vertical MOS transistor, holes are normally extracted from a p type base region. However, in a case where a voltage drop in an extraction path is too large, an avalanche current flows toward an n+ type source region to operate a parasitic bipolar transistor. Thus, an avalanche resistance is reduced. In order to improve the avalanche resistance, it is necessary not to operate the parasitic bipolar transistor formed by the n+ type source region, the p type base region, and an n− type drift layer.
In order to achieve that, conventionally, a structure in which p type impurities are deeply diffused between adjacent trench gates to form a high-concentration p+ type body layer so as to restrict operation of the parasitic bipolar transistor has been proposed (for example, Patent Document 1). Using the above-described structure, an avalanche breakdown, which has occurred at a lower portion of the trench gate on which electric field concentrates in a conventional structure, can be caused on a joint surface of the p+ type body layer and the n− type drift layer. Thus, holes, which cause operation of the parasitic bipolar transistor, can be extracted to a source electrode through a high concentration (low resistance) path so as not to operate the parasitic bipolar transistor.
However, in a case where the above-described structure is applied to a vertical MOS transistor having a super junction structure, a high-temperature and long-time heat treatment is necessary to diffuse a high-concentration p+ type body layer to be deeper than a trench filled with a gate electrode. By the heat treatment, impurities in an n type region (n type column) which is a current path of the super junction structure and a p type region (p type column) for charge compensation are diffused each other, charges are compensated, and an on-resistance increases.
An object of the present disclosure is to restrict increase in on-resistance in a semiconductor device that includes a vertical semiconductor element having a super junction structure.
A semiconductor device according to an aspect of the present disclosure includes a vertical semiconductor element that includes a semiconductor substrate, a drift layer, a second conductivity-type region, a base region, a first impurity region, a first trench, a first gate insulation film, a gate electrode, a contact region, a front surface electrode, a rear surface electrode, a second trench, a second gate insulation film, and a dummy gate electrode and applies electric current between the front surface electrode and a rear surface electrode based on voltage application to the gate electrode.
The semiconductor substrate has a first conductivity-type or a second conductivity-type and has a main surface and a rear surface. The drift layer has the first conductivity-type and is formed to the main surface side of the semiconductor substrate. The second conductivity-type region is formed to the main surface side of the semiconductor substrate and is arranged alternately with the drift layer to form a super junction structure. The base region has the second conductivity-type and is formed above the super junction structure. The first impurity region has the first conductivity-type, is formed at a surface portion of the base region, and has an impurity concentration higher than the drift layer. The first trench penetrates the first impurity region and the base region to reach the first conductivity-type region in the super junction structure. The first gate insulation film is formed on an inner wall of the first trench. The gate electrode is formed on a surface of the first gate insulation film and fills the first trench to form a trench gate structure. The contact region has the second conductivity-type and is formed at the surface portion of the base region on an opposite side of the first impurity region from the first trench. The contact region has an impurity concentration higher than the base region. The front surface electrode is electrically connected to the first impurity region and the contact region. The rear surface electrode is electrically connected to the semiconductor substrate. The second trench penetrates the base region to reach the super junction structure and is formed to be deeper than the first trench. The second gate insulation film is formed on an inner wall of the second trench. The dummy gate electrode is formed on a surface of the second gate insulation film and fills the second trench to form a dummy gate structure.
In the semiconductor device, the second trench forming the dummy gate structure is formed to be deeper than the first trench forming the trench gate structure. Thus, an avalanche resistance can be improved and an increase in on-resistance can be restricted.
In a manufacturing method of a semiconductor device including a vertical semiconductor element according to another aspect of the present disclosure, a semiconductor substrate of a first conductivity-type or a second conductivity-type having a main surface and a rear surface is prepared. A drift layer of the first conductivity-type is formed to the main surface side of the semiconductor substrate and a second conductivity-type region is formed in the drift layer to form a super junction structure in which a first conductivity-type region provided by a remaining region of the drift layer at which the second conductivity-type region is not formed and the second conductivity-type region are alternately arranged. A base region of the second conductivity-type is formed above the super junction structure. A mask having a first opening portion and a second opening portion wider than the first opening portion is arranged above the base region and a first trench having a width corresponding to the first opening portion and a second trench having a width corresponding to the second opening portion and deeper than the first trench are formed by etching using the mask. Inner walls of the first and second trenches are covered by gate insulation films. A trench gate structure is formed by forming a gate electrode on a surface of the gate insulation film in the first trench, and a dummy structure is formed by forming a dummy gate electrode on a surface of the gate insulation film in the second trench. A first impurity region of the first conductivity-type having an impurity concentration higher than the drift layer is formed at a surface portion of the base region. A contact region of the second conductivity-type is formed at the surface portion of the base region on an opposite side of the first impurity region from the first trench. The contact region has an impurity concentration higher than the base region. A front surface electrode electrically connected to the first impurity region and the contact region is formed. A rear surface electrode electrically connected to the semiconductor substrate is formed.
As described above, in a case where a width of the second opening portion for forming the second trench is set to be wider than the first opening portion for forming the first trench, the second trench is formed deeper than the first trench by a micro loading effect when forming the trenches. Accordingly, the semiconductor device that can restrict an increase in on-resistance can be manufactured.
The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
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a) is a diagram illustrating an electric field strength distribution in a depth direction in a case where a dummy gate structure is applied to a MOS transistor having a super junction structure,
A first embodiment of the present disclosure will be described. In the present embodiment, a semiconductor device that includes a vertical MOS transistor as a vertical semiconductor element will be described as an example.
In the semiconductor device according to the present embodiment illustrated in
In the n type drift layer 2, as illustrated in
For example, when a breakdown voltage is anticipated at about 600 V due to the super junction structure, a depth of the n type drift layer 2 is set to 30 through 50 for example, 45 μm, a pitch (a column pitch) between the n type region 2b and the p type region 3 is set to 6.0 a ratio of widths of the n type region 2b and the p type region 3 is set to 1:1, and an area ratio of the cell region Rc is set to 1:1.
On surfaces of the n type regions 2b and the p type regions 3, a p type base region 4 is formed. For example, the p type base region 4 has a p type impurity concentration of 1.0×1017 cm−3 and has a depth of 1.0 μm. At a surface of the p type base region 4, n+ type impurity regions 5 and p+ type contact regions 6 are formed. The n+ type impurity regions 5 have an impurity concentration higher than the n type drift layer 2 and become a source region. The p+ type contact regions 6 have an impurity concentration higher than the p type base region 4. The n+ type impurity regions 5 have an n type impurity concentration of 1.0×102° cm−3 and have a depth of 0.4 μm, for example. The p+ type contact regions 6 have a p type impurity concentration of 1.0×1020 cm−3 and have a depth of 0.4 μm, for example.
A plurality of first trenches 7 penetrating the n+ impurity region 5 and the p+ type base region 4 to reach the n type region 2b and having a longitudinal direction in a direction perpendicular to a paper sheet is arranged at equal intervals. In the present embodiment, the first trenches 7 are formed at positions where the n type regions 2b are formed, and the p type regions 3 are disposed between the adjacent first trenches 7. Gate insulation films 8 are formed to cover surfaces of the first trenches 7, and gate electrodes 9 made of, for example, doped Poly-Si are formed on surfaces of the gate insulation films 8 to fill the first trenches 7. These form a trench gate structure. The first trenches 7 forming the trench gate structure are not illustrated in
Similarly, between the first trenches 7, second trenches 10 penetrate the p+ type base region 4 to reach the p type regions 3. The second trenches 10 have a longitudinal direction in a direction perpendicular to the paper sheet. In the present embodiment, the first trenches 7 are formed at positions where the p type regions 3 are formed. To cover surfaces of the second trenches 10, gate insulation films 11 are formed. The second trenches 10 are deeper and wider than the first trenches 7. For example, each of the second trenches 10 has a depth of 3.8 μm and a width of 3.0 μm. In the second trenches 10, dummy gate electrodes 12 made of, for example, doped Poly-Si are formed. These form a dummy gate structure.
Furthermore, between the first trenches 7, p+ type body layers 13 having a p type impurity concentration higher than the p type base region 4 are formed. For example, each of the p+ type body layer 13 has a p type impurity concentration of 1.0×1019 cm−3, and has a depth of 2.0 μm, which is shallower than the first trenches 7 and the second trenches 10.
Above the trench gate structure, an interlayer insulation film 14 is formed to cover the gate electrodes 9. In addition, a front surface electrode 15 forming a source electrode is formed. The front surface electrode 15 is electrically connected with the n+ type impurity regions 5, the p+ type contact regions 6, and the dummy gate electrodes 12 through contact holes formed in the interlayer insulation film 14. In addition, a rear surface electrode 16 serving as a drain electrode is formed on the rear surface of the n+ type substrate 1, which serves as a drain region, and the vertical MOS transistor is formed.
In the vertical MOS transistor having the above-described structure, for example, when a gate voltage is not applied to the gate electrode 9, a channel is not formed at the surface portion of the p type base region 4, and electric current between the front surface electrode 15 and the rear surface electrode 16 is interrupted. When a gate voltage is applied, a conductivity-type of a portion of the p type base region 4 being in contact with a side surface of the first trench 7 is reversed in accordance with a voltage value of the gate voltage to form a channel, and electric current flows between the front surface electrode 15 and the rear surface electrode 16.
In addition, in the vertical MOS transistor having the above-described structure, bottom portions of the second trenches 10, which form the dummy gate structure, is deeper than bottom portions of the first trenches 7, which form the trench gate structure. Thus, electric field concentration occurs at the bottom portions of the second trenches 10, and an avalanche breakdown occurs at the bottom portions. Then, holes generated by the avalanche breakdown are extracted along the side surfaces of the second trenches 10 to the front surface electrode 15 through the p+ type contact regions 6. Thus, holes can be restricted from approaching a parasitic bipolar transistor formed by the n+ type impurity region 5, the p type base region 4, and the n− type drift layer 2, and operation of the parasitic bipolar transistor can be restricted. Accordingly, an avalanche resistance can be improved.
Subsequently, a manufacturing method of the semiconductor device including the vertical transistor according to the present embodiment will be described with reference to
In a process illustrated in
In a process illustrated in
In a process illustrated in
In a process illustrated in
Although it is not illustrated, an ion implantation of n type impurities and an ion implantation of p type impurities are performed to the surface portion of the p type base region 4 to form the n+ type impurity regions 5 and the p+ type contact regions 6. These are formed by repeatedly performing a forming process of a mask having opening at positions where respective regions will be formed and an ion implantation process to the surface of the p+ type base region 4. Although the n+ type impurity regions 5 and the p+ type contact regions 6 are formed after forming the trench gate structure, the n+ type impurity region 5 and the p+ type contact regions 6 may also be formed after forming the p type base region 4 and before forming the trench gate structure.
In a process illustrated in
As described above, in the semiconductor device including the vertical MOS transistor according to the present embodiment, the bottom portion of the second trenches 10 forming the dummy gate structure is located at positions deeper than the bottom portions of the first trenches 7 forming the trench gate structure. Thus, an electric field concentration occurs at the bottom portions of the second trenches 10, and an avalanche breakdown occurs at the bottom portions. Then, holes generated by the avalanche breakdown can be extracted along the side surfaces of the second trenches 10 to the front surface electrode 15 through the p+ type contact regions 6. Thus, the holes can be restricted from approaching a parasitic bipolar transistor formed by the n+ type impurity region 5, the p type base region 4, and the n− type drift layer 2, and operation of the parasitic bipolar transistor can be restricted. Accordingly, the avalanche resistance can be improved.
Because the avalanche resistance can be improved by the structure in which the second trenches 10 are deeper than the first trenches 7, it is not necessary to form the p+ type body layer 13 to be deeper than the trench gate structure. Thus, it is not necessary to perform the heat treatment in the forming process of the p+ type body layer 13 at high-temperature for a long time as the conventional art. Thus, the present embodiment can restrict generation of a problem that the impurities in the n type regions 2b of the current path of the super junction structure and the impurities in the p type region 3 for charge compensation are diffused each other, the charges are compensated, and the on-resistance increases. Although formation of the p+ type body layer 13 is unnecessary, formation of the p+ type body layer 13 makes extraction of the holes easy. Thus, operation of the bipolar transistor can be more restricted, and the avalanche resistance can be more improved.
Furthermore, as the present embodiment, when the dummy gate structure is formed at positions where the p type regions 3 are formed in the super junction structure, the trench gate structures are formed at all positions where the n type regions 2b are formed. Thus, a forming area of the trench gate structure per the same chip area increases, and the on-resistance can be reduced.
A second embodiment of the present disclosure will be described. In the present embodiment, a configuration of the super junction structure is changed with respect to the first embodiment, and the other part is similar to the first embodiment. Thus, only a part different from the first embodiment will be described.
In this way, the dummy gate structure may be formed at positions where the n type regions 2b are formed. In a case with the above-described structure, because the second trenches 10 are disposed at the positions where the n type regions 2b are formed, the number of the first trenches 7 is limited. Thus, compared with the first embodiment, the forming area of the trench gate structure per the same chip area is reduced. In view of reduction of the on-resistance, the structure of the first embodiment has an advantage. However, when an equipotential distribution in the super junction structure is confirmed, a potential distribution is less likely to expand in the p type regions 3 compared with the n type regions 2b. Thus, compared with a case where the dummy gate structure is disposed at the positions where the n type regions 2b are formed, an advantage due to the depth of the dummy gate structure is less likely to be obtained. Thus, in the structure according to the present embodiment, by forming the dummy gate structure to be deeper, a generation position of an avalanche breakdown can be easily controlled, the operation of the parasitic bipolar transistor can be restricted more certainty, and the avalanche resistance can be improved.
A third embodiment of the present disclosure will be described. In the present embodiment, a configuration of the super junction structure is changed with respect to the first embodiment, and the other part is similar to the first embodiment. Thus, only a part different from the first embodiment will be described.
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As illustrated in
A fourth embodiment of the present disclosure will be described. In the present embodiment, a configuration in the vicinity of the dummy gate structure is changed with respect to the first embodiment, and the other part is similar to the first embodiment. Thus, only a part different from the first embodiment will be described.
Note that the above-described configuration can be manufactured by a manufacturing method basically similar to the manufacturing method of the semiconductor device according to the first embodiment. For example, after the process illustrated in
A fifth embodiment of the present disclosure will be described. In the present embodiment, a layout of the super junction structure is changed with respect to the first embodiment, and the other part is similar to the first embodiment. Thus, only a part different from the first embodiment will be described.
Like this, the n type region 2b and the p type region 3 may also be alternately repeated from the center of the cell region Rc in the radial direction by arranging the p type region 3 in the dotted pattern, not by alternately arranging the n type region 2b and the p type region 3 in the stripe pattern.
A sixth embodiment of the present disclosure will be described. In the present embodiment, a connection destination of the dummy gate electrodes 12 is changed with respect to the first embodiment, and the other part is similar to the first embodiment. Thus, only a part different from the first embodiment will be described.
Like this, the dummy gate electrodes 12 can also be fixed to the gate potential not to the source potential. Note that the dummy gate electrodes 12 can be in a floating state. However, it is preferable to fix the dummy gate electrodes 12 to the source potential or the gate potential so that an avalanche breakdown occurs certainly at the dummy gate electrodes 12. In a case where the dummy gate electrodes 12 are in the floating state, a change (curve) in equipotential lines in semiconductor is smaller than a case where the dummy gate electrodes 12 are fixed to a potential. Thus, it is preferable to fix the dummy gate electrodes 12 to the potential in order to generate more electric field concentration due to a large change in equipotential lines and to cause an avalanche breakdown more easily.
A seventh embodiment of the present embodiment will be described. In the above-described first embodiment, the trenches 2a are formed with respect to the n type drift layer 2, and the p type regions 3 are formed in the trenches 2a to fill the trenches 2a. However, the p type regions 3 can also be formed by an ion implantation to the n type drift layer 2.
Specifically, after a part of the whole thickness of the n type drift layer 2 is formed by epitaxial growth above the main surface 1a of the n+ type substrate 1, the p type impurities are ion-implanted to the portions where the p type regions 3 will be formed. Then, after a part of the whole thickness of the n type drift layer 2 is further formed by epitaxial growth, the p type impurities are ion-implanted to portions where the p type regions 3 will be formed. Also after that, an epitaxial growth of a part of the whole thickness of the n type drift layer 2 and an ion implantation process of the p type impurities to form the p type regions 3 are repeated and a heat treatment is performed so that the n type drift layer 2 is formed to have a desired thickness and the p type regions 3 are formed at positions of the ion implantation. Accordingly, even when a forming depth of the p type regions 3 is deep, the p type regions 3 can be formed by ion implantation. In a case where the p type regions 3 are formed by the above-described way, the p type impurities implanted in each of the ion implantation processes are thermally diffused to equal distance from the positions where the p type impurities are implanted. Thus, the p type regions 3 have a shape in which a width changes in multiple stages as illustrated in
As described above, the p type regions 3 can also be formed by the ion implantation of the p type impurities to the n type drift layer 2 not by filling the trenches 2a formed in the n type drift layer 2.
In each of the above-described embodiments, the second trenches 10 for forming the dummy gate structure are disposed between the first trenches 7 for forming the trench gate structure. A forming ratio of the second trenches 10 to the first trenches 7 may be set optionally. In other words, it is not necessary to form the second trenches 10 between all the first trenches 7. One line of the second trenches 10 may be formed for every multiple lines of the first trenches 7.
In the fourth embodiment, the case where the p type high concentration regions 30 are formed with respect to the configuration of the first embodiment has been described. However, the p type concentration regions 30 may be formed with respect to the second or the third embodiment.
In each of the above-described embodiments, the case where the manufacturing process is simplified by forming the first trenches 7 and the second trenches 10 at the same time has been described. However, it is not always necessary to form the first trenches 7 and the second trenches 10 at the same time. In other words, it is only necessary to form the second trenches 10 for forming the dummy gate structure to be deeper than the first trenches 7 for forming the trench gate structure and it is not always necessary to form the first trenches 7 and the second trenches 10 at the same time. In a case where the first trenches 7 and the second trenches 10 are not formed at the same time, it is not necessary to set the width of the second trenches 10 to be wider than the width of the first trenches 7. When the width of the second trenches 10 is set to be narrower than the width of the first trenches 7, an avalanche breakdown occurs more likely to occur at the bottom portions of the second trenches 10.
In each of the above-described embodiments, the shape of the second trenches 10 for forming the dummy gate structure may be different from the shape of the first trenches 7 so that an avalanche breakdown is likely to occur at the bottom portions of the second trenches 10.
In
In
Furthermore, by limiting the forming positions of the second trenches 10, an avalanche breakdown is more likely to occur at the bottom portions of the second trenches 10.
In the above-described embodiments, an n channel type MOS transistor in which a first conductivity-type is n type and a second conductivity-type is p type has been described. However, the present disclosure can also be applied to a p channel type MOS transistor in which conductivity-types of respective components forming elements are inversed. In addition, not limited to the MOS transistors, the present disclosure can also be applied to an IGBT, and a configuration similar to each of the above-described configuration can be applied. In this case, a p+ type substrate may be used instead of the n+ type substrate.
In the above-described embodiments, the trenches 2a are formed to the n− type drift layer 2, and the trenches 2a are filled with the p type regions 3 to form the super junction structure. However, this is one example of a forming method of the super junction structure, and the super junction structure may be formed by other method. For example, when the n− type drift layer 2 is grown, an ion implantation of the p type impurities may be performed to form a part of the p type regions 3 after growing the n− type drift layer 2 for a predetermined thickness, and they may be repeated to form the super junction structure.
In the above-described embodiment, cases where silicon is used as semiconductor material have been described. However, the present disclosure can also be applied to a semiconductor substrate used in a manufacture of a semiconductor device in which other semiconductor material such as silicon carbide or compound semiconductor is used.
The above-described dummy gate structure can be applied to various transistors to which a trench gate structure is applied, such as a MOS transistor, a DMOS, or an IGBT having a super junction structure. Especially when the above-described dummy gate structure is applied to the MOS transistor having the super junction structure, an effect is high. This is because, when a dummy trench structure is included, a breakdown voltage is less likely to decrease in a MOS transistor having a super junction structure than in a DMOS or an IGBT.
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Number | Date | Country | Kind |
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2011-210676 | Sep 2011 | JP | national |
2012-161523 | Jul 2012 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2012/005463 | 8/30/2012 | WO | 00 | 2/18/2014 |