Patent Application
20170133316
Many traditional semiconductor devices have essentially similar shapes: a housing with thin leads extending from it. The housing can be in form of a solid rectangle that serves to enclose and protect the circuitry on the inside. Protruding through the housing are the leads which are used to electrically connect the device to other components or circuits. For example, this form factor is used for some types of insulated-gate bipolar transistor (IGBT).
Because semiconductor devices are used for controlling electric current, their efficiency in doing so play an important role in the efficiency of the overall apparatus where they are being used. For instance, the performance and efficiency of a power inverter—a converter of direct current (DC) to alternating current (AC)—depends on the efficiency of the semiconductors devices in its circuits. The efficiency of the apparatus, in turn, can affect the performance of some larger system. For example, in an electric vehicle (e.g., a plug-in electric vehicle or a hybrid vehicle) the range of travel by electric power before one has to recharge the battery is an important characteristic. Therefore, an improved semiconductor device can improve the performance and efficiency of electric vehicles and other systems.
In a first aspect, a semiconductor device comprises: a housing; a substrate inside the housing; a semiconductor circuit on the substrate; and first and second planar busbars electrically connected to the semiconductor circuit, the first and second planar busbars being parallel to each other and extending away from the semiconductor circuit in opposite directions through respective openings in the housing.
Implementations can include any or all of the following features. The second planar busbar is in a different plane than the first planar busbar such that there is an offset between the first and second planar busbars. The semiconductor circuit is positioned between the second planar busbar and the substrate. The offset accommodates attachment of a distal end of the second planar busbar to a corresponding first planar busbar from an adjacent semiconductor device. The first planar busbar is configured to have a planar terminal attached to it such that the planar terminal is on a same side of the first planar busbar as the semiconductor circuit. The second planar busbar is configured to have an attachment to a planar terminal such that the planar terminal is positioned on an opposite side of the second planar busbar than the semiconductor circuit. The housing is configured so that the planar terminal extends across the housing toward the attachment. The planar terminal contains a contact portion offset from a main portion thereof by an offsetting portion, and wherein the contact portion abuts the second planar busbar at the attachment, and wherein the main portion extends along the housing. The substrate includes a direct bonded copper structure.
In a second aspect, a semiconductor assembly comprises: a first semiconductor device comprising: a first housing; a first substrate inside the first housing; a first semiconductor circuit on the first substrate; and first and second planar busbars electrically connected to the first semiconductor circuit, the first and second planar busbars being parallel to each other and extending away from the first semiconductor circuit in opposite directions through respective openings in the first housing; a second semiconductor device comprising: a second housing; a second substrate inside the second housing; a second semiconductor circuit on the second substrate; and third and fourth planar busbars electrically connected to the second semiconductor circuit, the third and fourth planar busbars being parallel to each other and extending away from the second semiconductor circuit in opposite directions through respective openings in the second housing, wherein the second planar busbar of the first semiconductor device is attached to the third planar busbar of the second semiconductor device; a first planar terminal attached to the first planar busbar of the first semiconductor device; and a second planar terminal attached to the fourth planar busbar of the second semiconductor device.
Implementations can include any or all of the following features. Each of the second and fourth planar busbars is in a different plane than a corresponding one of the first and third planar busbars such that their offsets exists between respective planar busbars. The offsets accommodate attachment of the second planar busbar to the third planar busbar. The first planar busbar is configured to have the first planar terminal attached to it such that the first planar terminal is on a same side of the first planar busbar as the first semiconductor circuit. The fourth planar busbar is configured to have an attachment to the second planar terminal such that the second planar terminal is positioned on an opposite side of the fourth planar busbar than the second semiconductor circuit. The first and second housings are configured so that the second planar terminal extends across the first and second housings toward the attachment. The second planar terminal contains a contact portion offset from a main portion thereof by an offsetting portion, and wherein the contact portion abuts the fourth planar busbar at the attachment, and wherein the main portion extends along the first and second housings. The semiconductor device further comprises a capacitor, wherein the first and second planar terminals connect the capacitor to the first and second semiconductor devices.
In a third aspect, a method comprises: positioning a first semiconductor device near a second semiconductor device, the first semiconductor device having first and second planar busbars parallel to each other and extending in opposite directions through respective openings in a first housing, the second semiconductor device having third and fourth planar busbars parallel to each other and extending in opposite directions through respective openings in a second housing; attaching the second planar busbar of the first semiconductor device to the third planar busbar of the second semiconductor device; positioning a first planar terminal adjacent the first planar busbar of the first semiconductor device, and positioning a second planar terminal adjacent the fourth planar busbar of the second semiconductor device; and attaching the first planar terminal to the first planar busbar, and attaching the second planar terminal to the fourth planar busbar. Attaching the first planar terminal to the first planar busbar comprises accessing the first planar terminal from a same side of the first planar busbar as where a semiconductor circuit of the first semiconductor device is located. Attaching the second planar terminal to the fourth planar busbar comprises accessing the second planar terminal from an opposite side of the fourth planar busbar than where a semiconductor circuit of the second semiconductor device is located.
This document describes examples of systems and techniques relating to improved semiconductor devices. In some implementations, a semiconductor device has relatively large and planar high-voltage terminals and/or busbars that are stacked on top of each other. These planar terminals/busbars and their arrangement with regard to the device as a whole can allow more efficient semiconductor operation and provide a convenient manufacturing process. For example, some parts of systems that are traditionally arranged around the device can instead be integrated into the same package as the device. This can improve the device's electrical and thermal performance, reduce its inductance, and lower the manufacturing and assembly costs.
Some implementations feature a co-pack design where one die (e.g., an IGBT and a diode) is included in a separate housing to form an individual device. Such devices can then be paired with each other to form the intended circuit, for example an inverter or other power electronics component. This can reduce the number of manufacturing steps, for example so that sintering is only performed on top and bottom sides of the co-pack with two step sintering. This can significantly simplify the manufacturing process and improve the yield rate. As another example, reliability validation testing can be simplified.
Some examples herein mention IGBTs or power inverters. This is for illustrative purposes only and other implementations include transistors other than an IGBT and/or an apparatus other than an inverter.
In a conventional IGBT, the module essentially consists of a substrate with four semiconductor circuits (also referred to as silicon dies) positioned in a generally rectangular arrangement on its surface. The module then has two busbars soldered to the silicon dies so that they extend away from the module. That is, each of the busbars is positioned on top of two of the silicon dies so that one busbar end is on the substrate and the other end extends beyond the edge of the substrate. These busbars are usually parallel to each other and spaced apart some distance that essentially corresponds to the positioning of the silicon dies on the substrate. In operation, current flows into the semiconductor device through one of the busbars, passes through the silicon dies, and flows out of the device through the other busbar.
One of the electrical characteristics that negatively affect semiconductor device performance is its inductance. It is therefore desirable to lower the inductance of a device without diminishing its ability to conduct and convert current. In the IGBT describe above, the inductance is proportional to the area between the busbars. Looking at the IGBT at a higher level, the individual silicon dies are connected to each other by bond wires that also connect them to one or more of the three leads extending from the housing. The bond wires often loop up in between two silicon dies, or between a die and the lead. In that context, the inductance is proportional to the area under the loop of the bond wire. As such, the efficiency of the semiconductor device can be improved by reducing the area between busbars or the area under bond wire loops.
Semiconductor circuits are implemented on top of the substrate. Here, silicon dies 106A-B are shown. These silicon dies contain the circuitry that defines the particular mode(s) of operation of the overall semiconductor assembly. In some implementations, the silicon dies define an IGBT device. For example, the silicon dies can be manufactured as chips (sometimes referred to as silicon chips) that are then mounted onto the top surface of the substrate.
In this example, the semiconductor device has the stacked planar terminals 102A-B that abut the silicon dies 106A-B, respectively. The stacked planar terminals have an arbitrary length extending toward the left in the figure. Each of the terminals forms a complete plane, can be made of any conductive material, and can be soldered to its respective silicon die(s). The planar terminal 102A here abuts the silicon die 106A and is labeled positive (+) for reference. The planar terminal 102B here abuts the silicon die 106B and is labeled negative (−) for reference. That is, the terminals are stacked on top of each other and in this example the negative terminal overlaps the positive one. A separation 108 is here formed between the planar terminals.
Particularly, because the silicon dies 106A-B are in a common plane (on top of the substrate) the planar terminal 102B has an offsetting portion 110 along the entire width of the plane so as to provide a contact portion 112 that abuts the silicon die 106B. In some implementations, the contact portion forms a plane that is parallel to, and offset from, the plane of the main portion of the planar terminal 102B. The offsetting portion can be formed using any suitable technique, such as by stamping or bending.
A housing 114 encloses at least part of the semiconductor device. The housing can have one or more openings. In some implementations, the housing has a common opening 116 through which the planar terminals 102A-B extend. For example, after the substrate, the silicon dies and the planar terminals are assembled, the housing can be overmolded on that assembly so that the terminals extend from the enclosed structure.
An electric insulator 118 can be provided in the separation between the planar terminals. The insulator provides electric insulation across the entire width of the conductive sheets that form the respective planar terminals. In some implementations insulating paper is used.
That is, the above describes an example of a semiconductor device 100 that includes a housing 114, a substrate 104 inside the housing, semiconductor circuits 106A-B on the substrate, and planar terminals 102A-B that extend away from the housing and are electrically connected to the first and second semiconductor circuits, respectively. In particular, the planar terminals are stacked on top of each other.
As a result, the inductance is now proportional to the area between the planar terminals 102A-B plus the area between the terminal 102B and the substrate 104 where the negative terminal overlaps the positive one. This can allow for a significant reduction of inductance compared to traditional device designs. For example, because the planar terminals abut the silicon dies and also extend outside the housing, the busbar structure can be considered (at least partially) integrated within the housing. Some of the present implementations can avoid attaching IGBT leads to an external busbar layer and thereby eliminate the need to form holes in such busbar layer, which could otherwise increase the inductance.
Here, the planar terminal 302A abuts the busbar 304A outside the housing. Also, the planar terminal 302B abuts the busbar 304B, at least the part thereof that is exposed through the opening 310. For example, the planar terminal and the busbar can be welded together. In some implementations, this approach can lead to a simplified manufacturing process in that the planar terminals—which can be sheets wide enough to span several IGBTs—can easily be aligned with and attached to the busbars of the device(s). In some implementations, both of the busbars can be exposed through holes in a similar way as shown for the busbar 304B.
Similar to the previous example, the planar terminal 302B can have an offsetting portion that provides a contact portion—parallel with and offset from the main portion of the planar terminal—so as to reach at least a portion of its busbar.
Electric insulation 312 can be provided in the separation between the planar terminals 302A-B. In some implementations, the stacked structure of these planar terminals (with insulation) can be assembled in advance and then this assembly can be brought to the rest of the semiconductor device for making the electrical connections. As such, the current example can be considered as having the stacking done outside the semiconductor package instead of inside it which can simplify the manufacture.
Here, a set of six semiconductor devices 402 are shown but in other implementations more or fewer can be used. The semiconductor housings are here omitted for clarity. The semiconductor devices are arranged next to each other in a row. Each device has a substrate 406 and busbars 408A-B. The busbars are connected to respective semiconductor circuits on the substrates (e.g., silicon dies) which are not visible in this illustration. In particular, the silicon dies would be positioned between the respective busbars 408A-B and the substrate 406.
Planar terminals 410A-B are here comprised of conductive sheets that connect the capacitors 404 to each of the semiconductor devices via the busbars. The planar terminals are stacked on top of each other so that the planar terminal 410A abuts the busbar 408A and the planar terminal 410B abuts the busbar 408B. At the other end of the planar terminals, they connect to respective conductors of the capacitors. That is, each planar terminal connects multiple semiconductor devices to each of the several capacitors.
One or more of the planar terminals 410A-B can have a step shape when viewed in profile. Here, the planar terminals are essentially flat planes in the area near the semiconductor devices. To accommodate the relative position of the capacitors and the semiconductor devices, the planar terminal 410B (the “lower” of the terminals in this example) makes turns 412A-B so as to provide a contact plane 414B for (in this example) the bottom conductor of the capacitor. The planar terminal 410A can make corresponding turns to form a contact plane 414A for the opposite capacitor conductor.
The planar terminals provide a continuous conductive plane for current traveling to and from the capacitors. That is, because there are no holes in these sheets or pins at their edge where they electrically connect to the semiconductor devices, there are fewer or no “necks” that impede the flow of current.
The assembly 400 can form part of a power inverter. In some implementations, the inverter can include two (or more) of the assembly 400 where the semiconductor devices (e.g., IGBTs) are jointly controlled so as to perform the DC-to-AC conversion. For example, two such assemblies can be oriented so that their respective semiconductor devices are near each other, which can simplify the placement and operation of cooling systems (e.g., liquid-based heatsinks).
An example of assembling an apparatus will now be described. This description will refer to some examples of components mentioned above for illustrative purposes. However, other components can be used instead of or in addition to these.
Semiconductor devices (e.g., 402) are positioned in a row. Each of the semiconductor devices comprises a substrate (e.g., 406), first and second semiconductor circuits (e.g., 106A-B) on the substrate, and first and second busbars (e.g., 408A-B) abutting the first and second semiconductor circuits, respectively.
An assembly is formed by placing a first planar terminal (e.g., 410A) in contact with the first busbar (e.g., 408A) of each of the plurality of semiconductor devices, and a second planar terminal (e.g., 410B) in contact with the second busbar (e.g., 408B) of each of the plurality of semiconductor devices. The first and second planar terminals are stacked on top of each other. For example, the terminals can first be stacked and then (as an assembled stack) be placed in contact with the respective busbars.
The first planar terminal is welded to the first busbar of each of the plurality of semiconductor devices. Such welding can be performed from one side of the assembly. A weld 416A from above the assembly is here schematically illustrated. Similarly, the second planar terminal is welded to the second busbar of each of the plurality of semiconductor devices. Such welding can be performed from the opposite side of the assembly. A weld 416B from below the assembly is here schematically illustrated. For example, laser welding can be used.
An electrical insulation layer (e.g., 118) can be included between the first and second planar terminals. For example, an insulating paper can be inserted before the terminals are stacked on top of each other.
Each of the first and second planar terminals can be electrically connected to a plurality of capacitors (e.g., 404). For example, respective contact planes of the terminals can be connected (e.g., welded) to respective capacitor terminals.
More or fewer steps can be performed in some assembly processes. Also, two or more steps can be performed in a different order.
Each device has a substrate 618 on which a corresponding silicon die 620 is positioned. The substrate and/or the die can be similar or identical to those described elsewhere herein. In some implementations that have a co-pack design, the die 620 can include both one or more switching devices (e.g., an IGBT) and one or more other semiconductor devices (e.g., a diode). For example, the assembly 600—which includes the two devices 602 and 604—can then be used in one of the half bridges in a power inverter.
The busbars 612 and 616 are here positioned on top of the corresponding silicon die and are electrically connected to it. The other busbars 610 and 614 are also electrically connected, for example by one or more wire bonds (not shown) to the die. The busbars for the individual device (e.g., busbars 610 and 612) can be configured so that they facilitate good performance characteristics (e.g., reduced inductance) and a simplified assembly process. These busbars can be positioned in opposite directions from the silicon die. In some implementations, one of the planar busbars can extend in a plane that is parallel to and offset from the plane of the other busbar. For example, here the busbar 612 sits higher above the substrate than the busbar 610 so that there is an offset between them. In other implementations, the busbars can be located in a common plane.
The devices 602 and 604 are enclosed in respective housings 622 and 624. One advantage of a co-pack design can be that the individual die within its housing is easy to handle and install. For example, the busbar geometries of the respective individual devices can facilitate direct connection between the devices, and with other components such as terminals.
The planar busbars can extend from the respective housing in essentially opposing directions. Here, for example, the busbar 610 has an opening 626 that allows connection with the terminal 608. The busbar 612 has an opening 628 that allows connection with the busbar 614 from the device 604. The attachment between the busbar 616 and the terminal 606 can be facilitated by a contact portion 630 that is offset from a main part of the terminal 606 by an offsetting portion 632. For example, this can facilitate a close spacing (here in a vertical direction) between the terminal 606 and the busbar 616, which can help avoid significant inductance.
The assembly 600 can be used in any or all contexts described above. Some examples will be provided. With reference again to
The assembly 600 can be assembled using any or all approaches described above. First, in some implementations, the busbars 612 and 614 are attached to each other before the terminals (e.g., 606, 608) are put in place. Any suitable joining technique can be used, including, but not limited to, laser welding, ultrasonic welding, sintering or soldering.
Second, the planar terminals 606 and 608 can be attached to the respective devices 602 and 604 in analogy with examples described herein. With reference to
That is, the above exemplifies a manufacturing process where a first semiconductor device can be positioned near a second semiconductor device, the first semiconductor device having first and second planar busbars parallel to each other and extending in opposite directions through respective openings in a first housing. The second semiconductor device can have third and fourth planar busbars parallel to each other and extending in opposite directions through respective openings in a second housing. The second planar busbar of the first semiconductor device can be attached to the third planar busbar of the second semiconductor device. A first planar terminal can be positioned adjacent the first planar busbar of the first semiconductor device, and a second planar terminal can be positioned adjacent the fourth planar busbar of the second semiconductor device. The first planar terminal can be attached to the first planar busbar, and the second planar terminal can be attached to the fourth planar busbar.
A number of implementations have been described as examples. Nevertheless, other implementations are covered by the following claims.
The present U.S. Utility Patent Application claims priority pursuant to 35 U.S.C. §119(e) to U.S. Provisional Application No. 62/233,178, entitled “SEMICONDUCTOR DEVICE WITH STACKED TERMINALS”, filed Sep. 25, 2015, which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 62233178 | Sep 2015 | US |
