The present application claims priority to International Patent Application No. PCT/IB2014/002946, entitled “SEMICONDUCTOR DEVICE AND METHOD FO MANUFACTURE THEREFOR,” filed on Dec. 8, 2014, the entirety of which is herein incorporated by reference.
This invention relates to a semiconductor device and a method of manufacture therefor.
Standard power transistors have a low blocking voltage in one direction, making them unidirectional devices. Consequently, if a bi-directional switch is required it is typically implemented using two separate serially coupled power MOSFETs in back to back configuration. The separate MOSFETs are formed on separate semiconductor dice, and often housed in separate packages, which results in a high manufacturing cost and a large area occupied on a circuit board. This may be problematic in, for example, a H-bridge arrangement where multiple power transistors are used.
The present invention provides a semiconductor product and methods as described in the accompanying claims.
Specific embodiments of the invention are set forth in the dependent claims.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Because the illustrated examples may for the most part, be implemented using techniques, processes and components known to those skilled in the art, details will not be explained in any greater extent than that considered necessary for the understanding and appreciation of the underlying concepts of the examples set forth herein and in order not to obfuscate or distract from the teachings herein.
The common interconnecting semiconductor electrode 2 allows a single compact semiconductor product 10 that integrates both the first switch 21 and the second switch 22 into a single semiconductor assembly.
As is known to the person skilled in the art, a potential difference may be applied between nodes N1 and N2. The switches S1, S2, S3, 34 are switched on or off to control current flow between the node M1 and node M2. For example if both FETs T1 and T4 are on and both FETs T2 and T3 are off then an electric current may flow from node M1 to node M2. For example if both FETs T2 and T3 are on and both FETs T1 and T4 are off then an electric current may flow from node M2 to node M1
Thus if a particular potential difference is applied between node N1 and node N2, the direction of the electric current between the node M1 and node M2 may be controlled by controlling whether the FETs T1, T2, T3, T4 are on or off.
Referring to
Referring to
Referring to
Referring to
The vertical insulated-gate field-effect-transistor 100 comprises a first current electrode 120 which forms the first semiconductor electrode 11 and a second current electrode 124 which forms the second semiconductor electrode 12. In the following description, the first current electrode 120 will be referred to as first semiconductor electrode 120 and the second current electrode 124 will be referred to as the second semiconductor electrode 124 to maintain continuity.
The first semiconductor electrode 120 is connected via a first semiconductor drift region 121 to a semiconductor body 122. The second semiconductor electrode 124 is connected via a second semiconductor drift region 123 to the semiconductor body 122. The first semiconductor electrode 120, first semiconductor drift region 121, semiconductor body 122, second semiconductor drift region 123 and second semiconductor electrode 124 are stacked such that access to the first semiconductor electrode 120 and the second semiconductor electrode 124 is from different and opposing sides of the semiconductor product 10.
The first semiconductor electrode 120 and the first semiconductor drift region 121 have a first conductivity type. The second semiconductor electrode 124 and the second semiconductor drift region 123 have a first conductivity type. The body 122 has a second conductivity type different to the first conductivity type.
The discontinuity in Fermi Energy levels between the first semiconductor drift region 121 and the body 122 creates a first junction diode 50. The discontinuity in Fermi Energy levels between the second semiconductor drift region 123 and the body 122 creates a second junction diode 52.
In the example shown the first semiconductor drift region 121 is n-type and the body 122 is p-type and the first junction diode 50 enables current flow from body 122 to the first semiconductor drift region 121 and prevents current flow to the body 122 from the first semiconductor drift region 121. The second semiconductor drift region 123 is n-type and the second junction diode 52 enables current flow from body 122 to the second semiconductor drift region 123 and prevents current flow to the body 122 from the second semiconductor drift region 123.
A vertically extending gate electrode 111 is adjacent the body 122 and separated from the body 122 by an insulator 114.
Application of a gate voltage above a threshold voltage disables one or both of the first diode 50 and second diode 52 allowing current flow.
If the body 122 and the first semiconductor drift region 121 are held at the same potential the first diode 50 is not disabled by the gate potential. In this case, the gate can enable current flow from the second drift region 123 to the body 122 while the first diode can prevent current flow from the first drift region 121 to the body 122, as shown in
If the body 122 and the second semiconductor drift region 123 are held at the same potential the second diode 52 is not disabled by the gate potential. In this case, the gate can enable current flow from the first drift region 121 to the body 122 while the second diode can prevent current flow from the second drift region 123 to the body 122, as shown in
In
It will be appreciated that although
In
It will be appreciated that although
It will be appreciated from
The nodes N1, N2, M1, M2 may be accessible because they are at a surface of the semiconductor product 10 or because conductive interconnects, galvanically connected to the respective nodes, are at an exterior of the semiconductor product 10.
Referring to
The vertical insulated-gate field-effect-transistors described in the preceding paragraphs may be bidirectional power metal-oxide-semiconductor field-effect-transistors as described below.
The semiconductor product 10 may be manufactured by: providing, using doped semiconductor, an interconnecting semiconductor electrode; providing, using doped semiconductor, a first vertical insulated-gate field-effect-transistor 21 (T2/T1) that has an interconnecting semiconductor electrode 13 (N2/M1) as a first current electrode (drain/source) and a second vertical insulated-gate field-effect-transistor 22 (T4/T2) that has the interconnecting semiconductor electrode 13 (N2/M1) as a first current electrode (drain/source), the interconnecting electrode 13 (N2/M1) interconnecting the first vertical insulated gate field-effect-transistor 21 (T2/T1) and the second vertical insulated gate field-effect-transistor 22 (T4/T2); and providing, using doped semiconductor, a first semiconductor electrode 11 (M1/N1) and a second semiconductor electrode 12 (M2/N2), wherein the first semiconductor electrode 11 (M1/N1) forms a second current electrode (source/drain) of the first vertical insulated-gate field-effect-transistor 21 (T2/T1) and the second semiconductor electrode 12 (M2/N2) forms a second current electrode (source/drain) of the second vertical insulated-gate field-effect-transistor 22 (T4/T2).
The method may further comprise: providing, using doped semiconductor, a second interconnecting semiconductor electrode (N1/M2) defining a semiconductor electrode (drain/source); providing, using doped semiconductor, a third vertical insulated-gate field-effect-transistor (T3/T4) that has the second interconnecting semiconductor electrode (N1/M2) as a first current electrode (drain/source) and a fourth vertical insulated-gate field-effect-transistor (T1/T3) that has the second interconnecting semiconductor electrode (N1/M2) as a first current electrode (drain/source), the second interconnecting electrode (N1/M2) interconnecting the third vertical insulated gate field-effect-transistor (T3/T4) and the fourth vertical insulated gate field-effect-transistor (T1/T3); wherein providing, using doped semiconductor, the first semiconductor electrode (M1/N1) forms a second current electrode (source/drain) of the fourth vertical insulated-gate field-effect-transistor (T1/T3) and a second current electrode (source/drain) of the first vertical insulated-gate field-effect-transistor (T2/T1) and wherein providing, using doped semiconductor, the second semiconductor electrode (M2/N2) forms a second current electrode (source/drain) of the third vertical insulated-gate field-effect-transistor (T3/T4) and a second current electrode (source/drain) of the second vertical insulated-gate field-effect-transistor (T4/T2).
An FET 100 of this type is suitable for use as the first vertical insulated-gate field-effect-transistor 31. A FET 100 of this type is suitable for use as the second vertical insulated-gate field-effect-transistor 31. A FET 100 of this type is suitable for use as any of FETs T1, T2, T3, T4.
A first drift region 121 extends, in the vertical direction, between the body 122 and the first semiconductor electrode 120. A second drift region 123 extends, in the vertical direction, between the body 122 and the second semiconductor electrode 124.
The first drift region 121 and the second drift region 123 may be implemented in any manner suitable for the specific implementation. The first and second drift region can be of a first conductivity type having a first type of majority charge carriers, while the body is of a second conductivity type having a second type of majority charge carriers opposite to the first type. For example the drift regions may be n-type semiconductors and the body 122 may be a p-type semiconductor. The first semiconductor electrode 120 and the second semiconductor electrode 124 may be implemented in any manner suitable for the specific implementation. The first and second semiconductor electrodes can be of a first conductivity type, having a first type of majority charge carriers but with a higher dopant concentration than the respective first and second drift regions 121, 123.
An electrical path extends vertically between the first semiconductor electrode 120 and the second semiconductor electrode 124. The electrical path can be selectively enabled or disabled to allow current to flow in a first direction, e.g. from the first semiconductor electrode 120 to the second semiconductor electrode 124 or a second direction, opposite to the first direction. The electrical path comprises the first drift region 121, the body 122 and the second drift region 123.
One or more vertical trenches 110 extend vertically adjacent the body and comprise a gate electrode 111 that is separated from the body by a gate dielectric 114. The gate electrode 111 is used to selectively enable or disable the electrical path.
In the shown example a first vertical trench 110 and a second vertical trench 110 extend in the vertical direction from an upper portion adjacent the first semiconductor electrode 124, past and adjacent to the second drift region 123, past and adjacent to the body 122 and past and adjacent to the first drift region 121 and partially into the first semiconductor electrode 120. Hereinafter, the vertical sidewalls of the trench 110 closest to, and facing towards, the body 122 are referred to as the inner sidewalls 115 and the vertical sidewalls facing away from the body 122 are referred to as the outer sidewalls. The body 122, first drift region 121 and the second drift region 123 extend laterally between the first and second vertical trench 110.
In the shown example, each of the first and second vertical trench 110 comprises a gate electrode 111 in a first part of the vertical trench 110. The gate electrode 111 is electrically isolated from the body 122 by a gate dielectric, in this example formed by a gate dielectric layer 114 lining the inner sidewall in the first part of the trench. The gate electrode 111 is coupled, via capacitive coupling, to the body 122 and, when a suitable voltage is applied to the gate electrode a vertical channel is formed in the body 122. Through the vertical channel a current can flow from the first drift region 121 to the second drift region 122, when the first semiconductor electrode 120 is at a positive voltage with respect to the second semiconductor electrode 124, or vice versa when the second semiconductor electrode 124 is at a positive voltage with respect to the first semiconductor electrode 120.
The bi-directional trench field effect power transistor 100 is a layered device comprising a substrate 101, layer stack 102 and a passivation layer 103. The first semiconductor electrode 120, is present at the backside of the substrate 101, and extends over the bottom surface of the substrate 101.
The vertical trench 110 may be implemented in any manner suitable for the specific implementation. The first and second vertical trench 110 are very deep trenches which extend in the shown example from the top of the layer stack 102 into the substrate 101. However the vertical trenches may be less deep, and for example extend until the substrate 101 top surface, i.e. the bottom of the trench touching the substrate top surface 1010. Likewise, the vertical trenches 110 may terminate slightly above the substrate 101, for example at a vertical position closer to the substrate top surface 1010 than to the middle of the first drift layer 121.
The bi-directional trench field effect power transistor 100 may additionally comprise a body electrode connected to the body 122. Alternatively, the body electrode may be absent and the body 122 may be a fully floating body.
Each of the electrodes present in the semiconductor product is connectable to an external power supply, not shown. The connection between the electrodes and the external power supply may be provided in any conventional manner, and is not described in further detail.
Drift Regions
The first drift region 121 extends in lateral direction between the vertical trenches and is defined by the inner sidewalls of the vertical trenches. The first drift region 121 extends in vertical direction from the top-surface of the first semiconductor electrode 120 until the bottom of the body 122. Suitable lower limits for the thickness have been found to 2 micron or more, such as 5 micron or more, for example 10 micron or more, and suitable upper limits 10 micron or less, such as 5 micron or less, such as 2 micron or less. The first drift region 121 may for example be mono-crystalline, and grown on the substrate through for instance an epitaxial process. The first drift region may be of the same material, e.g. Si, as the first semiconductor electrode 120 but with a lower doping concentration. A suitable dopant has been found to be P or As with a resistivity of 0.2 Ohm*cm or more, e.g. 0.5 Ohm*cm or more, such as 0.8 Ohm*cm or more. A suitable upper limit has been found a resistivity of 1 Ohm*cm or less. A particularly effective resistivity has been found to be 0.4 Ohm*cm on average. The resistivity may vary in the first drift region 121, for example as a function of depth, in a manner suitable to increase the breakdown voltage of the power transistor. The first drift region 121 may for example be provided with a linearly graded doping to obtain a suitable resistivity variation.
The second drift region 123 may, as in the examples, have essentially the same characteristics as the first drift region 121. In the example, the thickness of the second drift region 123 is much less than of the first drift region 121. A suitable thickness has found to be 1 micron or more, for example 1.5 micron.
Semiconductor Electrodes
The first semiconductor electrode 120 and second semiconductor electrode 124 may be implemented in any manner suitable for the specific implementation. In the shown examples, the first and second semiconductor electrode 120, 124 are of the same, first, conductivity type as the drift regions 121,123 and opposite to the conductivity type of the body 122. The concentration of majority charge carriers in the first semiconductor electrode 120 is higher than in the first drift region 121. The concentration of majority charge carriers in the second semiconductor electrode 124 is higher than in the second drift region 123. The semiconductor electrodes 120, 124 may for example be doped or otherwise be provided with a resistivity which is at least one order of magnitude smaller than the resistivity of the drift regions 121, 123.
The first semiconductor electrode 120 is formed by the substrate 101. On the bottom of the substrate 101, also referred to as the back-side, a metal layer 129 is provided which constitutes the electrode for the first semiconductor electrode 120 and allows to connect the first semiconductor electrode 120 to an external voltage or current supply. In this example, the substrate 101 is of a semiconductor material provided with a dopant of the same type as the first drift region 121 (e.g. an n-type doping or a p-type doping) to make the first semiconductor electrode 120 highly conductive compared to the first drift region 121. For instance, the doping concentration may be at least 2.5 orders of magnitude higher than in the drift region 121, 3 orders or more have been found to be particularly effective. The substrate 101 may be any suitable type of substrate such as a mono-crystalline Si substrate with a <100> orientation, and doped with a suitable dopant, such as in case of an N-doped semiconductor electrode Arsenic (As), to obtain a resistivity of less than 1 mOhm*cm, such as less than 0.005 Ohm*cm, for example 0.03 Ohm*cm or less.
The second semiconductor electrode 124 may be implemented in any manner suitable for the specific implementation, and be of similar constitution as the first semiconductor electrode 120, but in terms of conductivity and doping concentration different, for example with a doping concentration which is an order of magnitude higher.
Body
The body 122 may be implemented in any manner suitable for the specific implementation. In the shown example, the body is defined in lateral direction by the inner sidewalls of the vertical trenches 110 and in vertical direction between by the bottom of the second drift region 123, and the top of the first drift region 121. The body 122 may for example be formed by doping a semiconductor material, e.g. Si, with a suitable dopant. A suitable dopant has been found Boron, such as B11. A suitable concentration has been found to be 2 orders of magnitude smaller than that of the first semiconductor electrode 120.
Layer Stack
The layer stack may be implemented in any manner suitable for the specific implementation. In the shown example, the layers stack 102 comprises a bulk layer of a base material of the first conductivity type with a concentration of majority charge carriers equal to a concentration in the first drift region 121 or in the second drift region 123. The bulk layer is provided with one or more doped layers in which a doping is different than in the base material. The doped layer having a second conductivity type and/or a concentration of majority charge carriers higher than the base material. Thus, in the example shown, the layers of the layer stack 102 are formed from the same base material. However, alternatively the layer stack may comprise a plurality of different layers of different base materials, for example individually grown on top of each other during consecutive phases of manufacturing of the power transistor.
The doped layers in the bulk layer may for example comprise one or more of the group consisting of: a buried layer of the second conductivity type, in which the body 122 is present; a source layer of the first conductivity type with a concentration of majority charge carriers higher than the base material, in which the second semiconductor electrode 124 is present, the source layer is separated from the buried layer 122 by a drift layer of the base material which the second drift region 123 is present; a drain layer of the first conductivity type with a concentration of majority charge carriers higher than the base material, in which the first semiconductor electrode 120 is present, the drain layer is separated from the buried layer by a drift layer of the base material in which the first drift region 121 is present.
Isolation
The arrangement may, as in the example, be provided with an enclosure which isolates or protects the arrangement. For instance, the arrangement shown is enclosed by, a well 108 of a conductivity type opposite to that of the first semiconductor electrode 120, which in turn is enclosed by a shallow trench isolation, STI, 109 at the top of the layer stack 102. The well 108 extends in lateral direction partly under the STI 109 and is in direct contact with the STI. The well 108 extends in vertical direction from the top of the layer stack 102 towards the substrate 101 in the layer 102. In this example the layer 102 has the same concentration of majority charge carriers as the first drift region 121 and is a doped semiconductor layer with the same doping concentration as the first drift region 121.
Characteristics
The bi-directional trench field effect power transistor 100 shown can support high energies, i.e. high currents and/or voltages. The power transistor 100 may for example have a current maximum of more than 1 A, such as 10 A or more, such as 100 A or more, such as at least 200 A and/or a positive drain-source break down voltage of at least 25 V, for example 50 V or more, and a negative drain-source break down voltage of at least 25 V, for example 30 V or more, such as 50 V or more, for example 100 V or more, e.g. 300 V or more. The bi-directional trench field effect power transistor 100 may be symmetric with positive and negative break down voltages that have the same absolute value, or be asymmetric, with different values, depending on the specific implementation. For an asymmetric transistor, a suitable positive breakdown voltage has found to be between 1.5 and 2 times that of the negative breakdown voltage, such as 45 V for a 25 V negative breakdown voltage. For instance, depending on the specific implementation the thickness of the first and/or second drift region may be adapted to obtain a breakdown voltage for the specific implementation.
Shield Plate
In the example shown, but not necessarily all examples, each of the first and second vertical trench 110 comprises a lower shield plate 112. The lower shield plate 112 is in this example additional to the lateral isolation of the first drift region 121 by the vertical trench 110. However, it should be apparent that the lower shield plate 112 may be used without the lateral isolation of the first drift region 121, and that the lateral isolation of the first drift region may be used without a shield plate 112. The shield plate 112 is situated in a lower part of the trench 110. This lower part is closer to the substrate 101 than the part occupied by the gate electrode 111.
The shield plate 112 is capable of generating a vertical accumulation layer in the first drift region 121, e.g. along the inner sidewall of the trench, when the lower shield plate 112 is biased with respect to the first semiconductor electrode 120 in a first polarity. For example, in case the first semiconductor electrode 120 is an n-doped semiconductor material, the accumulation layer can be generated when the lower shield plate 112 is sufficiently positively biased. In case the first semiconductor electrode 120 is a p-doped semiconductor material, the accumulation layer can be generated when the lower shield plate 112 is sufficiently negatively biased. In the shown examples the accumulation layer will extend in a vertical direction through the whole first drift region 121, from the bottom limit of the body 122 to the first semiconductor electrode 120. Thus, a conductive path between the body 122 and the first semiconductor electrode 120 may be established in a relatively fast manner. However, depending on the specific implementation, the accumulation layer may extend in a vertical direction through a part of the first drift region 121 only, and e.g. be spaced from the body or the first semiconductor electrode 120.
The shield plate 112 can further locally reduce the electrical field density in parts of the first drift region 121 when the lower shield plate 112 is biased with respect to the first semiconductor electrode 120 in a second polarity. For example, in case the first semiconductor electrode is an n-doped semiconductor material, the reduction is obtained when the lower shield plate 112 is sufficiently negatively biased. For example, in case the first semiconductor electrode 120 is an n-doped semiconductor material, the reduction is obtained when the lower shield plate 112 is sufficiently negatively biased. Thus, unexpected breakdown may be reduced because overly high electric fields in the first drift region 121 may be avoided while the speed of switching may be improved since the current path through the drift region 121 can be enabled more rapidly by creating the accumulation layer.
Upper Shield Plate
In some but not necessarily all examples, the vertical trenches 110 may be provided, in addition to the gate electrode 11 and the lower shield plate 112, with other elements of the power transistor 100. For instance, each vertical trench 110 may further comprise an upper shield plate 125. The upper shield plate 125 may be controlled in a similar manner as the lower shield plate 112 and be arranged to generate an accumulation layer in the second drift region 123 when the upper shield plate 125 is biased with respect to the second semiconductor electrode 124 in the first polarity and reducing, at least locally, the electrical field density when the upper shield plate 125 is biased with respect to the second semiconductor electrode 124 in the second polarity. There, unexpected breakdown may be reduced because overly high electric fields in the second drift region 123 may be avoided while the speed of switching may be improved since the current path through the second drift region 123 can be enabled more rapidly by creating the accumulation layer. As shown, the upper shield plate 125 may have a similar shape as the lower shield plate 112 and be separated from the second drift region 123 by a suitable dielectric.
Trench Enclosure
In this example, the terms first vertical trench and second vertical trench are used for convenience to denote the trench part at opposite sides of the electrical path, however, they may both be parts a single elongated vertical trench enclosure which, in a plane parallel to the substrate top-surface, encloses the electrical path.
The elongated vertical trench enclosure comprises an elongated enclosing gate electrode which comprises the gate electrodes 114 of the vertical trenches 110 and an elongated enclosing lower shield plate which comprises the lower shield plates 112 of the vertical trenches, the enclosing gate electrode enclosing the body 122 and the enclosing lower shield plate enclosing the first drift region 121. It will be apparent that the enclosing shield plate may be absent when the transistor is implemented without shield plate(s).
Trenches-Dielectric
Also, the vertical trenches 110 may be filled, e.g. with the electrodes 111,112 and dielectrics 113,114 in any suitable manner. In the shown example, for instance the vertical trenches extend into the substrate 101 and the shield plate 112 terminates above the substrate 101. The shield plate 112 is isolated from the substrate 101 by a thick dielectric at the bottom of the trench 110. Thereby, the substrate 101 operation can be effectively decoupled from the voltage of the shield plate 112.
Furthermore, at least the inner sidewall 115 of the vertical trenches 110, and in this example both the inner and outer sidewall, may be covered with a dielectric which separates respectively the gate electrode 111 and the shield plate 112 from the sidewall. Hereinafter the dielectric in the first part is referred to as the gate dielectric 114 and the dielectric in the lower part is referred to as the shield dielectric 113. As shown, the dielectric is along the surface of the sidewall in contact with respectively the body 122 and the drift regions 121,123. The dielectric is thinner in the first part than in the lower part. Thus, the gate electrode 111 is sufficiently coupled in order to generate the channel whereas the shield plate 112 is less coupled to the drift region 121, to enable creating the accumulation layer and the reduction of the electrical field density. In the shown example the gate dielectrics 114 and the shield dielectrics 113 are of the same material, e.g. silicon oxide. However, depending on the specific implementation, the dielectrics may be of different materials. Although the dielectrics 113,114 are shown as a single vertical dielectric layer, it will be apparent that the dielectric may comprise a stack of two or more vertical layers. Furthermore, the gate electrode 111, and if present shield plate(s) 112, filling parts of the vertical trench 110 may be implemented in any manner suitable for the specific implementation and have any suitable shape, size and configuration. The dielectric thickness may be varied throughout the trench 110.
Operation
The power transistor 100 may be used to control the flow of current. The shown example of power transistor 100 may for example be used in a method for operating a power transistor as described below, although it will be apparent that other types of bi-directional power transistors may be used as well to perform such a method. The power transistor can be operated intermittently in a first direction or a second direction, i.e. bi-directional. The bi-directional nature of the power transistor 100 will now be described in operation, using the example of a n-type power transistor.
In a first direction and in respect of switching the power transistor 100 on, a positive voltage may be applied to the first semiconductor electrode 120 (drain). The body 122 may be connected to the second semiconductor electrode 124 (source), so as to electrically couple the body 122 to the source. To the shield plate 112 a positive bias voltage sufficient to generate an accumulation layer in the first drift region may then be provided. A positive gate bias voltage, Vgs>0V, may be applied on the gate electrode 111 causing a depletion field effect through the gate dielectric 114 into a region of the body 122 that contacts the first and second trenches 110. When the gate bias voltage exceeds a threshold voltage Vth, an inversion conducting n-layer may be formed along the interface of the trench 110 and the body 122, which conducts the majority of n-type carriers injected from the source 124 to be collected by the drain 120.
In an off-state, a positive voltage may be applied to the drain 120. The body 122 may still be electrically tied to the source 124 and so be subjected to a source potential. The gate bias voltage may be set to a lowest potential, namely Vgs=0V. A first depletion layer may be formed around a bottom p-n junction formed by the interface of the body 122 and the first drift region 121. By increasing the drain-source bias voltage, Vds, a first space charge region of the depletion layer may increase to the low-doped bottom part of the first drift region 121. The electrical field in the region thereby increases and when a breakdown voltage is reached, an avalanche phenomena by carrier impact ionization may be observed causing breakdown of the reverse biased junction mentioned above. A negative bias voltage may be provided to the shield plate. This reduces the electrical field density in at least a part of the first drift region 121, and accordingly the breakdown voltage can be increased.
In the second direction and in relation to an on-state, the drain 120 is coupled to the body 122. A positive voltage may be applied to the source 124. The positive gate bias voltage, Vgs>0V, may be applied to the gate 111, thereby causing a depletion field effect through the gate dielectric 114 into the body 122 along the inner sidewalls of the trenches 110. When the gate bias voltage exceeds the threshold voltage Vth an inversion conducting layer may be formed along the interface of the trench dielectric and the body 122, which may conduct the majority of the carriers injected from the drain 120 and collected by the source 124.
In an off state, a positive voltage may be applied to the source 124. The body 122 may still be electrically tied to the potential of the drain 120. The gate bias voltage, Vgs, may be set to the lowest potential, namely, Vgs=0V. A second depletion layer may be formed around a top p-n junction formed by the interface of the body 122 and the second drift region 123. By increasing the drain-source bias voltage, Vds, a second space charge region of the depletion layer may increase to the low-doped top part of second drift region 123. The electrical field in the region may thereby increase and when a breakdown voltage is reached, an avalanche phenomena by carrier impact ionization may be observed causing breakdown of the reverse biased junction mentioned above, thereby implementing the blocking voltage.
Manufacture
The power transistor 100 may be manufactured in any manner suitable for the specific implementation.
Referring to
On the top surface 1010 of the substrate 101, a layer stack may be manufactured in any suitable manner. For example, a bulk layer 201 may be provided, e.g. by epitaxial growth, extending over the top-surface 1010 and directly adjacent thereto. The bulk layer 201 may be monolithic, and for example of the same material as the substrate, i.e. <100> Si.
However the bulk layer or substrate may alternatively be of a different material, such as SiC or GaN. The substrate may be a single material, e.g. Si, or be an engineered substrate consisting of multiple, initially unpatterned layers layered one on top of the other.
In the shown example the bulk layer 201 has about the thickness of the layer stack 102, e.g. 5 micron, and subsequently several layers are created by modifying the characteristics of the bulk layer at different depth, e.g. through suitable doping implant and activation. However, alternatively the bulk layer may be thinner than the layer stack and serve as a bottom layer thereof, with the additional layers of the layer stack being created by growth on the bulk layer, e.g. of an oppositely doped epitaxial layer for the body 122, and on top of the oppositely doped epitaxial layer another epitaxial layer for the second drift region 123.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
After that, a blanket dielectric layer 207 may be deposited which covers the exposed lateral surface of the layer stack and fills the trenches up to the re-oxidized top surface 206, see
A suitable material for the intermediate dielectric has been found to be TEOS. For instance, a TEOS layer may be deposited as blanket dielectric layer 207, e.g. in this example on the pad nitride layer 202. The TEOS layer may then be planarized, e.g. through CMP or otherwise, down to the pad nitride layer 202. The TEOS layer may then be etched in the trenches 110 until the desired depth.
Referring to
Referring to
Referring to
Referring to
Referring to
In this example, the body 122 is formed by implanting a dopant layer 212 at a convenient depth and subsequent activation of the dopant. For example, in case of a n-type transistor, implantation and activation of a p-type dopant, e.g. Boron, such as B11, may be performed. For instance, a dose of 2·1013 at/cm3 implanted with 700 kEV energies may be provided and activated by a furnace anneal.
As shown in
Referring to
Referring to
In the foregoing description, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the scope of the invention as set forth in the appended claims, and that the claims are not limited to the specific examples given in the foregoing description. Of course, the above advantages are examples, and these or other advantages may be achieved by the examples set forth herein. Further, the skilled person will appreciate that not all advantages stated above are necessarily achieved by embodiments described herein.
For example, the semiconductor substrate described herein can be any suitable semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
Likewise, the semiconductor substrate described herein is a mono-layer but the semiconductor substrate may also be an, unpatterned, engineered substrate consisting of several layers of different materials.
Also, some of the figures are discussed in the context of a device with a n-type transistor. However, embodiments according to the present invention are not so limited. That is, the features described herein can be utilized in a p-type transistor. The discussion of an n-channel device can be readily mapped to a p-channel device by substituting p-type dopant and materials for corresponding n-type dopant and materials, and vice versa. Likewise, although specific dopants (As, B, P) have been mentioned, it should be apparent that other dopants may be suitable as well.
Furthermore, although in the examples shown, the layer stack is formed from Si, other materials may be suitable as well.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing absolute positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Other modifications, variations and alternatives to the examples set forth herein are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
Number | Date | Country | Kind |
---|---|---|---|
PCT/IB2014/002946 | Dec 2014 | WO | international |
Number | Name | Date | Kind |
---|---|---|---|
5420451 | Williams et al. | May 1995 | A |
5488862 | Neukermans et al. | Feb 1996 | A |
5682050 | Williams | Oct 1997 | A |
5767733 | Grugett | Jun 1998 | A |
5770883 | Mizuno et al. | Jun 1998 | A |
5850042 | Warren | Dec 1998 | A |
5914801 | Dhuler et al. | Jun 1999 | A |
5945708 | Tihanyi | Aug 1999 | A |
6043965 | Hazelton et al. | Mar 2000 | A |
6049108 | Williams et al. | Apr 2000 | A |
6096608 | Williams | Aug 2000 | A |
6215137 | Suzuki et al. | Apr 2001 | B1 |
6433401 | Clark et al. | Aug 2002 | B1 |
6650520 | He | Nov 2003 | B2 |
6781195 | Wu et al. | Aug 2004 | B2 |
6943408 | Wu et al. | Sep 2005 | B2 |
7019231 | Ishikawa et al. | Mar 2006 | B2 |
7280014 | Potter | Oct 2007 | B2 |
7282406 | Grivna et al. | Oct 2007 | B2 |
7283343 | Grose et al. | Oct 2007 | B2 |
7297603 | Robb et al. | Nov 2007 | B2 |
7352036 | Grebs et al. | Apr 2008 | B2 |
7508277 | Kuo et al. | Mar 2009 | B2 |
7537970 | Robb et al. | May 2009 | B2 |
7605435 | Anderson et al. | Oct 2009 | B2 |
7807536 | Sreekantham et al. | Oct 2010 | B2 |
7910409 | Robb et al. | Mar 2011 | B2 |
8049287 | Combi et al. | Nov 2011 | B2 |
8049568 | Youssef et al. | Nov 2011 | B2 |
8101969 | Robb et al. | Jan 2012 | B2 |
8120984 | Huang et al. | Feb 2012 | B2 |
8247867 | Nakata et al. | Aug 2012 | B2 |
8269263 | Li et al. | Sep 2012 | B2 |
8304275 | Schlarmann et al. | Nov 2012 | B2 |
8431989 | Bhalla et al. | Apr 2013 | B2 |
8541833 | Schulze et al. | Sep 2013 | B2 |
8642425 | Burke et al. | Feb 2014 | B2 |
8648432 | Haeusler | Feb 2014 | B2 |
8653587 | Hshieh | Feb 2014 | B2 |
8907394 | Hossain | Dec 2014 | B2 |
8947156 | Stultz et al. | Feb 2015 | B2 |
9123559 | Meiser | Sep 2015 | B2 |
9159786 | Chen | Oct 2015 | B2 |
9269779 | Deng et al. | Feb 2016 | B2 |
9443845 | Stefanov | Sep 2016 | B1 |
9446940 | Dawson et al. | Sep 2016 | B2 |
9458008 | Dawson et al. | Oct 2016 | B1 |
9472662 | Stefanov | Oct 2016 | B2 |
20010043112 | Voldman | Nov 2001 | A1 |
20050172717 | Wu et al. | Aug 2005 | A1 |
20060267161 | Thompson et al. | Nov 2006 | A1 |
20070004116 | Hshieh | Jan 2007 | A1 |
20070108511 | Hirler | May 2007 | A1 |
20070205431 | Robb et al. | Sep 2007 | A1 |
20080016683 | Brida et al. | Jan 2008 | A1 |
20080023473 | Spyros et al. | Jan 2008 | A1 |
20080111642 | Bohorquez | May 2008 | A1 |
20080121995 | Anderson et al. | May 2008 | A1 |
20080290430 | Mahadevan et al. | Nov 2008 | A1 |
20090261446 | Gogoi | Oct 2009 | A1 |
20100019393 | Hsieh et al. | Jan 2010 | A1 |
20100031077 | Swoboda | Feb 2010 | A1 |
20100187602 | Woolsey et al. | Jul 2010 | A1 |
20100315938 | Ascanio et al. | Dec 2010 | A1 |
20110127573 | Robb | Jun 2011 | A1 |
20120025305 | Takeda | Feb 2012 | A1 |
20120049187 | Haruyama et al. | Mar 2012 | A1 |
20120083075 | Robb et al. | Apr 2012 | A1 |
20120175635 | Weis et al. | Jul 2012 | A1 |
20120326227 | Burk et al. | Dec 2012 | A1 |
20130187196 | Kadow | Jul 2013 | A1 |
20130214365 | Schlarmann et al. | Aug 2013 | A1 |
20130249602 | Mauder et al. | Sep 2013 | A1 |
20130344667 | Qin et al. | Dec 2013 | A1 |
20140009212 | Altunkilic et al. | Jan 2014 | A1 |
20140021484 | Siemieniec et al. | Jan 2014 | A1 |
20140084362 | Schloesser et al. | Mar 2014 | A1 |
20140252512 | Yang et al. | Sep 2014 | A1 |
20140367773 | Poelzl | Dec 2014 | A1 |
20150028416 | Zundel et al. | Jan 2015 | A1 |
20150069610 | Grivna et al. | Mar 2015 | A1 |
20150102403 | Kuruc | Apr 2015 | A1 |
20150115387 | Buckley et al. | Apr 2015 | A1 |
20150145030 | Meiser et al. | May 2015 | A1 |
20150162324 | Mauder | Jun 2015 | A1 |
20150194915 | Mulliken | Jul 2015 | A1 |
20160051131 | Jeong et al. | Feb 2016 | A1 |
20160126348 | Deng et al. | May 2016 | A1 |
20160159642 | Hooper et al. | Jun 2016 | A1 |
Number | Date | Country |
---|---|---|
1887698 | Feb 2008 | EP |
2533246 | Dec 2012 | EP |
9530277 | Nov 1995 | WO |
0019540 | Apr 2000 | WO |
2015028838 | Mar 2015 | WO |
Entry |
---|
Robb, F. et al., “A new p-channel bidirectional trench power MOSFET for battery charging and protection,” Proceedings of the 22nd International Symposium on Power Semiconductor Devices & ICs, Hiroshima; pp. 405-408. |
Final Office Action dated Feb. 19, 2016 for U.S. Appl. No. 14/564,340, 15 pages. |
Non-Final Office Action dated Jun. 16, 2016 for U.S. Appl. No. 14/564,340, 15 pages. |
Non-Final Office Action dated Sep. 14, 2015 for U.S. Appl. No. 14/564,340, 13 pages. |
Arzumanyan, A. et al. “Flip Chip Power MOSFET: A New Wafer Scale Packaging Technique,” Proceedings of 2001 International Symposium on Power Semiconductor Devices and I.C.'s, Osaka, JP; pp. 251-254; Jun. 2001. |
Sawada, M. et al., “High side n-channel and bidirectional Trench Lateral Power MOSFETs on one chip for DCDC converter I.C.s,” Proceedings of the 20th International Symposium on Power Semiconductor Devices and I.C.s, Orlando, FL; May 2008. |
Notice of Allowance dated Dec. 7, 2016 for U.S. Appl. No. 14/912,346, 9 pages. |
Notice of Allowance dated Oct. 3, 2016 for U.S. Appl. No. 14/912,346, 9 pages. |
Final Office Action dated Jun. 16, 2016 for U.S. Appl. No. 14/506,037, 8 pages. |
Non-Final Office Action dated Jan. 21, 2016 for U.S. Appl. No. 14/506,037, 8 pages. |
Notice of Allowance dated Jul. 29, 2016 for U.S. Appl. No. 14/506,037, 8 pages. |
Extended European Search Report for corresponding EP 15199239.3, dated Jul. 7, 2016, 9 pages. |
Notice of Allowance dated Aug. 1, 2016 for U.S. Appl. No. 14/870,311, 5 pages. |
Notice of Allowance dated May 16, 2016 for U.S. Appl. No. 14/870,311, 8 pages. |
Notice of Allowance dated Jun. 13, 2016 for U.S. Appl. No. 14/870,333, 13 pages. |
Notice of Allowance dated Sep. 8, 2016, 2016 for U.S. Appl. No. 14/870,333, 9 pages. |
Restriction Requirement dated Mar. 22, 2016 for U.S. Appl. No. 14/870,333, 6 pages. |
Ex parte Quayle Action dated Jun. 24, 2016 for U.S. Appl. No. 14/658,598, 5 pages. |
Notice of Allowance dated Aug. 10, 2016 for U.S. Appl. No. 14/658,598, 5 pages. |
Restriction Requirement dated Mar. 1, 2016 for U.S. Appl. No. 14/658,598, 5 pages. |
Non-Final Rejection dated Dec. 7, 2016 for U.S. Appl. No. 15/132,855 21 pages. |
U.S. Appl. No. 14/994,197, filed Jan. 13, 2016. |
Notice of Allowance dated Apr. 17, 2017 for U.S. Appl. No. 15/132,855, 18 pages. |
Number | Date | Country | |
---|---|---|---|
20160163849 A1 | Jun 2016 | US |