Patent Application
20220190152
The present disclosure relates to a semiconductor device, and particularly to a technique to improve characteristics of gate leakage current and current collapse of a semiconductor device.
Semiconductor devices constituted of group-III nitride semiconductor (hereinafter, referred to as group-III nitride semiconductor devices) are well known (see, for example, Japanese Patent No. 5492919, and Japanese Unexamined Patent Application Publication Nos. 2010-225765 and 2008-210836). In particular, a group-III nitride semiconductor device which uses GaN (Gallium Nitride) and AlGaN (Aluminum Gallium Nitride) has a high insulation break-down voltage because such materials have a wide band gap.
Further, in a group-III nitride semiconductor device, a hetero structure such as an AlGaN/GaN can be formed easily. In the hetero structure, a channel (hereinafter, referred to as a 2DEG channel) due to high concentration electrons (two-dimensional electron gas, 2DEG) is generated on the side of the GaN layer at the AlGaN/GaN interface due to a piezo-electric charge generated through a lattice constant difference between materials and difference in band gap between materials. The 2DEG channel enables a large-current operation and high-speed operation of a semiconductor device.
A field effect transistor (FET) which operates by controlling a 2DEG channel is generally referred to as a high electron mobility transistor (HEMT).
Because of these features, group-III nitride semiconductor devices are applied to FETs and diodes etc. for power applications.
However, in the group-III nitride semiconductor devices disclosed in Japanese Patent No. 5492919, and Japanese Unexamined Patent Application Publication Nos. 2010-225765 and 2008-210836, there is a room for improvement in gate leakage current and current collapse. Accordingly, the present disclosure provides a semiconductor device of which gate leakage current and current collapse characteristics are improved.
A semiconductor device according to an aspect of the present disclosure includes: a substrate; a channel layer which is constituted of a single nitride semiconductor disposed on the substrate; a first barrier layer which is a nitride semiconductor disposed on and in contact with a selected part of an upper surface of the channel layer and having a band gap larger than a band gap of the channel layer; a gate layer which is a nitride semiconductor disposed on and in contact with the first barrier layer; a second barrier layer which is a nitride semiconductor disposed in contact with the first barrier layer in an area where the gate layer is not disposed above the channel layer, and having a band gap larger than the band gap of the channel layer and having a thickness or a band gap independently set with respect to the first barrier layer; a gate electrode which is disposed on the gate layer; and a source electrode and a drain electrode which are spaced apart from the gate layer and disposed on the second barrier layer.
In the above described semiconductor device, since a threshold voltage Vth is dependent substantially only on a thickness of the first barrier layer, it is possible to decrease variation in the threshold voltage Vth in a wafer by, for example, forming the first barrier layer through epitaxy with an excellent thickness controllability. Further, for example, when the gate layer is constituted of a semiconductor material of p-type, it is possible, by using a depletion layer of a p-n junction, to easily realize a normally-off-operation in which the threshold voltage Vth is positive and, at the same time, reduce the gate leakage current.
Further, it is also possible to suppress occurrence of current collapse by providing a thick second barrier layer in the vicinity of the gate end on the drain side where strong electric field concentration occurs, thereby physically separating the semiconductor surface (that is, the surface of the second barrier layer) from the 2DEG.
Moreover, electrons captured in a surface level and impurity level at the surface of the second barrier layer, etc. can be cancelled by holes injected from a p-type layer when a positive voltage is applied to the gate electrode, thus suppressing the occurrence of current collapse. Further, since the On-resistance is substantially determined by the thickness of the second barrier layer, it is possible to decrease the variation of On-resistance in a wafer. Further, by fully removing the first barrier layer, into which a p-type impurity has diffused, in an area other than directly beneath the gate, it is possible to inhibit the occurrence of gate leakage current at a high voltage, which flows in the p-type impurity diffusion layer.
These and other objects, advantages and features of the disclosure will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the present disclosure.
The present inventors have found that there is a room for further improvement in characteristics of gate leakage current and current collapse of semiconductor devices described in Japanese Patent No. 5492919, and Japanese Unexamined Patent Application Publication Nos. 2010-225765 and 2008-210836 mentioned in Description of the Related Art.
Note that although the gate leakage current generally refers to a current that flows between gate and drain, and between gate and source, the present description addresses a gate leakage current that flows between gate and drain of an FET in an Off-state.
Further, current collapse (also referred to as current slump) refers to a phenomenon in which drain current flowing in an FET in an On-state is hindered. This phenomenon occurs as a result of electrons being captured in a surface level, an impurity level, levels caused by crystal defects of a semiconductor, and the like. More specifically, electrons captured in the above described levels during an Off-state and an On-state of an FET remain in the concerned levels during an On-state to form a depletion layer in the surrounding, thereby hindering drain current. In a HEMT constituted of GaN, generally, the surface level of semiconductor is considered to be closely related to current collapse.
First, for the purpose of comparison with a semiconductor device of the present disclosure, the structure of a HEMT assumed by the present inventor will be described based on descriptions of Japanese Patent No. 5492919, and Japanese Unexamined Patent Application Publication Nos. 2010-225765 and 2008-210836.
HEMT 901 shown in
Further, recess 21 is formed in a part of barrier layer 20, and gate layer 5 (p-GaN, etc.) of a p-type semiconductor is formed so as to embed recess 21. Gate electrode 8 is formed above gate layer 5, and source electrode 9 and drain electrode 10, which are in ohmic contact with barrier layer 20, are formed so as to be spaced apart on both sides of gate electrode 8.
In HEMT 901, by providing p-type gate layer 5, it is possible to form a p-n junction between gate electrode 8 and 2DEG 7, thereby realizing a normally-off operation, and at the same time to reduce the gate leakage current. Moreover, by embedding gate layer 5 in recess 21, it is possible to realize a normally-off operation, and at the same time to keep 2DEG 7 and the surface (upper surface in
HEMT 902 shown in
After selectively removing gate layer 5, second barrier layer 6 (AlGaN, etc.) is selectively formed in an area where gate layer 5 is removed. Gate electrode 8 is formed above gate layer 5, and source electrode 9 and drain electrode 10, which are in ohmic contact with second barrier layer 6, are formed so as to be spaced apart on both sides of gate electrode 8.
In HEMT 902, since threshold voltage Vth is substantially determined by a thickness of first barrier layer 4, it is possible to decrease the variation of threshold voltage Vth in a wafer by forming first barrier layer 4 through an epitaxy with an excellent thickness controllability.
Further, as with HEMT 901, by forming barrier layer 20 and p-type gate layer 5 consecutively, it is possible to form a p-n junction between gate electrode 8 and 2DEG 7, thereby realizing a normally-off operation, and at the same time to reduce gate leakage current. Further, by forming second barrier layer 6, it is possible to keep 2DEG 7 and the surface (upper surface in
HEMT 903 shown in
According to HEMT 903, a portion covering side surface 23 of protrusion 22, out of barrier layer 20 covering protrusion 22 of channel layer 3, becomes thin due to low lateral growth rate of epitaxy. Therefore, it is possible to realize a normally-off operation by using the concerned thin portion of barrier layer 20.
Moreover, as with HEMT 902, it is possible to decrease the variation of threshold voltage Vth in a wafer by forming barrier layer 20 through epitaxy.
Further, as in HEMT 902, by forming barrier layer 20 and p-type gate layer 5 consecutively, it is possible to form a p-n junction between gate electrode 8 and 2DEG 7, thereby realizing a normally-off operation, and at the same time to reduce gate leakage current. Further, it is possible to keep 2DEG 7 and the surface (upper face in
In this way, in HEMTs 901 to 903 which are configured based on the concepts of Japanese Patent No. 5492919, and Japanese Unexamined Patent Application Publication Nos. 2010-225765 and 2008-210836, it is possible to reduce gate leakage current and current collapse.
However, the present inventors have noticed that there are the following concerns with HEMTs 901 to 903, which may impair reducing effect of gate leakage current and current collapse.
The first concern is that in HEMT 901, variation of threshold voltage Vth is likely to increase in a wafer. The threshold voltage Vth of HEMT 901 is determined substantially by a thickness of barrier layer 20 which is remained directly beneath recess 21 (hereinafter, referred to as a remained thickness). However, since there is no etching stopper layer, etc. in HEMT 901, two factors that determine the remained thickness of barrier layer 20 are an initial thickness of barrier layer 20 and a depth of recess 21. Therefore, it is difficult to increase uniformity of the remained thickness of barrier layer 20, and the variation of threshold voltage Vth is likely to increase between wafers in HEMT 901.
The second concern is that the variation of On-resistance is likely to increase in a wafer in HEMTs 901 to 903. In HEMTs 901 to 903, generally, the surface of barrier layer 20 or first barrier layer 4 is removed to a depth of several nm to several tens of nm by performing over etching when selectively etching and removing gate layer 5. For that reason, the variation of the thickness of barrier layer 20 or first barrier layer 4 increases in a wafer, the uniformity of distribution of 2DEG 7 is impaired, and consequently the variation of On-resistance of HEMTs 901 to 903 in a wafer increases.
The third concern is that leaking defect of gate current is likely to occur when high voltage is applied in HEMTs 901 to 903. In HEMTs 901 to 903, p-type impurities (Mg, etc.) may be diffused into barrier layer 20 or first barrier layer 4 with a high concentration when p-type gate layer 5 is formed through epitaxial regrowth. For that reason, when a high voltage (for example, a voltage of several hundreds of volt which is commonly used in a power semiconductor) is applied in HEMTs 901 to 903, there is concern that gate current may leak through an area into which the concerned p-type impurity has diffused.
The present inventors have conducted diligent work on a semiconductor device which can resolve the above described concerns and is excellent in reducing gate leakage current and current collapse to eventually reach a semiconductor device according to the present disclosure.
A semiconductor device according to Embodiment 1 is a semiconductor device which has a first barrier layer directly beneath a gate layer, and a second barrier layer, which is thicker than the first barrier layer, in an area other than the area directly beneath the gate layer. Embodiment 1 shows a non-limiting example of a minimum configuration of the semiconductor device according to Embodiment 1.
As shown in
Substrate 1 may be constituted of, for example, an Si substrate of a (111) crystal plane, as well as a substrate of sapphire, SiC, GaN, AlN, or the like.
Buffer layer 2 may be constituted of, for example, a single layer or plural layers of GaN, AlGaN, AlN, InGaN, AlInGaN, or the like.
Channel layer 3 may be constituted of, for example, GaN, as well as InGaN, AlGaN, AlInGaN, or the like.
First barrier layer 4 may be constituted of, for example, AlGaN as well as GaN, InGaN, AlGaN, AlInGaN, or the like.
Gate layer 5 may be constituted of, for example, a p-type semiconductor including p-GaN, as well as p-InGaN, p-AlGaN, p-AlInGaN, or the like.
In the example of
Gate electrode 8 is a metal electrode which is in ohmic contact or in Schottky contact with gate layer 5. Gate electrode 8 is constituted of, for example, a combination of one or more metals such as Ti, Ni, Pd, Pt, Au, W, WSi, Ta, TiN, Al, Mo, Hf, and Zr.
Source electrode 9 and drain electrode 10 are a metal electrode which is ohmic contact with at least one of 2DEG 7, second barrier layer 6, and channel layer 3. Source electrode 9 and drain electrode 10 are constituted of, for example, a combination of one or more metals such as Ti, Al, Mo, and Hf. Source electrode 9 and drain electrode 10 may be formed on, for example, the surface of second barrier layer 6, and may also be formed so as to be in contact with at least one of second barrier layer 6, 2DEG 7, and channel layer 3 by using a known ohmic recess structure (not shown).
First barrier layer 4 is constituted of a material having a larger band gap than that of channel layer 3. For that reason, 2DEG may occur in channel layer 3 directly beneath first barrier layer 4 in the same mechanism as that in which 2DEG 7 occurs in channel layer 3 directly beneath second barrier layer 6.
On the other hand, unlike second barrier layer 6, first barrier layer 4 is p-n joined with gate layer 5 which is constituted of a p-type semiconductor. As a result of that, when no gate voltage is applied to gate electrode 8, 2DEG directly beneath first barrier layer 4 disappears due to the depletion layer of the concerned p-n junction, and thus no current flows between the source and drain.
In this way, by constituting gate layer 5 with a p-type semiconductor, a normally-off operation is realized by a depletion layer of p-n junction, and also gate leakage current is reduced. For example, when first barrier layer 4 is constituted of AlGaN containing, in composition ratio, 20% of Al, a normally-off operation is realized by configuring that the thickness of first barrier layer 4 is less than or equal to 20 nm.
Moreover, if a film thickness of second barrier layer 6 is small, and a distance from channel layer 3 to the surface (the upper surface in the figure) of second barrier layer 6 is too small, a large current collapse occurs due to electrons captured in the surface level of second barrier layer 6. For that reason, a film thickness of second barrier layer 6 in the vicinity of gate end 11 is made larger than that of first barrier layer 4 and more than or equal to 20 nm. Especially, for uses for a general purpose power semiconductor element of at least 600 rated voltage, the film thickness of second barrier layer 6 may be more than or equal to 30 nm (for example, about 100 nm which is a critical film thickness of epitaxy).
Semiconductor device 101 configured as described above performs normally-off operation as follows. That is, when no gate voltage is applied to gate electrode 8, since a depletion layer spreads directly beneath gate layer 5, no 2DEG is present and semiconductor device 101 is in an Off-state. When a positive gate voltage more than a threshold voltage Vth is applied to gate electrode 8 with source electrode 9 being grounded and drain electrode 10 applied with a positive load voltage, 2DEG occurs below the gate and is connected with left and right 2DEG causing a drain current to flow, so that semiconductor device 101 turns into an On-state (not shown).
In a general purpose power semiconductor element with a rated voltage of 600 V, a load voltage of at most 600 V is applied to the source and drain when in Off-state. Transition times from Off-state to On-state and from On-state to Off-state in such a general purpose power semiconductor element are both at least several nanoseconds to several tens of nanoseconds.
According to semiconductor device 101 configured as described above, the following effects can be obtained.
The threshold voltage Vth of semiconductor device 101 is substantially dependent on the thickness of first barrier layer 4. By forming first barrier layer 4 by using epitaxy such as MOCVD (Metal Organic Chemical Vapor Deposition) which exhibits an excellent thickness controllability, it is possible to decrease the variation of threshold voltage Vth in a wafer plane.
Moreover, by constituting gate layer 5 with a p-type semiconductor material, it is possible to realize a normally-off operation by using a depletion layer of a p-n junction, and at the same time to reduce gate leakage current.
Further, by providing thick second barrier layer 6 in the vicinity of gate end 11 on the drain side in which strong electric field concentration occurs, to physically separate the surface of the semiconductor layer (here, the surface of second barrier layer 6) from channel layer 3 including 2DEG 7, it is possible to suppress occurrence of current collapse.
Moreover, since electrons captured in a surface level and impurity level at the surface of second barrier layer 6, etc. are cancelled by holes injected from p-type gate layer 5 when a positive voltage is applied to gate electrode 8, it is possible to suppress the occurrence of current collapse.
Moreover, the On-resistance of semiconductor device 101 is dependent on the thickness of second barrier layer 6. For that reason, by forming second barrier layer 6 by using epitaxy such as MOCVD which exhibits an excellent thickness controllability, it is possible to decrease variation of On-resistance in a wafer plane.
Next, various variations of semiconductor device 101 described above will be described. It is noted that a component equivalent to a component of semiconductor device 101 is denoted by the same symbol, and regarding matters equivalent to those of semiconductor device 101, description thereof will be appropriately omitted by applying the above described description.
In an actual semiconductor device, impurities contained in gate layer 5 may diffuse into first barrier layer 4 when gate layer 5 is formed. Such a case will be described in Variation 1.
As a specific example, in semiconductor device 102, the concentration of p-type impurities contained in first barrier layer 4 may be more than or equal to 1E18 cm−3, and the concentration of the p-type impurities contained in second barrier layer 6 may be less than 1E18 cm−3. Where, 1EX cm−3 means 1×10X cm−3, and the same notation will be used hereinafter.
Such a structure may be formed by, for example, fully removing an unnecessary portion of gate layer 5, as well as first barrier layer 4, which lies directly beneath the unnecessary portion, together with diffusion layer 12 when patterning of gate layer 5 is performed.
According to thus configured semiconductor device 102, the same effects as those of semiconductor device 101 can be obtained. Moreover, since in semiconductor device 102, diffusion layer 12 which works as a leakage path of gate current is fully removed in an area other than directly beneath gate layer 5, leakage of gate current when a high voltage is applied in semiconductor device 102 is suppressed.
In an actual semiconductor device, impurities added to gate layer 5 may diffuse into channel layer 3 depending on the impurity concentration of gate layer 5 and process conditions (temperature and time, etc.) for forming gate layer 5. In Variation 2, such a case will be described.
As a specific example, in semiconductor device 103, the concentration of p-type impurities contained in first barrier layer 4 may be more than or equal to 1E18 cm−3, and the concentration of the p-type impurities contained in channel layer 3 (particularly, diffusion layer 13) directly beneath second barrier layer 6 may be less than 1E18 cm−3. Such a structure may be formed by, for example, optimizing the impurity concentration of gate layer 5, and process conditions for forming gate layer 5.
According to thus configured semiconductor device 103, it is possible to obtain, in addition to the same effects as those of semiconductor devices 101 and 102, an effect of suppressing leakage of gate current when a high voltage is applied in semiconductor device 103 by suppressing the concentration of impurities contained in diffusion layer 13.
In the above described semiconductor devices 101 to 103, although the lower surface of first barrier layer 4 and the lower surface of second barrier layer 6 are shown at the same height, the lower surface of second barrier layer 6 may be located at a position lower than the lower surface of first barrier layer 4. In Variation 3, such a case will be described.
Such a structure may be formed by, for example, performing over etching when patterning of gate layer 5 is performed, thereby fully removing unnecessary portion of gate layer 5, as well as first barrier layer 4 together with diffusion layer 12, and further removing the surface layer of channel layer 3.
According to thus configured semiconductor device 104, the same effects as those of semiconductor devices 101 to 103 can be obtained. Further, since diffusion layer 12 in an area other than gate layer 5 is surely removed even when there is variation in the depth of etching in a wafer plane, it is possible to more securely suppress leakage of gate current when a high voltage is applied in semiconductor device 104.
In the above described semiconductor device 104, although the upper surface of second barrier layer 6 is shown at a position lower than the upper surface of first barrier layer 4 (that is, the upper surface of diffusion layer 12 formed in barrier layer 4) and higher than the lower surface of first barrier layer 4, the upper surface of second barrier layer 6 may be located at a position higher than the upper surface of first barrier layer 4. In Variation 4, such a case will be described.
Such a structure may be formed, as a specific example, by providing second barrier layer 6 so as to be thicker than first barrier layer 4 in semiconductor device 104.
According to thus configured semiconductor device 105, the same effects as those of semiconductor devices 101 to 104 can be obtained. Further, by providing a thick second barrier layer 6 to keep the surface of second barrier layer 6 and 2DEG 7 to be physically apart from each other in the vicinity of gate end 11 on the drain side where electric field is most concentrated, it is possible to reduce current collapse.
In the above described semiconductor devices 101 to 105, it is assumed that the band gap of first barrier layer 4 and the band gap of second barrier layer 6 are set independently, and the relationship between these band gaps is not particularly specified. However, as one example, the band gap of second barrier layer 6 may be larger than the band gap of first barrier layer 4. Such a case will be described in Variation 5.
According to thus configured semiconductor device 106, it is possible to obtain, in addition to the same effects as those of semiconductor devices 101 to 105, an effect of reducing On-resistance of semiconductor device 106 and increasing maximum drain current since the concentration of 2DEG 7 which occurs directly beneath second barrier layer 14 increases.
In the above described semiconductor devices 101 to 106, second barrier layer 6, 14 may contain n-type impurities for setting the band gap of second barrier layer 6, 14 to be larger than the band gap of channel layer 3. When an upper layer, middle layer, and lower layer are defined in this order from the side, where source electrode 9 and drain electrode 10 are formed, of second barrier layer 6, 14, n-type impurities may be added to any one of the upper layer, middle layer, and lower layer, or may be added to two or three layers. As one specific example, the concerned upper layer may be constituted of n-AlGaN/AlGaN, the middle layer of AlGaN/n-AlGaN/AlGaN, and the lower layer of AlGaN/n-AlGaN. Such a case will be described in Variation 6.
According to thus configured semiconductor device 107, it is possible to obtain, in addition to the same effects as those of semiconductor devices 101 to 106, an effect of decreasing On-resistance and increasing maximum drain current of semiconductor device 107 since the concentration of 2DEG 7 which occurs directly beneath second barrier layer 15 increases.
Although, in the above described semiconductor devices 101 to 107, second barrier layer 6, 14, 15 is in contact with channel layer 3, a spacer layer which is a nitride semiconductor having a band gap larger than that of second barrier layer 6, 14, 15 may be provided between second barrier layer 6, 14, 15 and channel layer 3. Such a case will be described in Variation 7.
Spacer layer 16 and second barrier layer 6 may be constituted of, for example, AlN and AlGaN, respectively, or may also be constituted of AlGaN having a larger compositional ratio of Al, and AlGaN having a smaller compositional ratio of Al, respectively. Note that spacer layer 16 may be provided in any of semiconductor devices 101 to 107 without being limited to semiconductor device 105.
According to thus configured semiconductor device 108, the same effects as those of semiconductor devices 101 to 107 can be obtained. Further, it becomes possible to increase the mobility of 2DEG 7 which occurs in channel layer 3 directly beneath spacer layer 16, thereby allowing high-speed operation. Moreover, it is possible to further increase carrier density, thereby decreasing On-resistance and increasing maximum drain current.
Although, in the above described semiconductor devices 101 to 108, source electrode 9 and drain electrode 10 are provided on second barrier layer 6 without any explicit layer being interposed, a cap layer may be provided on second barrier layer 6, and source electrode 9 and drain electrode 10 are provided on the cap layer. Such a case will be described in Variation 8.
According to thus configured semiconductor device 109, the same effects as those of semiconductor devices 101 to 108 can be obtained. Further, by physically separating the surface of the semiconductor layer (here, the surface of cap layer 17) from 2DEG 7 by an amount of the thickness of cap layer 17 without increasing concentration of 2DEG 7 which occurs directly beneath second barrier layer 6, it is possible to suppress the occurrence of current collapse.
Although, in the above described semiconductor devices 101 to 109, channel layer 3 is configured in a single layer, the channel layer may be configured in a laminated body of multiple (for example, two) layers. Such a case will be described in Variation 9.
The band gap of first channel layer 24a may be larger than the band gap of second channel layer 24b. For example, first channel layer 24a may be constituted of AlGaN, InGaN, AlInGaN, or the like, and second channel layer 24b may be constituted of GaN.
Such a structure may be formed by, for example, performing over-etching when patterning of gate layer 5 is performed, to remove an unnecessary portion of gate layer 5 as well as entire second channel layer 24b underling directly beneath the unnecessary portion and a surface layer of first channel layer 24a.
Note that channel layer 24 may be provided in any of semiconductor devices 101 to 109 without being limited to semiconductor device 110.
According to thus configured semiconductor device 110, the same effects as those of semiconductor devices 101 to 109 can be obtained. Further, when second channel layer 24b is constituted of GaN, and first channel layer 24a is constituted of AlGaN, high-voltage resistant operation becomes possible. Further, when second channel layer 24b is constituted of GaN, and first channel layer 24a is constituted of InGaN, mobility and density of carrier increase, thus making it possible to decrease On-resistance and increase maximum drain current.
Although, in the above described semiconductor devices 101 to 110, the lower surface of second barrier layer 6 is shown at the same height on the source side and the drain side, the height of the lower surface of the second barrier layer may not necessarily be the same on the source side and the drain side. Such a case will be described in Variation 10.
Such a structure may be formed by, for example, performing over etching, which is deeper on the side of drain than on the side of source, when patterning of gate layer 5 is performed. Alternatively, over etching may not be performed on the side of source, and the lower surface of second barrier layer 6 is in contact with the upper surface of diffusion layer 12 (not shown). Note that the height of the lower surface of second barrier layer 6 may differ between the source side and the drain side not only in semiconductor device 111 but also in any of semiconductor devices 101 to 110.
Since, in a common FET (including HEMT), when a high voltage is applied, no high voltage will be applied between the gate and source, and diffusion layer 12 which remains on the side of the source is not likely to become a leakage path of gate current. For that reason, according to semiconductor device 111 configured as described above, the same effects as those of semiconductor devices 101 to 110 can be obtained. Moreover, resistance of 2DEG on the source side can form a 2DEG layer based on the sum of the first barrier layer and the second barrier layer, thus allowing to reduce On-resistance and to increase maximum drain current. At the same time, since diffusion layer 12, into which a p-type impurity has diffused, on the drain side is fully removed, it is possible to reduce gate leakage current at a high voltage, which flows in the p-type impurity diffusion layer.
Next, a manufacturing method of a semiconductor device according to Embodiment 1 will be described with reference to
First, as shown in
As described above, substrate 1 is for example an Si substrate of a (111) crystal plane, and besides substrates of sapphire, SiC, GaN, AlN, and the like can be used.
As buffer layer 2, for example, a single or plural layers of GaN, AlGaN, AlN, InGaN, or the like are formed. Although channel layer 3 is a single layer constituted of GaN in this embodiment, it may be a single layer constituted of InGaN, AlGaN, AlInGaN, or the like. Although first barrier layer 4 is constituted of AlGaN, it may be constituted of, for example, GaN, InGaN, AlInGaN, or the like depending on the material of channel layer 3. Although gate layer 5 is constituted of p-GaN which is a p-type group-III nitride semiconductor device, it may be a single layer of p-InGaN, p-AlGaN, p-AlInGaN, or the like.
When forming gate layer 5, a p-type impurity constituted of Mg (besides, may be C, Zn, or the like) is added at a concentration of 1E19 cm−3 to 1E20 cm−3. The concerned impurity may form diffusion layer 12 in first barrier layer 4 depending on the concentration of the concerned impurity and the process temperature for growing gate layer 5. The concerned diffusion layer may reach channel layer 3.
Next, as shown in
Next, as shown in
At this moment, it is possible to suppress leakage of gate current at high voltage operation by fully removing diffusion layer 12 in an area other than resist pattern 19, or by removing at least a portion of diffusion layer 12 where impurity concentration is more than or equal to 1E18 cm−3. On the other hand, when the diffusion layer remains without being fully removed, if an area in which impurity concentration is more than or equal to 1E18 cm−3 remains, leakage of gate current during high voltage operation occurs.
When diffusion layer 12 is formed only in first barrier layer 4, the depth of dry etching for removing diffusion layer 12 is enough if it is a depth which allows to fully remove first barrier layer 4. However, considering that there is variation in the depth of dry etching in a wafer plane, and that diffusion layer 12 may be formed reaching channel layer 3, channel layer 3 may be over etched to a depth of several nm to several tens of nm as shown in
Next, as shown in
Second barrier layer 6 may be regrown to a thickness of at least more than or equal to 20 nm, possibly more than or equal to 30 nm for suppressing current collapse. Second barrier layer 6 may be provided at a thickness not reaching the lower surface of gate layer 5 depending on the size and regrowth condition of mask layer 18. Further, second barrier layer 6 may be grown to a thickness to cover a part of the side surface of gate layer 5 as long as a part of gate layer 5 to which gate electrode 8 is to be connected later is exposed. Moreover, a cap layer may be formed on second barrier layer 6 (not shown).
Next, as shown in
Next, as shown in
Semiconductor devices 101 to 111 are manufactured by using the manufacturing method described so far and manufacturing methods similar to those described above. Effects which can be obtained by semiconductor devices 101 to 111 are as described above, and description thereof will not be repeated here.
Although, in semiconductor devices 101 to 111 shown in Embodiment 1, second barrier layer 6 covers a part of the side surface of gate layer 5, the second barrier layer may cover at least a part of the side surface of the gate layer and, for example, the second barrier layer may cover the entire side surface of the gate layer. Such a case will be described in Embodiment 2. Note that hereinafter, components equal to those of Embodiment 1 are denoted by the same symbols, and the above description are intended to apply to matters equivalent to those of Embodiment 1, and description thereof will be appropriately omitted.
According to semiconductor device 201 thus configured, the same effects as those of semiconductor devices 101 to 111 can be obtained. Further, by providing a thick second barrier layer 6 thereby physically keeping the surface of second barrier layer 6 and 2DEG 7 to be apart from each other in the vicinity of gate end 11 on the drain side where electric field is most concentrated, it is possible to reduce current collapse.
Also, in the above described semiconductor device 201, as in semiconductor device 104 according to Variation 3, impurities which are contained in gate layer 5 when gate layer 5 is formed may diffuse into first barrier layer 4. Such a case will be described in Variation 11.
According to thus configured semiconductor device 202, both effects of semiconductor device 201 and semiconductor device 104 can be obtained.
Next, a manufacturing method of a semiconductor device according to Embodiment 2 will be described with reference to
First, as shown in
Next, as shown in
Next, as shown in
Second barrier layer 6 may be regrown to a thickness of at least more than or equal to 20 nm, possibly more than or equal to 30 nm to suppress current collapse. Second barrier layer 6 is also provided on gate layer 5, unlike in Embodiment 1.
Next, as shown in
Next, as shown in
Next, as shown in
Semiconductor devices 201 and 202 are manufactured by using the manufacturing method described above and a similar manufacturing method. The effects to be obtained by semiconductor devices 201 and 202 are as described above and description thereof will not be repeated here.
In Embodiment 3, an example of the structure of an electrode of the semiconductor device described in Embodiments 1 and 2 will be described.
For example, as shown in
Moreover, as shown in
So far, semiconductor devices according to plural aspects of the present disclosure have been described based on embodiments, however, the present disclosure will not be limited to those embodiments. Aspects in which various alterations conceived by the person skilled in the art are made to those embodiments, and aspects which are constructed by combining components in different embodiments can be included in the present disclosure as long as they do not depart from the spirit of the present disclosure.
For example, although, in the above description, semiconductor devices 102 to 111, and 202 have been described as respectively independent Variations 1 to 11, further different variations may be constituted by combining semiconductor devices 102 to 111, and 202.
The semiconductor device of the present disclosure can be used for power devices as a HEMT which can realize a normally-off operation, and at the same time can significantly suppress gate leakage current and reduce current collapse.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-211254 | Oct 2015 | JP | national |
This application is a Divisional of U.S. patent application Ser. No. 15/958,075 filed on Apr. 20, 2018, which is a U.S. continuation application of PCT International Patent Application Number PCT/JP2016/004679 filed on Oct. 25, 2016, claiming the benefit of priority of Japanese Patent Application Number 2015-211254 filed on Oct. 27, 2015, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15958075 | Apr 2018 | US |
| Child | 17688440 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2016/004679 | Oct 2016 | US |
| Child | 15958075 | US |
