This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-123030, filed on May 21, 2009, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
In recent years, there has been a demand for a reduction in the thickness of DRAM packages. However, for packages having a uBGA structure in which chip terminals are connected to a tape substrate by lead bonding and packages having an sFBGA structure in which packages of the uBGA structure are stacked, the package needs to have an appropriate height for the lead bonding. Thus, the reduction in package thickness is limited. Furthermore, to allow the lead bonding to be achieved, one end of each lead needs to be projected from the tape substrate. Hence, the arrangement of wires is restricted.
Opening 109 is formed in tape substrate 102 and stress buffering layer 104. Chip terminals 106 are provided on the bottom surface of semiconductor chip 101. Semiconductor chip 101 is stacked on adhesion layer 104b of stress buffering layer 104 so that chip terminals 106 are arranged inside opening 109. Chip terminals 106 are joined to wiring layer 103a by bonding. Specifically, wiring layer 103a is cut, and then pressed against and joined to respective chip terminals 106. The cutting and pressing of wiring layer 103a is performed using a bonding tool.
Wiring layer 103a projecting into opening 109, that is, a lead, need to be linear and to have a predetermined length before being cut. If the lead is not linear, when a load is applied to the lead using the tool in order to cut the lead, the lead is flexurally deformed and thus becomes difficult to cut. Furthermore, if the lead does not have the predetermined length, the cut lead may fail to reach the corresponding chip terminal, resulting in improper electric continuity. Furthermore, the lead that is connected to the chip terminal may undergo high tension and thus broken.
Moreover, in the above-described junction method, after wiring layer 103a is cut, unwanted parts of tape substrate 102 and stress buffering layer 104 may remain in opening 109. Thus, the semiconductor device is difficult to miniaturize in the width direction thereof.
In one embodiment, there is provided a semiconductor device that includes a substrate including a substrate which has an opening, a wiring layer formed on a principal surface of the substrate, and a plurality of extending portions which are a part of the wiring layer and which extend like cantilevers from an inner peripheral edge of the opening, a semiconductor chip which is mounted on the substrate and which has a plurality of terminals to which the respective extending portions are joined, and resin which seals a junction portion between a tip portion of each of the extending portions and the corresponding one of the terminals of the semiconductor chip.
In another embodiment, there is provided a method that includes providing a substrate which has an opening, a wiring layer formed on a principal surface of the substrate, and a plurality of extending portions which are a part of the wiring layer and which extend like cantilevers from an inner peripheral edge of the opening, mounting a semiconductor chip on the substrate, joining terminals of the semiconductor chip exposed inside the opening to the respective extending portions, and sealing a junction portion between each of the extending portions and the corresponding terminal.
The above feature and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purpose.
Referring now to
Wiring layer 3 is provided on principal surface 2a of tape substrate 2. Solder balls 7 are provided on a surface (back surface) of tape substrate 2 located opposite principal surface 2a. Wiring layer 3 provided on principal surface 2a is electrically connected to solder balls 7 provided on the back surface, via respective through-holes 2b (
As shown in
Wiring layer 3 includes stack portion 3a stacked on tape substrate 2 and a plurality of extending portions 3b shaped like cantilevers and extending from the opposite sides of opening 9. That is, extending portions 3b form flying leads. The angle between each extending portion 3b and corresponding inner peripheral edge 9e of opening 9 is substantially a right angle. Furthermore, extending portions 3b are arranged parallel to one another. End 3b1 of each extending portion 3b (flying lead) extending like a cantilever from inner peripheral edge 9e is joined to corresponding chip terminal 6. Specifically, each extending portion 3b extending from long side 9a of opening 9 is joined to corresponding chip terminal 6 in terminal row 6a. Each extending portion 3b extending from long side 9b is joined to corresponding chip terminal 6 in terminal row 6b. That is, each extending portion 3b is joined to corresponding chip terminal 6 located close to the side from which this extending portion 3b extends. Additionally, the junction portion between end 3b1 of extending portion 3b and corresponding chip terminal 6 is sealed with sealing resin 5. Stack portion 3a of wiring layer 3 is joined to solder balls 7.
In the present embodiment, two terminal rows 6a and 6b are arranged in the center of semiconductor chip 1. Moreover, terminal rows 6a and 6b are arranged along respective long sides 9a and 9b of opening 9. However, the number and arrangement of terminal rows are not limited to those in the above-described configuration. For example, one of terminal rows 6a and 6b may be arranged in the center of semiconductor chip 1 along long sides 9a and 9b.
Stress buffering layer 4 is stacked on wiring layer 3. Stress buffering layer 4 has a three-layer structure with core layer 4a and adhesion layers 4b provided on the respective opposite sides of core layer 4a. Semiconductor chip 1 is stacked on adhesion layer 4b of stress buffering layer 4.
Now, a method for manufacturing a semiconductor device according to the exemplary embodiment will be described with reference to
First, as shown in
Next, as shown in
Next, as shown in
Then, as shown in
Then, as shown in
Finally, as shown in
In the related art, the wiring layer which is joined to the chip terminals of the semiconductor chip is cut with a bonding tool after the semiconductor chip is mounted on the stress buffering layer. Thus, to allow the wiring layer to be cut by raising and lowering the bonding tool, the stress buffering layer needs to have a thickness of at least 100 μm. This is because the wiring layer may be improperly cut when the stress buffering layer has a thickness of less than 100 μm. Thus, reducing the thickness of the semiconductor device is limited in the related art.
On the other hand, in the manufacturing method according to the present embodiment, the wiring layer which is provided on the tape substrate is cut before semiconductor chip 1 is mounted on the tape substrate. Specifically, as shown in
Furthermore, in semiconductor device 100 shown in
Semiconductor device structures and manufacturing methods according to exemplary embodiments described below are essentially similar to those according to the first exemplary embodiment. Thus, a detailed description of the semiconductor device structure and manufacturing method according to each exemplary embodiment is omitted. Only differences from the first exemplary embodiment will be described. Furthermore, the same members as those already described in the first exemplary embodiment are denoted by the same reference numerals.
In the first exemplary embodiment, each extending portion 3b extending from long side 9a of opening 9 is joined to corresponding chip terminal 6 in terminal row 6a. Each extending portion 3b extending from long side 9b of opening 9 is joined to corresponding chip terminal 6 in terminal row 6b (
In the second exemplary embodiment, each extending portion 3b is joined to corresponding chip terminal 6 in terminal row 6a located far from the side from which this extending portion 3b extends. That is, each extending portion 3b extending from long side 9b of opening 9 is joined to corresponding chip terminal 6 (not shown in the drawings) in terminal row 6a arranged at distance S2 from long side 9b. Each extending portion 3b extending from long side 9a is also joined to corresponding chip terminal 6 in terminal row 6b arranged far from the side from which extending portion 3b extends. However, this is not shown in the
In the related art, when leads are joined to the respective chip terminals, a bonding tool is used to cut the leads. Thus, the shape and length of the leads need to be suitable for the cutting. On the other hand, in the present invention, the preformed extending portions are joined to the respective chip terminals. Hence, as shown in
In the first exemplary embodiment, the angle between each extending portion 3b and inner peripheral edge 9e of opening 9 is a right angle. In contrast, in the third exemplary embodiment, the angle between some extending portions 3b and inner peripheral edge 9e of opening 9 is R1. The angle between s few other extending portions 3b and inner peripheral edge 9e of opening 9 is R2. The angle between the remaining extending portions 3b and inner peripheral edge 9e of opening 9 is R3. Angles R1, R2, and R3 are different from one another. Angle R3 is a right angle. That is, extending portions 3b extend at different angles. As a result, extending portions 3b are not parallel to one another.
In the related art, a plurality of leads need to be parallel to one another so that they can be uniformly and reliably cut with the bonding tool. There is no limitation which is caused by cutting operation that uses a bonding tool. Thus, the extending portions need not be parallel to one another. This allows wires connecting solder balls 7 and chip terminal 6 shown in
In the related art, the leads need to extend linearly into the opening so that they can be uniformly and reliably cut with the bonding tool without being flexurally deformed. There is no limitation which is caused by cutting operation that uses a bonding tool. Thus, the bent portion can be provided on the extending portion.
As described in the third exemplary embodiment, to improve the electrical characteristics, the present invention allows each extending portion to be located so as to minimize the length of the wire between the corresponding solder ball and chip terminal. However, when each extending portion is located so as to minimize the length of the wire between the corresponding solder ball and chip terminal, the adjacent extending portions may be arranged too close to each other.
Bending the extending portion 3b as shown in
As described above in each exemplary embodiment, There is no limitation which is caused by cutting operation that uses a bonding tool. Thus, in order to improve the electrical characteristics, each wire can be formed so as to have a minimum length between the solder ball and the chip terminal. However, when only the wire length is taken into account, can the angle between the long side of the inner peripheral edge and the extending portion be an angle other than a right angle. However, to prevent the extending portion from being twisted, the angle between the long side and the extending portion is preferably as close to a right angle as possible. The principle of possible twist in extending portion 3b will be described with reference to
On the other hand, the angle between extending portion 3b shown in
Thus, in the semiconductor device according to the fifth exemplary embodiment, as shown in
In the fifth exemplary embodiment, to prevent a possible twist in extending portion 3b, long sides 9a and 9b of inner peripheral edge 9e are shaped such that the angle between each extending portion 3b and inner peripheral edge 9e is almost a right angle (
In the sixth exemplary embodiment, pressing force F is applied to the outside of the center line of extending portion 3b to prevent a possible twist in extending portion 3b.
Extending portion 3b shown in
On the other hand, the angle between extending portion 3b shown in
Now, the position of pressing point P will be described in further detail with reference to
When pressing force F is applied onto center line C of extending portion 3b shown in
If the twist in extending portion 3b is not sufficiently suppressed even by pressing the tip of extending portion 3b, pressing point P is set at a position located closest to the position where the stresses offset each other and away from the tip of extending portion 3b to the extent that bonding can be properly achieved.
The sixth exemplary embodiment allows the semiconductor device to be miniaturized. The sixth exemplary embodiment further allows extending portion 3b to be joined to chip terminal 6 without being twisted even if the angle between extending portion 3b and inner peripheral edge 9e is not a right angle.
Thus, also in the seventh exemplary embodiment, a technique similar to that described in the sixth exemplary embodiment is used to suppress a twist in extending portion 3b. That is, as shown in
With reference to
If a twist in extending portion 3b is not sufficiently suppressed even by pressing the tip of extending portion 3b, pressing point P is set at a position located closest to the position where the stresses offset each other and away from the tip of extending portion 3b to the extent that bonding can be properly achieved.
The seventh exemplary embodiment allows the semiconductor device to be miniaturized. Furthermore, even if extending portion 3b includes bent portion 11, extending portion 3b can be joined to chip terminal 6 without being twisted.
It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Number | Date | Country | Kind |
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2009-123030 | May 2009 | JP | national |