Semiconductor device

Abstract

A semiconductor device capable of reducing a threshold voltage is obtained. The semiconductor device includes a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween, and a gate electrode formed on the channel region through a gate insulating film and including a metal-containing layer arranged in the vicinity of an interface between the gate insulating film and the gate electrode, wherein the metal-containing layer is so formed in the form of dots as to partially cover the surface of the gate insulating film, and the average distance between dots forming the metal-containing layer is set to not more than a diameter of the dot of the metal-containing layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing a structure of a CMOS according to a first embodiment of the present invention;

FIGS. 2 to 10 are sectional views for illustrating a process of fabricating the CMOS according to the first embodiment of the present invention;

FIG. 11 is a sectional view showing a structure of a CMOS according to a second embodiment of the present invention;

FIGS. 12 to 14 are sectional views for illustrating a process of fabricating the CMOS according to the second embodiment of the present invention;

FIG. 15 is a graph showing the relation between average distances between dots forming a metal-containing layer and flat band voltages; and

FIG. 16 is a CV characteristic diagram showing results of CV measurement (simulation).

Claims

1. A semiconductor device comprising: a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween; anda gate electrode formed on said channel region through a gate insulating film and including a metal-containing layer arranged in the vicinity of an interface between said gate insulating film and said gate electrode, whereinsaid metal-containing layer is so formed in the form of dots as to partially cover the surface of said gate insulating film, andthe average distance between dots forming said metal-containing layer is set to not more than a diameter of said dot forming said metal-containing layer.

2. The semiconductor device according to claim 1, wherein the average distance between said dots forming said metal-containing layer is not more than 1.5 nm.

3. The semiconductor device according to claim 1, wherein said gate electrode includes a first semiconductor layer so formed as to be embedded in a region between said dots forming said metal-containing layer.

4. The semiconductor device according to claim 3, wherein said first semiconductor layer is constituted by a silicon layer.

5. The semiconductor device according to claim 3, wherein the thickness of said first semiconductor layer is larger than a diameter of said dot of said metal-containing layer.

6. The semiconductor device according to claim 3, wherein said gate electrode includes a second semiconductor layer provided on said first semiconductor layer.

7. The semiconductor device according to claim 6, wherein the thickness of said first semiconductor layer is smaller than that of said second semiconductor layer.

8. The semiconductor device according to claim 1, wherein said gate electrode further includes a metal layer or a metallic compound layer so formed as to embedded in a region between said dots forming said metal-containing layer; andsaid metal layer or said metallic compound layer contains a metal forming a level on a side closer to a conduction band or a valence band of silicon than an intermediate energy level between said conduction band and said valence band of silicon, or having a work function corresponding to a portion around said conduction band or said valence band of silicon.

9. The semiconductor device according to claim 8, wherein said metal layer or said metallic compound layer contains a metal forming a level on a side closer to said conduction band of silicon than an intermediate energy level between said conduction band and said valence band of silicon, or having a work function corresponding to a portion around said conduction band of silicon, in a case where said source/drain regions are n-type regions.

10. The semiconductor device according to claim 9, wherein said metallic compound layer is constituted by an Hf silicide layer.

11. The semiconductor device according to claim 8, wherein said metal layer or said metallic compound layer contains a metal forming a level on a side closer to said valence band of silicon than an intermediate energy level between said conduction band and said valence band of silicon, or having a work function corresponding to a portion around said valence band of silicon, in a case where said source/drain regions are p-type regions.

12. The semiconductor device according to claim 11, wherein said metallic compound layer is constituted by an Ru silicide layer.

13. The semiconductor device according to claim 8, wherein said gate electrode includes a third semiconductor layer provided on said metal layer or said metallic compound layer.

14. The semiconductor device according to claim 13, wherein the thickness of said metal layer or said metallic compound layer is smaller than that of said third semiconductor layer.

15. The semiconductor device according to claim 8, wherein the thickness of said metal layer or said metallic compound layer is larger than a diameter of said dot of said metal-containing layer.

16. The semiconductor device according to claim 1, wherein said metal-containing layer is made of TaN.

17. The semiconductor device according to claim 1, wherein said gate insulating film includes an HfO2 film.

18. The semiconductor device according to claim 1, wherein said metal-containing layer is so formed on the surfaces of said gate insulating film as to disperse substantially over the whole areas thereof.