Patent Application
20230215776
The present disclosure relates to a semiconductor device.
Japanese Patent Application Laid-Open No. 2012-028561 discloses a semiconductor device including: an insulating substrate having one surface mounted with a semiconductor element; and a heat sink having a plate shape, the heat sink having one surface joined in a heat transferring manner to another surface of the insulating substrate through a buffer material.
In the conventional techniques, there has been a problem that a semiconductor device is deformed due to a temperature rise, pumping-out being a phenomenon in which a heat dissipating material is pushed out due to the deformation occurs, the pushed out heat dissipating material does not return to its original state during cooling to form a gap, and heat dissipation is deteriorated.
An object of the present disclosure is to provide a semiconductor device capable of suppressing pumping out of a heat dissipating material and thereby suppressing decrease in heat dissipation.
A semiconductor device of the present disclosure includes: an insulating substrate; a semiconductor chip; a base plate; a first heat dissipating material; and a case. The semiconductor chip and a sealing material for sealing the semiconductor chip are housed in the case. The insulating substrate includes an insulating layer and a conductor pattern provided on an upper surface of the insulating layer. The semiconductor chip is joined onto the conductor pattern by a joining material. A lower surface of the insulating substrate and an upper surface of the base plate are in contact with each other with interposition of the first heat dissipating material. The insulating substrate and the base plate are not fixed to each other.
With the present disclosure, there is provided a semiconductor device capable of suppressing pumping out of a heat dissipating material, thereby suppressing decrease in heat dissipation.
These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings.
The semiconductor device 100a is a power semiconductor device.
The semiconductor device 100a includes a semiconductor chip 1a, a semiconductor chip 1b, solder 2, a signal terminal 3, a main terminal 4, a case 5, a lid 6, a wire 7, a wire 8, a sealing material 9, an adhesive 10, an insulating substrate 13, a heat dissipating material 14, and a base plate 15.
The insulating substrate 13 includes an insulating layer 11 and a conductor pattern 12a provided on the upper surface of the insulating layer 11.
A material of the insulating layer 11 is, for example, ceramic or resin.
The conductor pattern 12a is a pattern formed of, for example, copper, a copper alloy, aluminum, or an aluminum alloy.
The semiconductor chip 1a and the semiconductor chip 1b are joined onto the conductor pattern 12a by the solder 2.
The semiconductor chip 1a and the semiconductor chip 1b are disposed in the case 5 and sealed by the sealing material 9.
The case 5 is, for example, a resin case. The material of the case 5 is, for example, poly phenylene sulfide resin (PPS).
The sealing material 9 is, for example, a gel. The gel is, for example, a silicone gel.
The case 5 is attached with the lid 6.
The case 5 is bonded to the insulating substrate 13 with the adhesive 10.
The case 5 is attached with the signal terminal 3 and the main terminal 4. The main terminal 4 is a terminal for power. Although only one main terminal 4 is shown in the cross section shown in
The semiconductor chip 1a is, for example, a diode, and the semiconductor chip 1b is, for example, an insulated gate bipolar transistor (IGBT). The semiconductor chip 1b may be a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor device 100a may include a reverse-conducting IGBT (RC-IGBT), instead of including the semiconductor chip 1a being a diode and the semiconductor chip 1b being an IGBT. Each of the semiconductor chip 1a and the semiconductor chip 1b is, for example, a semiconductor chip using any one of a Si semiconductor, a SiC semiconductor, and a GaN semiconductor.
The main terminal 4 shown in
The lower surface of the insulating layer 11, that is, the lower surface of the insulating substrate 13 is in contact with the base plate 15 with interposition of the heat dissipating material 14. The base plate 15 is a metal plate. The base plate 15 is a plate of, for example, copper, a copper alloy, aluminum, or an aluminum alloy. The heat dissipating material 14 is, for example, grease or a heat dissipating sheet.
For example, the entire lower surface of the insulating substrate 13 is in contact with the base plate 15 with interposition of the heat dissipating material 14.
When the heat dissipating material 14 is a heat dissipating sheet, the heat dissipating sheet is not bonded to at least one of the insulating substrate 13 and the base plate 15.
In
The heat dissipating material 16 is, for example, grease or a heat dissipating sheet. The heat dissipating material 16 may have conductivity. When the heat dissipating material 16 has conductivity, the potential of the base plate 15 can be made equal to that of the radiator 17, and discharge between the base plate 15 and the radiator 17 can be suppressed.
Since the semiconductor device 100a is attached to the radiator 17 by the screws 18, the base plate 15 is sandwiched and supported from above and below by the case 5 and the radiator 17.
The insulating substrate 13 and the base plate 15 are not fixed to each other. That is, when the base plate 15 is thermally expanded during the operation of the semiconductor device 100a, the relative position in the in-plane direction between the lower surface of the insulating substrate 13 and the upper surface of the base plate 15 can be changed. The base plate 15 is in contact with the lower surface of the case 5 with interposition of the heat dissipating material 14. The base plate 15 is not fixed to the case 5. That is, when the base plate 15 is thermally expanded during the operation of the semiconductor device 100a, the relative position in the in-plane direction between the lower surface of the case 5 and the upper surface of the base plate 15 can be changed.
In the semiconductor device 100z, the insulating substrate 130 and the base plate 15 are fixed to each other. The linear expansion coefficient of the base plate 15 is larger than the linear expansion coefficient of the insulating layer 11. Therefore, when the temperature of the semiconductor device 100z rises, the base plate 15 deforms and protrudes toward the radiator 17 due to the difference in the expansion coefficient between the insulating substrate 13 and the base plate 15.
On the other hand, in the semiconductor device 100a of the present preferred embodiment, since the insulating substrate 13 and the base plate 15 are not fixed to each other, even when the temperature of the semiconductor device 100a rises, the base plate 15 does not protrude or is less likely to protrude toward the radiator 17. Therefore, the influence of the difference between the expansion coefficient of the insulating substrate 13 and the expansion coefficient of the base plate 15 is suppressed, and the pumping out of the heat dissipating material 16 is suppressed. Accordingly, decrease in heat dissipation can be suppressed.
The semiconductor device 100a may include an insulating substrate 130 instead of the insulating substrate 13. In this case, the lower surface of the insulating substrate 130, that is, the lower surface of the conductor pattern 12b provided on the lower surface of the insulating layer 11 is in contact with the base plate 15 with interposition of the heat dissipating material 14. Also in this case, since the insulating substrate 130 and the base plate 15 are not fixed to each other, even when the temperature of the semiconductor device 100a rises, the base plate 15 does not protrude or is less likely to protrude toward the radiator 17. Therefore, the influence of the difference between the expansion coefficient of the insulating substrate 130 and the expansion coefficient of the base plate 15 is suppressed, and the pumping out of the heat dissipating material 16 is suppressed. In order to prevent the insulating substrate 130 from protruding downward due to the difference in the linear expansion coefficient between the conductor pattern 12b and the insulating layer 11 and causing pumping out of the heat dissipating material 14 when the temperature of the semiconductor device 100a rises, the thickness of the conductor pattern 12b is preferably equal to or less than the thickness of the conductor pattern 12a.
Since a semiconductor chip using a wide band gap semiconductor operates at a higher temperature than a semiconductor chip using silicon, when at least one of the semiconductor chip 1a and the semiconductor chip 1b is a semiconductor chip using the wide band gap semiconductor, pumping out is more likely to occur in the semiconductor device 100z of the comparative example. In the semiconductor device 100a of the present preferred embodiment, since the insulating substrate 13 or the insulating substrate 130 and the base plate 15 are not fixed to each other, even when at least one of the semiconductor chip 1a and the semiconductor chip 1b is a semiconductor chip using a wide band gap semiconductor, pumping out can be suppressed, so that decrease in heat dissipation can be suppressed. Here, the wide band gap semiconductor is a semiconductor having a larger band gap than a silicon semiconductor, and is, for example, a SiC semiconductor or a GaN semiconductor.
The semiconductor device 100b is different from the semiconductor device 100a of the first preferred embodiment in that the base plate 15 is surrounded by the case 5 in plan view, and the inner side surface 50 of the case 5 faces the side surface 150 of the base plate 15. The semiconductor device 100b is similar to the semiconductor device 100a of the first preferred embodiment in other points.
The base plate 15 is smaller than the case 5 in plan view. There is an interval in the in-plane direction between the inner side surface 50 of the case 5 and the side surface 150 of the base plate 15. Since there is an interval in the in-plane direction between the inner side surface 50 of the case 5 and the side surface 150 of the base plate 15, even when the temperature of the base plate 15 rises and expands during the operation of the semiconductor device 100b, the contact between the base plate 15 and the case 5 can be avoided, or a force applied to the case 5 and the base plate 15 when the base plate 15 and the case 5 come into contact with each other can be suppressed.
Assuming that the temperature rise range of the base plate 15 is 125 K, when the base plate 15 is a copper plate, since the linear expansion coefficient of copper is 16.8 × 10-6/K, the base plate 15 expands by 100% × 16.8 × 10-6/K × 125 K = 0.21%. There has only to be an interval of 0.13% or more of the width W0 in the X direction of the base plate 15, with respect to the direction in a plane, in the X direction (see
The size of a general semiconductor module is 150 mm or less. Assuming that the size of the base plate 15 in plan view is 150 mm or less and the temperature rise width of the base plate 15 is 125 K, when the base plate 15 is a copper plate, since the linear expansion coefficient of copper is 16.8 × 10-6/K, the base plate 15 expands by 16.8 × 10-6/K × 125 K × 150 mm = 0.315 mm due to the temperature rise. Between the inner side surface 50 of the case 5 and the side surface 150 of the base plate 15, there has only to be an interval of 0.2 mm or more with respect to the in-plane direction, in the X direction being one direction in the plane and the direction opposite to the X direction, and there has only to be an interval of 0.2 mm or more with respect to the in-plane direction, in the Y direction in the plane orthogonal to the X direction and the direction opposite to the Y direction. With this configuration, even when the temperature of the base plate 15 rises by 125 K, the contact between the base plate 15 and the case 5 can be avoided, or a force applied to the case 5 and the base plate 15 when the base plate 15 and the case 5 come into contact with each other can be suppressed.
The semiconductor device of the present preferred embodiment may include the heat dissipating material 16 and the radiator 17 in addition to the semiconductor device 100b.
As shown in
In order to prevent the base plate 15 from coming into contact with the protrusion 51 when the base plate 15 expands, it is preferable that the tip of the protrusion 51 does not reach the depth of the groove 151, and it is preferable that there is a gap between the tip of the protrusion 51 and the depth of the groove 151 in the in-plane direction.
As shown in
Since the protrusion 51 at least partially enters the groove 151, the base plate 15 and the case 5 are integrated. Since the base plate 15 and the case 5 are integrated, the base plate 15, the insulating substrate 13, the semiconductor chip 1a, and the semiconductor chip 1b can be prevented from falling off from the case 5. Therefore, even when the semiconductor device 100c includes a plurality of insulating substrates 13, the semiconductor device 100c can be easily handled.
The semiconductor device of the present preferred embodiment may include the heat dissipating material 16 and the radiator 17 in addition to the semiconductor device 100c.
It should be noted that each preferred embodiment can be freely combined, and each preferred embodiment can be appropriately modified or omitted.
While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-000572 | Jan 2022 | JP | national |
