Patent Application
20130341711
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and particularly to a technique which is effectively applied to an UMOSFET (metal oxide semiconductor field effect transistor).
2. Background Art
On the background of global environmental protection, a reduction in the emission of carbon dioxide which is one of greenhouse gases has been demanded. For that reason, electric power saving of a wide variety of electronic devices has been increasingly required. Among those electronic devices, a requirement in railroad, automobile, and electric power fields which consume a large amount of power is strong, and the electric power saving of semiconductor power devices for controlling their electric powers has been encouraged. In order to reduce a power loss, a reduction in an on-resistance becomes a challenge for the power devices such as transistors or diodes. Under such circumstances, attention is paid to the power device using silicon carbide (SiC). SiC is a material indicative of a variety of polytypes, and 4H—SiC that is one of polytypes has a breakdown strength which is 10 times as large as Si mainly used at present. For that reason, in a variety of semiconductor devices, a thickness of adrift layer of 4H—SiC can be reduced to 1/10 if 4H—SiC has the same breakdown specification as that of Si. According to a Poisson equation, this means that a carrier concentration can be increased to 100 times. If a mobility is kept constant without depending on the carrier concentration, a resistance of the drift layer can be reduced by about double digits to triple digits. Further, in the case of a MOSFET, there is advantageous in that a switching loss is small in the inverter application. That is, the remarkable power saving can be expected as compared with the related art Si power device. Further, since a high-temperature operation can be physically conducted, a cooling system can be reduced, and can be downsized as an overall system. However, currently, a substrate price becomes a bottleneck, and a system of 4H—SiC is relatively expensive as compared with the system of Si. In the future, it is conceivable that since a chip unit price is decreased with a larger diameter of the substrate, and the cooling system can be reduced in the costs, the SiC power device becomes comprehensively predominant.
Under the above circumstances, the MOSFET has been developed as a switching element. The MOSFET can conduct normally-off operation in principle, and is convenient, and the application of the MOSFET over a wide range is expected. Since a high pressure resistance is demanded for the MOSFET, the vertical structures are adopted. The vertical structures have two types of a planar type using a wafer plane as a channel, and a trench type forming a trench, and using a side wall of the trench as the channel. Since the trench type MOSFET (UMOSFET) can be subjected to high integration, but has a plane direction dependency, there have been proposed a method of identifying the direction (for example, refer to JP-A-2009-187966), a trench forming method (for example, refer to JP-A-2009-289987), a method of reducing an electric field to be applied to a trench bottom (for example, refer to JP-A-2009-278067 and JP-A-2009-117593). However, attention needs to be paid to a method of forming a channel surface because in the MOSFET, a top surface of 10 to 100 nm order in depth forms the channel, and the performances such as the mobility and the reliability of a gate insulating film formed immediately over the channel are sensitive to a surface state. For that reason, surface processing is implemented immediately before the gate insulating film is formed. As a method of the surface processing, there is an epitaxial growth. The epitaxial growth is a technique of allowing an SiC film to grow, which is different from a method of removing a surface layer such as sacrificial oxidation or hydrogen etching. In particular, in the case of the UMOSFET, since a damage caused by the process is larger than that of the planar type because the channel surface is formed by dry etching, it is conceivable that the applied effect of the surface processing process is large. With the application of the surface processing method, an improvement in the performance of the SiC-MOSFET can be expected.
The present inventors have been engaged in research and development of the power devices, and have studied an improvement in the characteristics such as a reduction in the on-resistance of the above UMOSFET, and an improvement in the reliability of the gate insulating film. As means for improving the characteristics, the present inventors have studied the application of the epitaxial growth process, but there arise the following problems. A substrate used for the epitaxial growth process is mainly formed of a 4H—SiC, 4° off substrate at present. Therefore, if the trench is formed, a crystal plane is different from each other between a trench side wall and a wafer surface. For example, when a rectangular trench is formed on a generally used SiC substrate having a {0001} surface 4° off in a <11-20> direction as a main surface, there appear six surfaces in total including four side walls of the trench, a wafer main surface, and a trench bottom as illustrated in
According to the experimental results by the present inventors, because a growth rate of the epitaxial growth strongly depends on the crystal surface, it is difficult to conduct the epitaxial growth with a uniform thickness in the above trench structure. When the epitaxial growth is to be conducted in the UMOSFET, the film thickness unevenness induces the unevenness of the channel, and the insulation failure of a gate oxide film formed immediately over the channel, resulting in a problem that the yield is degraded.
In order to allow the epitaxial growth film to grow on the trench side wall with a uniform thickness, the channel is arranged in an optimum direction as a growth surface. For example, the trench is formed so that the channel surface becomes the {1-100} surface with respect to the SiC substrate having the {0001} surface 4° off in the <11-20> direction as the main surface. With the above configuration, the epitaxial growth with a uniform thickness can be conducted on the side wall where the {1-100} surface of the trench is exposed. As a result, the unevenness of the channel resistance and the insulation failure of the gate insulating film do not occur, and the yield is improved.
According to the present invention, a process likelihood in the epitaxial growth process of the semiconductor device is improved, thereby being capable of improving the yield.
Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
A configuration of a semiconductor device (UMOSFET) according to this embodiment will be described with reference to
As illustrated in
The semiconductor device described below is formed on a substrate in which an SiC epitaxially grown film (109) called “drift layer” is deposited on an SiC substrate (110). A gate electrode (101) illustrated in
The above semiconductor device is generally called “trench MOSFET” or “UMOSFET”, and a voltage to be applied to the gate electrode is controlled to control a channel resistance configuring a resistance value between the source electrode (107) and the drain electrode (108). In an extreme case, the channel resistance is remarkably increased to decrease a current between the source electrode (107) and the drain electrode (108) (off-operation). Conversely, the channel resistance is extremely decreased to increase the current between the source electrode (107) and the drain electrode (108) (on-operation). That is, a switch of a current between terminals of the source electrode (107) and the drain electrode (108) turns on/off, and is generally called “switching element” because of that characteristic. The UMOSFET is one configuration of the switching element. A DMOSFET (double diffused FET) is present as another configuration, and a description thereof will be omitted in this example.
The principle of the on-operation will be described. A positive voltage is applied to the drain electrode (108) while the source electrode is 0V. Therefore, a current flows from the drain electrode (108) toward the source electrode (107). A flow of electrons which are carriers is opposite to that of the current. When a positive voltage is applied to the gate electrode, a free electron layer called “channel” is formed on the epitaxial growth film (103) grown on the trench side wall. For that reason, a current that flown through the drain electrode (108), the substrate (110), and the drift layer (109) passes into the source electrode (107) through the n+ region (105) from the channel region. This is the principle of the on-operation. On the other hand, in the general MOSFET, no channel is formed when the gate electrode is 0V. Also, a current is cut off by a pn junction formed between the drift layer (109) and the p body region (104). This is the operation principle of the off operation. In general, a voltage value to be applied to the gate electrode which becomes a threshold value for opening or closing the channel is called “threshold voltage”. There are a variety of accurate definitions of the threshold voltage, but in this example, the threshold voltage is defined as the voltage for opening or closing the channel.
The basic operation is described above. In the present invention, the epitaxial growth layer (103) arranged between the p body region (104) and the gate insulating film (102) is arranged with a layer for recovering a damage of crystal due to dry etching for forming the trench, or ion implantation for forming the p body region (104). With this configuration, the channel mobility and the reliability are expected to be improved. That layer is arranged provided that the epitaxial thickness within the trench is kept uniform. In the related art epitaxial growth technique, it is difficult to epitaxially grow the layer with a uniform thickness on the trench inner wall, and a technique for controlling the growth is important. If the evenness is not kept, a degradation of the yield due to the unevenness of the channel resistance is problematic. Further, there arises such a problem that the gate oxide film becomes uneven in a post-process, resulting in a problem that the insulating film reliability is degraded. Therefore, in order to avoid those problems, it is important that the epitaxial film has an even thickness. The most importance for the uniform film growth is an epitaxial growth rate. It is needless to say that the growth rate depends on a growth condition such as a material gas quantity, and in order to grow the film with the even thickness, it is most important what a crystal plane on the trench side wall is. As described above, because the crystal plane different in principle is exposed in the UMOSFET, it is unavoidable that the growth rate is different in the respective planes. Under the circumstances, all of the planes used as the channel are configured by {1-100} surfaces that can be made identical with each other, and a termination portion of the cell is configured by a {11-20} surface, or a surface conforming to the {11-20} surface. With this configuration, the epitaxial growth with the even thickness can be conducted on the channel.
A second problem is that because the {11-20} surface is exposed in the termination portion of the cell, the thickness becomes uneven in that portion, and the above-mentioned problem becomes manifested. Under the circumstances, in order to avoid the problem, the gate electrode is arranged as illustrated in the figure, and the gate electrode is prevented from being formed in the termination portion. With this configuration, the semiconductor device with an excellent characteristic can be manufactured.
Subsequently, a method of manufacturing the semiconductor device according to this embodiment will be described with reference to
As illustrated in
A semiconductor region made of SiC is grown on the front surface of the SiC substrate (110) through the epitaxial growth method to form the n− drift layer (109). For example, 4H—SiC is epitaxially grown on the substrate (110) with a thickness of about 2 μm to 50 μm, using a source gas of, for example, SiH4, or Si2H6 as an Si source, or CH4, C2H6, and C3H8 as a C source. In this situation, nitrogen (N2) is contained in the source gas, to thereby introduce the n type impurities into the formed epitaxial film. The thickness and the impurity concentration of the drift layer (109) depend on a withstand design of the device and a designed value such as the resistance value. The n− drift layer (109) and the p body region (104) which will be described later configure the pn junction. Hence, the impurity concentrations of those semiconductor regions (104, 109) become factors for determining a width of a depletion layer of the pn junction. The impurity concentration of the n− drift layer (109) falls within a range of, for example, 1×1014 to 1×1018 cm−3. A laminated body of the SiC substrate (110) and the n− drift layer (109) may be regarded as the substrate.
Subsequently, the p body region (104) is partially formed on the front surface of the n− drift layer (109). More specifically, a photoresist film (111) is coated on the n− drift layer (109), and a pattern is exposed and transferred. Thereafter, development processing is conducted (photolithography). After the pattern has been drawn by using an electron beam, the development processing may be conducted. As a result, the region in which the p body region (104) is not formed is covered with the photoresist film (111). With the developed photoresist film (111) as a mask, p-type impurities are implanted into the n− drift layer (109), to thereby form the p body region (104). For example, an implantation depth of the impurities is, for example, about 1 μm. Also, the impurity concentration falls within a range of, for example, 1×1016 to 1×1019 cm−3. Also, for example, Al (aluminum) or B (boron) is used as the p type impurities. Since a resistance property of the photoresist film (111) may be short depending on an implantation energy or the amount of implantation of the impurities, for example, SiO2 may be used as a high resistant mask called “hard mask”. In this situation, a photoresist mask is coated on the high resistant mask, and a pattern is formed through the same process as that described above. Thereafter, SiO2 is etched through a technique such as a dry etching or a wet etching with the photoresist mask as the mask. With this processing, an SiO2 mask onto which a photoresist mask pattern has been transferred is completed, and the impurities are implanted from above this mask. Thereafter, the photoresist film (111) is removed by ashing, to thereby form the p body region (104) as illustrated in
Subsequently, the p+ region (106) is formed. Specifically, the photoresist film (111) is coated on the substrate, the pattern is exposed and transferred, and thereafter the development processing is conducted. As a result, the photoresist film (111) remains. With the developed photoresist film (111) as a mask, the p-type impurities are implanted into the n− drift layer (109), to thereby form the p+ region (106). For example, an implantation depth of the impurities is, for example, about 0.1 μm to 0.5 μm. The depth is determined by adjusting the implantation energy of the impurities. The impurity concentration is set to, for example, about 1×1018 to 1×1021 cm−3. Also, for example, Al (aluminum) or B (boron) is used as the p type impurities. Since a resistance property of the photoresist film (111) may be short depending on the implantation energy or the amount of implantation of the impurities, for example, SiO2 may be used as the “hard mask”. In this situation, a photoresist mask is coated on the high resistant mask, and a pattern is formed through the same process as that described above. Thereafter, SiO2 is etched through a technique such as a dry etching or a wet etching with the photoresist mask as the mask. With this processing, an SiO2 mask onto which a photoresist mask pattern has been transferred is completed, and the impurities are implanted from above this mask. Thereafter, the photoresist film (111) is removed by ashing, to thereby form the p+ body region (106). Also, when SiO2 is used as the hard mask, the photoresist film (111) is removed by wet etching of hydrofluoric acid after ashing.
Subsequently, the n+ region (105) is formed. Specifically, the photoresist film (111) is coated on the substrate, the pattern is exposed and transferred, and thereafter the development processing is conducted. As a result, the photoresist film (111) having an n+ region (105) formation region opened remains. With the developed photoresist film (111) as a mask, the n-type impurities are implanted into the p body region (104), to thereby form the n+ source region (105). For example, an implantation depth of the impurities is, for example, about 0.1 μm to 0.5 μm. With this processing, the n+ region (105) is formed on the front surface of the p body region (104). The impurity concentration falls within a range of, for example, 1×1018 to 1×1021 cm−3. Also, for example, N (nitrogen) or P (phosphorus) is used as the n type impurities. Since a resistance property of the photoresist film (111) may be short depending on the implantation energy or the amount of implantation of the impurities, for example, SiO2 may be used as the hard mask. In this situation, a photoresist mask is coated on the hard mask, and a pattern is formed through the same process as that described above. Thereafter, SiO2 is etched through a technique such as a dry etching or a wet etching with the photoresist mask as the mask. With this processing, an SiO2 mask onto which a photoresist mask pattern has been transferred is completed, and the impurities are implanted from above this mask.
Thereafter, the photoresist film (111) is removed by ashing, to thereby form the n+ source region (105).
The order of the wide variety of ion introduction (implantation) processing is not limited to the above processing. For example, the respective semiconductor regions (impurity regions 104, 105, and 106) can be formed at position indicated in
Then, for the purpose of recovering the crystalline disturbed through the above ion introduction (implantation) processing, and activating the introduced impurities, anneal processing (heat treatment) is conducted in an Ar or Ar/SiH4 atmosphere of, for example, about 1600 to 1800° C.
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, an interlayer insulating film that isolates the gate electrode from the source electrode is formed. Specifically, as illustrated in
Then, the source electrode is formed. Specifically, as illustrated in
Thereafter, a metal material such as nickel (Ni) is deposited on both of the front surface and the rear surface through the sputtering technique, and annealed at about 700 to 1000° C. With this processing, the silicide layer is formed on an opening portion of the contact hole and the rear surface. Thereafter, a metal not subjected to silicide, which remains on the interlayer insulating film, is completely removed by a mixture of sulfuric acid and oxygenated water. Thereafter, as illustrated in
With the above processing, the semiconductor device is completed as illustrated in
Through the above processing, the semiconductor device (UMOSFET) according to this embodiment is completed.
In the first embodiment, the center portion of the cell region (
In the first embodiment, the UMOSFET has been specifically described. The same effects are obtained even in a gate trench type IGBT (insulated gate bipolar transistor).
The semiconductor device described below is formed on the substrate in which the SiC epitaxially grown film (109) called “drift layer” is deposited on the SiC substrate (110). The gate electrode (101) illustrated in
A large difference form the first embodiment resides in that the impurity type of the substrate that grows the drift layer is opposite to the drift layer. In the case of the n channel type, the impurity type of the substrate is p-type, and in the p channel type, the impurity type of the substrate is n-type. The semiconductor device is generally called “trench gate type IGBT”, and the voltage to be applied to the gate electrode is so controlled as to control the channel resistance configuring the resistance value between the source electrode (107) and the drain electrode (108). In the case of the IGBT, the source electrode is precisely called “emitter”, and the drain electrode is called “collector”.
The basic manufacturing method is identical with that of the first embodiment. A difference from the first embodiment resides in the substrate forming the device, and the substrate and the drift layer having the same conduction type are formed in the UMOSFET. However, in the IGBT, the conduction type of the substrate is opposite to the conduction type of the drift layer.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-138317 | Jun 2012 | JP | national |
