Patent Grant
7064384
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-256774, filed on Sep. 2, 2002; the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device which has a trench gate type structure.
Semiconductor devices, such as power metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor), have been used for various kinds of fields including the field for electric power control. In these semiconductor devices, it is desired to increase the efficiency in order to meet the demand of saving of energy in recent years.
In order to satisfy the demand, it is effective to reduce the electrical conduction loss, i.e., “ON resistance” of the element. So far, reducing ON resistance has been sought by carrying out the miniaturization of the cell. Moreover, by adopting a “trench gate structure” as the element structure, the channel width has been made greater and the channel density has been increased sharply.
Currently, the further miniaturization of the trench gate structure is being carried out, and ON resistance of the element has come to be improved sharply. As an example which indicated the trench gate type semiconductor device where the channel density has been increased, Japanese Patent Laid-Open Publication No.2001-102579 can be mentioned which discloses a device where increase of the channel density and promotion of the degree modulation of conduction are compatible by adopting a ladder-like trench gate structure.
That is, this figure shows the cross-sectional structure near the gate of a trench gate type n channel type MOSFET. An n− type epitaxial region 6 and a p type base region 5 are formed on an n+ type substrate 7. Trenches are formed from the surface to the epitaxial layer 6, and are embedded with a gate oxide 3 and a gate electrode 1 to form an embedded gate structure. An insulating interlayer film 4 is provided appropriately on the embedded gate, and n type source regions 2 are formed around the trenches. Further, a drain region 8 is appropriately provided in the back side of the substrate 7.
By applying a predetermined bias voltage to the gate electrode 1, this MOSFET can form a channel region in the circumferences of the embedded trenches, and can carry out switching operation which changes the conduction state between the source region 2 and the drain regions 8 into “ON” state.
Now, in such a semiconductor device, in order to improve the efficiency of operation, it is important to reduce a “parasitic capacitance” as well as reducing the “ON resistance”, and to increase the operating speed.
For example, when performing inverter control, for example, combining two or more switching elements, if the operating speed of the elements is slow, it is necessary to set up a “dead time” which serves as “OFF” in all the switching elements that constitute an arm for a long time in order to prevent the penetration current of a rectification arm. As a result, a loss increases. On the other hand, if the operating speed becomes larger by reducing the parasitic capacitance of the switching elements, the “dead time” can be shortened and the loss can be reduced.
The parasitic capacitance of the semiconductor device illustrated in
First, the capacitance (Cgd) between the drain and the gate can be mentioned. This capacitance is produced in the region where the epitaxial region 6 and gate oxide 3 are in contact with. Next, the capacitance (Cds) between the drain and the source can be mentioned. This capacitance is produced in the p-n junction where the epitaxial region 6 and the base region 5 touch.
Moreover, the capacitance (Cgs) between the gate and the source can be mentioned. This capacitance is produced in the regions where the gate oxide 3 and the source region 2 touch, and where the gate oxide 3 and the base region 5 touch.
Since these capacitance constituents do loss to switching operation of the semiconductor device, they need to be reduced. In order to reduce the capacitance, it may be considered to make area of these contact parts smaller, or to promote depletion by lowering the carrier concentration of each semiconductor region, etc.
However, if these methods are employed, there will be a problem that it becomes difficult to juggle the “ON resistance” and the “parasitic capacitance”, or to juggle the “breakdown voltage” and the “parasitic capacitance” of the semiconductor device. Thus, an improvement of a total performance becomes difficult.
According to an embodiment of the invention, there is provided a semiconductor device comprising: a first main electrode; a second main electrode; a semiconductor base region of a first conductivity type; a gate electrode provided in a trench through an insulating film, the trench being formed to penetrate the semiconductor base region; and a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided under the semiconductor base region, a flow of a current between the first and second main electrodes when a voltage of a predetermined direction is applied between these electrodes being controllable in accordance with a voltage applied to the gate electrode, and a depleted region extending from a junction between the first and the second semiconductor regions reaching the trench.
According to other embodiment of the invention, there is provided a semiconductor device comprising: a first semiconductor region of a second conductivity type; a second semiconductor region of a first conductivity type provided on the first semiconductor region, a third semiconductor region of a second conductivity type provided on the second semiconductor region, a fourth semiconductor region of a first conductivity type provided on the third semiconductor region, a fifth semiconductor region of a second conductivity type provided on the fourth semiconductor region, a trench penetrating at least the third through fifth semiconductor regions, a bottom of the trench being provided within the second semiconductor region; and a gate electrode provided in the trench through an insulating film.
According to other embodiment of the invention, there is provided a semiconductor device comprising: a first semiconductor region of a second conductivity type; a second semiconductor region of a first conductivity type provided on the first semiconductor region, a third semiconductor region of a second conductivity type provided on the second semiconductor region, a fourth semiconductor region of a first conductivity type provided on the third semiconductor region, a fifth semiconductor region of a second conductivity type provided on the fourth semiconductor region, a trench penetrating at least the third through fifth semiconductor regions, a bottom of the trench being provided between an upper surface and a lower surface of the second semiconductor region; a sixth semiconductor region of a second conductivity type provided in contact with the bottom of the trench; and a gate electrode provided in the trench through an insulating film.
According to other embodiment of the invention, there is provided a semiconductor device comprising: a first semiconductor region of a second conductivity type; a semiconductor layer provided on the first semiconductor region and having a plurality of second semiconductor regions of a first conductivity type and a plurality of third semiconductor regions of a second conductivity type, the second and the third semiconductor regions being arranged alternately; a fourth semiconductor region of a first conductivity type provided on the semiconductor layer, a fifth semiconductor region of a second conductivity type provided on the fourth semiconductor region, a trench penetrating at least the fourth and the fifth semiconductor regions, a bottom of the trench being provided within the semiconductor layer; and a gate electrode provided in the trench through an insulating film.
The present invention will be understood more fully from the detailed description given here below and from the accompanying drawings of the embodiments of the invention. However, the drawings are not intended to imply limitation of the invention to a specific embodiment, but are for explanation and understanding only.
In the drawings:
Referring to drawings, some embodiments of the present invention will now be described in detail.
(First Embodiment)
That is, this figure expresses a trench gate type semiconductor device. In the case of this semiconductor device, a thin p type region 10 and a thin n type region 9 are inserted in this order between the n− type epitaxial region 6 and the p type base region 5 provided on the n+ type substrate 7. These p type region 10 and n type region 9 are substantially depleted by the p-n junction formed between them.
Hereafter, the effect acquired in this embodiment will be explained quantitatively.
First, the characteristic of the semiconductor device obtained when the concentrations of the n type region 9 and the p type region 10 are changed is explained.
Table 1 shows the relationship between the carrier concentrations Nd of the n type region 9 and the p type region 10, and the characteristics of the semiconductor device.
Here, “structure A” corresponds to the structure of this embodiment. The “structure A” is the structure where the n type region 9 and the p type region 10 are provided as shown in
On the other hand, as shown in
In both structures, the cell pitch is 1.05 micrometers, the width of the trench is 0.55 micrometers, and the depth of the trench is 2 micrometers. The carrier concentration of the p type base region 5 is set to 7×1016/cm3, and the carrier concentration of the epitaxial region 6 is set to 1.2×1016/cm3.
In Table 1, the breakdown voltage Vb is defined as the drain voltage Vd at the time of the drain current being 1 μA, on the condition that Vs=Vg=0V. The threshold (Vth) is defined as a voltage obtained when the drain current becomes 1 mA and the drain voltage Vd is 10V. The ON resistance (Ron) is defined as a resistance obtained when the drain current is 100 mA and the gate voltage is 10V. Furthermore, each capacitance value (Cout, Cgd, Cds, Cgd) is defined as a capacitance obtained when the drain voltage Vd is 0.05V and a modulation of 1 MHz is given. Moreover, Cout corresponds to (Cgd+Cds), and Cgg corresponds to (Cgd+Cgs).
From the Table 1, it can be seen that a big difference is not seen in the breakdown voltage and the threshold (Vth) between any of “structure A” and “structure B.” That is, even if the n type region 9 and the p type region 10 are provided, there is no tendency in the breakdown voltage and in the threshold to deteriorate.
On the other hand, with regard to the ON resistance (Ron), there is a tendency to become higher in the “structure A” rather than in the “structure B”. This tendency becomes more remarkable when the carrier concentration exceeds 1×1016/cm3.
On the other hand, the parasitic capacitance of “structure A” becomes generally lower rather than that of “structure B.” Especially, Cout which affects the switching characteristic of the semiconductor device becomes much lower in “structure A.” As a result, the CR multiplication value (Cout×Ron) of the ON resistance Ron and the capacitance Cout becomes lower in “structure A” than in “structure B.”
These graphs show that the CR multiplication value (Cout×Ron) of “structure A” becomes lower than the CR multiplication value of “structure B”, when carrier concentrations of the n type region 9 and the p type region 10 of the “structure A” are made lower than 2×1016/cm3. That is, it turns out that it is desirable to make the carrier concentrations of the n type region 9 and the p type region 10 lower than 2×1016/cm3 when it is especially required to lower the CR multiplication value.
Next, the parasitic capacitance will be explained.
In the range shown in Table 1, although both the Cgd and the Cds are lower than those of “structure B.” As seen in
Now, the formation of the depleted regions will be explained more concretely. When the extending distance W of the depleted region from the p-n junction can be expressed by the following formula:
W=(2εsVbi/qNd)1/2
where, εs is the permittivity of the semiconductor device, Vbi is the built-in potential, q is the electric charge, and Nd is the carrier concentration, respectively. When Vbi is 0.7V, the extending distances W of the depleted region are as the following:
That is, the distance of the depleted region extending to the n type region 9 and the p type region 10 becomes smaller as the carrier concentration increases. For example, when the thicknesses of the layer of the n type region 9 and the p type region 10 are 0.2 micrometers, respectively, if the carrier concentration is made lower than 1×1016/cm3, these regions can be depleted completely. However, if the carrier concentration is more than 1×1017/cm3, it becomes impossible for these regions to be depleted completely. Therefore, it is desirable to make the carrier concentrations of the n type region 9 and the p type region 10 low to some extent.
However, in an actual manufacture process, it is not easy to form the n type region 9 and the p type region 10 whose carrier concentrations are stably much less than those of the base region 5 and the epitaxial region 6 in many cases. Rather, it is easy for manufacture process to make the carrier concentrations of these regions close to the carrier concentration of the base region 5 or the epitaxial region 6.
Therefore, in order to obtain the semiconductor device whose parasitic capacitance component is especially low, it is desirable to make the carrier concentrations of the n type region 9 and the p type region 10 within the limits of 5×1015 through 3×1016/cm3.
Next, the condition of the location of the n type region 9 and the p type region 10 will be explained.
Table 2 shows the relationship between the locations of the n type region 9 and the p type region 10, and the characteristics of the semiconductor device.
Also, the “structure A” is the structure where the n type region 9 and the p type region 10 are provided as shown in
On the other hand, the “structure B” is the structure where the n type region 9 and the p type region 10 are not provided as shown in
In Table 2, the definition and the measurement conditions of the breakdown voltage Vb, Vth, Ron, Cout, Cgd, Cds and Cgg are the same as those of what were mentioned above about Table 1.
Since the product of (Cout×Ron) becomes the best when the junction part of these regions 9 and 10, i.e., p-n junction, is located at a position higher than the bottom of the trench gate by 0.1 micrometers, this position is defined as “0 micrometer” as the standard of “junction position”. The case where the p-n junction is lower than this standard is defined as “plus”, and the upper case is defined as “minus.”
On the other hand, the graph shows that the CR multiplication value is lower than that of “structure B” and the good characteristics are acquired when the position of the p-n junction shifts to the “minus” direction, i.e., to a higher position.
And,
An inversion channel region is formed in the semiconductor region of the circumference of the trench gate by applying a bias to the trench gate. However, as shown in
In contrast, as shown in
Furthermore, as shown in
As the result, the ON resistance falls to 10 ohms. This ON resistance is the same value as that of “structure” B, i.e., the case where the n type region 9 and the p type region 10 are not provided. That is, it turns out that the increase of the ON resistance produced by providing the p type region 10 can be completely cancelled.
As explained above, it is desirable to provide so that the p type region 10 may touch the trench gate throughout its thickness range from a viewpoint of the ON resistance.
On the other hand, with regard to the parasitic capacitance, the value lower than that of “structure B” is acquired when the position of the p-n junction is in the range from “plus 0.2 micrometers” to “minus 0.3 micrometers.” However, when the position of the p-n junction is “minus 0.3 micrometers”, Cout increases up to 466 which is close to the Cout of 493 of “structure B.” As shown in
That is, when it is especially required to reduce the parasitic capacitance, it is desirable to provide the n type region 9 and the p type region 10 in the position so that the bottom of the trench gate locates within the p type region 10.
And as shown in Table 2 and
Now, in an actual manufacture process, after forming the p type region 10 and the n type region 9, the opening of the trench is formed and the gate is formed in many cases. Since some “variation” arises in the depth of the trench in this trench opening process, it is safe to set the position of the p-n junction to the upper position rather than the standard position of 0 micrometer, as shown in
Here,
Thus, even when the trench is formed more shallowly than a preset value because of the “variation” in a formation process, the problem that the bottom of the trench does not reach the p type region 10 and the ON resistance Ron increases, as shown in
As explained referring to
In the above explanation, although the case where this embodiment is applied to MOSFET was mentioned as the examples, the present invention is not limited to these examples.
In this IGBT, the emitter electrode E is connected to the n type source (emitter) region 2, the p+ type collector region 12 is provided in the back side of the n type substrate 7, and the p+ type collector region 12 is connected to the collector electrode C.
Also in such IGBT, by providing the n type region 9 and the p type region 10 and by depleting these regions during operation, the parasitic capacitance can be reduced and the trench gate type semiconductor device which is excellent in the operating characteristic can be offered.
Although the semiconductor device in which one layer of the n type region 9 and one layer of the p type region 10 are provided is illustrated in
In the case of the example of
The number of the layers of the p type regions 9 and the n type regions 10 is not necessarily two as shown. That is, three or more layers of the p type regions and the n type regions of may be laminated by turns.
Thus, when two or more p type regions 9 and n type regions 10 are laminated, thickness of the each layer can be made thin. That is, the depleted region DP as shown in
(Second Embodiment)
Next, the semiconductor device where the current path is kept by providing the n type region in the circumference of the trench gate and the parasitic capacitance is reduced while controlling the increase of the ON resistance will be explained as a second embodiment of the invention.
In this example, the p type region 10 is provided apart from the trench gate, and the n type region 11 is provided among these. Then, as illustrated by the arrows in this figure, the path of channel current will be kept. That is, according to this embodiment, the increase of the ON resistance by the p type region 10 which was mentioned above about
And the depleted region is extended from the p-n junction formed between the p type region 10, and the n type regions 9 and 11 which adjoin the p type region 10. Since the depleted region makes the circumference of the trench gate depleted as shown in
In addition, as a manufacturing method of the semiconductor device of this example, the following methods can be used, for example.
First, the method of diffusing the n type impurities from the inner wall of the trench can be mentioned as the first method. That is, after forming the p type region 10, the n type region 9 and the p type base region 5, the opening of the trench is carried out. Then, the n type region 11 can be formed by introducing the n type impurity into the surrounding of the semiconductor region from the inner wall of the trench.
On the other hand, the method of forming by introducing impurities alternatively can be mentioned as the second method. That is, the p type region 10 which is expressed in
In this example, the p type region 10 is in contact with the side of the trench gate, but it is not in contact with the bottom of the trench gate, and the n type region 11 is provided instead.
By applying the gate bias, the inversion channel is also formed in the p type region 10 in contact with the trench gate, and the current path is formed. Such an inversion channel is formed in the region in contact with the side and the bottom of the trench gate, and does not reach the region separated down from the bottom of the trench gate.
On the other hand, in the lower region of the trench with which this inversion channel does not reach, the current path can be kept by providing the n type region 11 and the increase of the ON resistance can be certainly prevented in this embodiment.
On the other hand, as shown in
In this example, a plurality of the n type regions 9 and a plurality of the p type regions 10 are arranged by turns in the horizontal directions which are perpendicular to the depth direction of the trench gate.
As shown in
In these structures of the example, the sizes and the carrier concentrations of the n type regions 9 and the p type regions 10 are set so that they may be appropriately depleted by the p-n junction formed therebetween.
For example, as mentioned above about the first embodiment, when the carrier concentrations of the n type regions 9 and the p type regions 10 are 1×1016/m3, respectively, the region of 0.3 micrometers from the p-n junction is depleted at zero bias condition. Therefore, if the size along the horizontal direction (it is a direction perpendicular to the depth direction of the trench) of the n type regions 9 and the p type regions 10 is 0.6 micrometers or less, the n type regions 9 and the p type regions 10 will be successfully depleted by the p-n junction therebetween.
Similarly, when the carrier concentrations of the n type regions 9 and the p type regions 10 are 1×1017 cm3, respectively, the region of 0.11 micrometers from the p-n junction is depleted at zero bias condition. Therefore, if the size along the horizontal direction of the n type regions 9 and the p type regions 10 is 0.2 micrometers or less, the n type regions 9 and the p type regions 10 will be depleted by the p-n junction therebetween.
Thus, in this example, it is easy to make these regions depleted completely by appropriately setting the size along the horizontal direction of the n type regions 9 and the p type regions 10 according to the carrier concentrations. And as mentioned above about the first embodiment, the parasitic capacitance can be reduced effectively by covering the trench gate with the depleted region. In order to reduce the parasitic capacitance effectively, as mentioned above about the first embodiment, it is desirable to provide so that the bottom of the trench gate may be located between the upper surface and the lower surface of the n type region 9 and the p type region 10.
However, if the carrier concentrations of the n type region 9 and the p type region 10 exceed 3×1017/cm3, the size along the horizontal direction of the n type regions 9 and the p type regions 10 must be set to 0.1 micrometers or less in order to make these regions depleted completely. It is often not easy in a practical manufacture process to form the n type regions 9 and the p type regions 10 of such detailed size by turns on the n type epitaxial region 6. Therefore, in this example, it is desirable to set the maximum of the carrier concentrations of the n type regions 9 and the p type regions 10 to about 3×1017/cm3.
On the other hand, since the n type region 9 connects the base region 5 and the epitaxial region 6 along the depth direction of the trench in this example, the path of channel current is also kept. As a result, the ON resistance (Ron) can be reduced.
Moreover, as shown in
The planar arranging pattern of the n type regions 9 and the p type regions 10 in the invention is not limited to what are expressed in
In addition, this embodiment can be applied to not only MOSFET but also to IGBT which is shown in
Thus, by applying an appropriate input signal to the input terminals 101 and 102, the LED 110 will emit a light. The emitted light is received by the array of photodiodes 120, where the received light is converted into an electric signal. The signal is supplied to the control circuit 130. When the control circuit 130 receives the signal, the circuit 130 supplies a gate activating signal to the gates of the MOSFETs 140. Thus, the MOSFETs 140 is turned on, and the output terminals 103 and 104 are connected.
In the case of such a photo-relay, it is required that the MOSFETs 140 have a low resistance at the on-state while having a high impedance at the off-state. In order to satisfy such requisitions, it is important to reduce the output capacitance Cout (=Cgd+Cds) and to reduce the on-resistance Ron while keeping the breakdown voltage high.
According to the invention, it becomes possible to reduce the output capacitance Cout and to reduce the on-resistance Ron while keeping the breakdown voltage high. Thus, the photo-relay exemplarily shown in
Heretofore, some embodiments of the present invention have been explained, referring to the examples. However, the present invention is not limited to these specific examples.
For example, in
In addition, about the structure of the semiconductor device of the present invention and the concrete composition, such as the materials, impurities, conduction types, thicknesses, sizes, and form of each element which constitutes the semiconductor device of the present invention, may be appropriately selected by those skilled in the art with the known techniques to carry out the invention as taught in the specification and obtain equivalent effects and all these transformations are included within the scope of the invention.
While the present invention has been disclosed in terms of the embodiment in order to facilitate better understanding thereof, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modification to the shown embodiments which can be embodied without departing from the principle of the invention as set forth in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-256774 | Sep 2002 | JP | national |
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| 5378914 | Ohzu et al. | Jan 1995 | A |
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| Number | Date | Country |
|---|---|---|
| 2002-26324 | Jan 2002 | JP |
| 2002-94061 | Mar 2002 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20040094798 A1 | May 2004 | US |
