Patent Application
20230231023
This application is based on and claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2022-0047647 filed on Apr. 18, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
Example embodiments of the disclosure relate to a semiconductor device.
As the demand for high performance, high speed, and/or multifunctionality of a semiconductor device has increased, integration density of a semiconductor device has also increased. In manufacturing a semiconductor device having a fine pattern corresponding to the trend of high integration of the semiconductor device, it has been necessary to implement patterns having a fine width or a fine spacing. Also, to address the limitations of operation properties due to the size reduction of a planar metal oxide semiconductor FET (MOSFET), there have been attempts to develop a semiconductor device including a FinFET having a three-dimensional channel structure.
An example embodiment of the disclosure includes a semiconductor device having improved electrical properties and improved productivity.
In accordance with an aspect of the disclosure, a semiconductor device includes a substrate; active regions extending in a first horizontal direction on the substrate, wherein the active regions include a first active region and a second active region spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a third active region and a fourth active region spaced apart from each other in the second horizontal direction; gate structures including a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, wherein the first gate structure and the second gate structure intersect the first active region and the second active region and are spaced apart from each other in the first horizontal direction, and wherein the third gate structure and the fourth gate structure intersect the third active region and the fourth active region and are spaced apart from each other in the first horizontal direction; source/drain regions including a first source/drain region on the first active region between the first gate structure and the second gate structure, a second source/drain region on the second active region between the first gate structure and the second gate structure, a third source/drain region on the third active region between the third gate structure and the fourth gate structure, and a fourth source/drain region on the fourth active region between the third gate structure and the fourth gate structure; contact plugs including a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, wherein a first length in a vertical direction of the first isolation insulating pattern is smaller than a second length in the vertical direction of the second isolation insulating pattern, wherein the vertical direction is perpendicular to an upper surface of the substrate.
In accordance with an aspect of the disclosure, a semiconductor device includes a substrate; active regions extending in a first horizontal direction on the substrate, wherein the active regions include a first active region and a second active region spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a third active region and a fourth active region spaced apart from each other in the second horizontal direction; gate structures including a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, wherein the first gate structure and the second gate structure intersect the first active region and the second active region and are spaced apart from each other, and wherein the third gate structure and the fourth gate structure intersect the third active region and the fourth active region and are spaced apart from each other; source/drain regions including a first source/drain region on the first active region between the first gate structure and the second gate structure, a second source/drain region on the second active region between the first gate structure and the second gate structure, a third source/drain region on the third active region between the third gate structure and the fourth gate structure, and a fourth source/drain region on the fourth active region between the third gate structure and the fourth gate structure; contact plugs including a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, wherein the first isolation insulating pattern is spaced apart from the first source/drain region and the second source/drain region, and wherein the second isolation insulating pattern contacts the third source/drain region and the fourth source/drain region.
In accordance with an aspect of the disclosure, a semiconductor device includes a substrate; active regions extending in a first horizontal direction on the substrate, wherein the active regions include a first active region, a second active region, a third active region, and a fourth active region spaced apart from each other; source/drain regions including a first source/drain region on the first active region, a second source/drain region on the second active region, a third source/drain region on the third active region, and a fourth source/drain region on the fourth active region; contact plugs including a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, wherein the first isolation insulating pattern has a side surface profile different from a side surface profile of the second isolation insulating pattern.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following detailed description, taken in combination with the accompanying drawings, in which:
Hereinafter, embodiments of the disclosure will be described as follows with reference to the accompanying drawings.
It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout.
Spatially relative terms, such as “over,” “above,” “on,” “upper,” “below,” “under,” “beneath,” “lower,” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
For the sake of brevity, conventional elements to semiconductor devices may or may not be described in detail herein for brevity purposes.
Referring to
In an example embodiment, in the semiconductor device 100, the active regions 105 may have a fin structure, and the gate electrode 165 may be disposed between the active regions 105 and the channel layers 140, between the channel layers 140, and in an upper portion of the channel layers 140. Accordingly, the semiconductor device 100 may be configured as a transistor having a multi-bridge channel FET (MBCFET™) structure, which may be a gate-all-around (GAA) field effect transistor formed by the channel layers 140, the source/drain regions 150, and the gate structures 160.
However, differently from the aforementioned example embodiments, the semiconductor device 100 may be implemented as a fin-type field effect transistor (FinFET) in which the active regions 105 may have a fin structure, the channel layers 140 may not be included, and a physical channel region of the transistor may be formed in an upper region of each of the active regions 105 intersecting the gate electrode 165. In this case, the gate electrode 165 may extend to cover the upper and side surfaces of each of the active regions 105.
The substrate 101 may have an upper surface extending in the x-direction and they direction. The substrate 101 may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like.
The active regions 105 may be disposed to extend in a direction parallel to the upper surface of the substrate 101, that is, for example, in the x direction. The active regions 105 may be spaced apart from each other in the y direction and disposed in parallel to each other (see, e.g.,
In an example embodiment, the active regions 105 may include first to fourth active regions 105a and 105b, 105c, and 105d. Each of the first active region 105a and the second active region 105b may have a line shape or a bar shape extending in the first horizontal direction (e.g., the x direction). The first active region 105a and the second active region 105b may be spaced apart from each other in a second horizontal direction (e.g., the y direction) and may extend in parallel to each other. Each of the third active region 105c and the fourth active region 105d may have a line shape or a bar shape extending in the first horizontal direction (e.g., the x direction). The third active region 105c and the fourth active region 105d may be spaced apart from each other in the second horizontal direction (e.g., the y direction) and may extend in parallel to each other.
The device isolation layers 107 may define active regions 105 in the substrate 101. The device isolation layers 107 may be disposed between adjacent ones of the active regions 105. The device isolation layers 107 may have upper portions on a level lower than a level of the upper portions of the active regions 105. Accordingly, the device isolation layers 107 may partially expose the upper portions of the active regions 105. In an example embodiment, the device isolation layers 107 may have a curved upper surface having a level increasing toward the active regions 105, but an example embodiment thereof is not limited thereto. The device isolation layers 107 may be formed by, for example, a shallow trench isolation (STI) process. The device isolation layers 107 may be formed of an insulating material. The device isolation layers 107 may be, for example, oxide, nitride, or a combination thereof.
As illustrated in
The source/drain regions 150 may be disposed on the active regions 105 on at least one side of the channel layers 140. The source/drain regions 150 may be disposed to cover upper surfaces of the active regions 105 on a side surface of each of the channel layers 140 and on a lower end of the source/drain regions 150. In other words, the source/drain regions 150 may be disposed to cover upper surfaces of the active regions 105 and side surfaces of the channel layers 140. The source/drain regions 150 may be in contact with the channel layers 140. The source/drain regions 150 may be partially recessed into the upper portions of the active regions 105, but in example embodiments, the presence of the recess and the depth of the recess may be varied. The source/drain regions 150 may be a semiconductor layer including silicon (Si), and may include an epitaxial layer.
Each of the source/drain regions 150 may include impurities of different types and/or concentrations.
In an example embodiment, the source/drain regions 150 may include a first source/drain region 150a disposed on the first active region 105a, a second source/drain region 150b disposed on the second active region 105b, a third source/drain region 150c disposed on the third active region 105c, and a fourth source/drain region 150d disposed on the fourth active region 105d.
The gate structures 160 may intersect the active regions 105 and the channel layers 140 when viewed in a plan view, and may extend in one direction, that is, for example, they direction. The gate structures 160 may be spaced apart from each other. Channel regions of transistors may be formed in the active regions 105 and/or the channel layers 140 intersecting the gate structures 160.
Each of the gate structures 160 may include a gate dielectric layer 162, a gate electrode 165, a spacer structure 164, and a capping layer 166. The gate structures 160 may be in contact with the channel layers 140 between the channel layers 140.
The gate dielectric layer 162 may be disposed between each of the active regions 105 and the gate electrode 165 and between the channel layers 140 and the gate electrode 165, and may cover at least a portion of the surfaces of the gate electrode 165. For example, the gate dielectric layer 162 may be disposed to surround the entirety of surfaces of the gate electrode 165 other than the uppermost upper surface of the gate electrode 165. The gate dielectric layer 162 may extend to a region between the gate electrode 165 and the spacer structure 164, but an example embodiment thereof is not limited thereto. The gate dielectric layer 162 may include an oxide, nitride, or high-k material. The high-k material may refer to a dielectric material having a dielectric constant higher than that of a silicon oxide layer (SiO2). The high-k material may refer to a dielectric material having a dielectric constant higher than that of a silicon oxide layer (SiO2). The high dielectric constant material may be one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3). In example embodiments, the gate dielectric layer 162 may include multiple layers.
The gate electrode 165 may fill a gap between the channel layers 140 on the active regions 105 and may extend to an upper portion of the channel layers 140. The gate electrode 165 may be spaced apart from the channel layers 140 by the gate dielectric layer 162. The gate electrode 165 may include a conductive material, such as, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and/or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. In example embodiments, the gate electrode 165 may include multiple layers, two or more layers. Depending on the configuration of the semiconductor device 100, the gate electrode 165 may be isolated by a separator between at least a portion of the transistors adjacent to each other. The gate electrode 165 may include different materials depending on transistor regions.
The spacer structure 164 may be disposed on both sidewalls of the gate electrode 165 and may extend in the z-direction perpendicular to the upper surface of the substrate 101. The spacer structures 164 may include a portion in which a width of the upper portion is smaller than a width of the lower portion. The spacer structure 164 may include a curved upper surface, curved toward the substrate 101. However, the shape of the spacer structure 164 may be varied in example embodiments. The spacer structure 164 may insulate the source/drain regions 150 from the gate electrode 165. The spacer structure 164 may include multiple layers in example embodiments. The spacer structure 164 may be formed of oxide, nitride, and oxynitride.
The capping layer 166 may be disposed on the gate electrode 165. The capping layer 166 may be a structure for protecting the gate electrode 165 from etching in a subsequent process after forming the gate electrode 165. The capping layer 166 may be a structure supporting the contact plugs 170 to be self-aligned during the process of forming a contact plug. However, the example embodiment of the capping layer 166 is not limited thereto.
The capping layer 166 may be disposed on the gate electrode 165 and the spacer structure 164, and at least a portion of the lower surface thereof may be surrounded by the gate electrode 165 and the spacer structure 164. In an example embodiment, the capping layer 166 may include a lower surface having a curved shape, convexly curved toward the substrate 101. The capping layer 166 may include silicon nitride or a silicon nitride-based insulating material.
In an example embodiment, the gate structures 160 may include first and second gate structures 160a and 160b intersecting the first and second active regions 105a and 105b, spaced apart from each other, and extending in parallel to each other. The gate structures 160 may further include third and fourth gate structures 160c and 160d intersecting the third and fourth active regions 105c and 105d, spaced apart from each other, and extending in parallel to each other.
In an example embodiment, referring to
In an example embodiment, the semiconductor device 100 may further include internal spacer layers disposed in parallel to the gate electrode 165 between the channel layers 140. The internal spacer layers may be disposed on the same level as a level of the channel layers 140. The gate electrode 165 disposed below the uppermost portion of the channel layers 140 may be spaced apart from the source/drain regions 150 by the internal spacer layers and may be electrically isolated from the source/drain regions 150. The internal spacer layers may have a shape in which side surfaces opposing the gate electrode 165 have a rounded shape, rounded inwardly toward the gate electrode 165, but an example embodiment thereof is not limited thereto. The internal spacer layers may be formed of oxide, nitride, or oxynitride, and may be formed as a low-k film in particular. According to an example embodiment, as illustrated in
The contact plugs 170 may penetrate through interlayer insulating layer 190 and may be connected to the source/drain regions 150. The contact plugs 170 may apply electrical signals to the source/drain regions 150.
Each of the contact plugs 170 may have an inclined side surface of which a width decreases in a direction toward the substrate 101 depending on an aspect ratio, but an example embodiment thereof is not limited thereto. Each of the contact plugs 170 may be recessed from the source/drain regions 150 by a predetermined depth. However, in example embodiments, the contact plugs 170 may be in contact with the upper surfaces of the source/drain regions 150 without being recessed into the source/drain regions 150.
The contact plugs 170 may extend toward the source/drain regions 150 between the adjacent gate structures 160 and may be in contact with the source/drain regions 150.
In an example embodiment, the contact plugs 170 may be configured as self-aligning contacts (SAC) aligned by the gate structures 160. In this case, the contact plugs 170 may be aligned by the capping layer 166 of the adjacent gate structures 160. Alternatively, the contact plugs 170 may be formed using a separate mask.
The contact plugs 170 may include a plug layer 171 and a barrier layer 172. The plug layer 171 may include metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and/or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), for example. The barrier layer 172 may conformally cover side surfaces and a bottom surface of the plug layer 171. The barrier layer 172 may include, for example, a metal nitride such as a titanium nitride layer (TiN), a tantalum nitride layer (TaN), or a tungsten nitride layer (WN). The barrier layer 172 may allow the plug layer 171 and the isolation insulating patterns 180 to be apart from each other. The barrier layer 172 may extend along one side surface of the isolation insulating patterns 180 between the plug layer 171 and the isolation insulating patterns 180.
In an example embodiment, the contact plugs 170 may include a first contact plug 170a connected to the first source/drain region 150a, a second contact plug 170b connected to the second source/drain region 150b, a third contact plug 170c connected to the third source/drain region 150c, and a fourth contact plug 170d connected to the fourth source/drain region 150d. The first to fourth contact plugs 170a, 170b, 170c, and 170d may be spaced apart from each other.
Each of the isolation insulating patterns 180 may isolate contact plugs 170 adjacent to each other in one direction (e.g., they direction as shown in
The isolation insulating patterns 180 may include an insulating material such as oxide, nitride, or carbide, and may include, for example, silicon nitride. In an example embodiment, each of the isolation insulating patterns 180 may be a single insulating material layer, but an example embodiment thereof is not limited thereto, and the isolation insulating patterns 180 may have a multilayer structure.
In an example embodiment, the isolation insulating patterns 180 may include a first isolation insulating pattern 181 isolating the first contact plug 170a from the second contact plug 170b, and a second isolation insulating pattern 182 isolating the third contact plug 170c from the fourth contact plug 170d. The first isolation insulating pattern 181 may be in contact with each of the first and second contact plugs 170a and 170b between the first and second contact plugs 170a and 170b, and the second isolation insulating pattern 182 may be in contact with the third and fourth contact plugs 170c and 170d between the third and fourth contact plugs 170c and 170d, respectively.
In an example embodiment, side surfaces of the first and second isolation insulating patterns 181 and 182 may be in contact with the gate structures 160 in a first horizontal direction (e.g., the x direction), and may be in contact with the contact plugs 170 in the second horizontal direction (e.g., a y direction).
A side surface of the first isolation insulating pattern 181 and a side surface of the second isolation insulating pattern 182 may have different shapes.
In an example embodiment, the first isolation insulating pattern 181 may have an inclined side surface of which a width may decrease in a direction toward the substrate 101. The side surface of the first isolation insulating pattern 181 may have a plurality of side surfaces including a first side surface 181S1 having a first slope in the first horizontal direction and a second side surface 181S2 having a second slope in the first horizontal direction greater than the first slope. For example, the first side surface 181S1 and the second side surface 181S2 may have different slopes. A side surface of the first isolation insulating pattern 181 may have a third side surface 181S3 having a third slope in the second horizontal direction, as illustrated in
In an example embodiment, referring to
In an example embodiment, a side surface of the second isolation insulating pattern 182 may have a side surface 182S having a fourth slope as illustrated in
In an example embodiment, the third and fourth contact plugs 170a and 170b may have a width decreasing toward the substrate 101 or may have a constant width, in the second horizontal direction (e.g., the y direction).
The first and second isolation insulating patterns 181 and 182 may have different side surface profiles as the first and second isolation insulating patterns 181 and 182 may be formed by different etching processes. For example, the first isolation insulating pattern 181 may be a structure formed by selectively etching the interlayer insulating layer 190 with respect to the adjacent gate structures 160 under a specific etching condition, and the second isolation insulating pattern 182 may be a structure formed by etching without an etching selectivity.
The first isolation insulating pattern 181 may extend by penetrating through a portion of the interlayer insulating layer 190 disposed between the first and second gate structures 160a and 160b. The first isolation insulating pattern 181 may be disposed on the device isolation layers 107 between the first and second active regions 105a and 105b. The second isolation insulating pattern 182 may extend by penetrating through a portion of the interlayer insulating layer 190 disposed between the third and fourth gate structures 160c and 160d. The second isolation insulating pattern 182 may be disposed on the device isolation layers 107 between the third and fourth active regions 105c and 105d.
Referring to
The average width and/or average planar area of the first isolation insulating pattern 181 may be smaller than the average width and/or average planar area of the second isolation insulating pattern 182. In example embodiments, “average width” may refer to an average value of widths at each level of a corresponding component, and “average planar area” may refer to an average value of planar areas at each level of a corresponding component.
The first isolation insulating pattern 181 may be spaced apart from the source/drain regions 150 and/or the device isolation layers 107. The second isolation insulating pattern 182 may be disposed to be in contact with the source/drain regions 150 and/or the device isolation layers 107. This is because the second isolation insulating pattern 182 may be configured as an insulating pattern extending by a depth greater than that of the first isolation insulating pattern 181 and penetrating through at least a portion of the source/drain regions 150 and/or the device isolation layers 107.
In an example embodiment, the first isolation insulating pattern 181 may be spaced apart from the spacer structure 164, and the second isolation insulating pattern 182 may be in contact with the spacer structure 164. This is because the second isolation insulating pattern 182 may be configured as an insulating pattern having a width greater than a width of the first isolation insulating pattern 181 and formed in an opening penetrating through at least a portion of the spacer structure 164 together with the interlayer insulating layer 190.
In an example embodiment, the first and second isolation insulating patterns 181 and 182 may include the same insulating material. However, in example embodiments, the first and second isolation insulating patterns 181 and 182 may include different materials. This may be because the first and second isolation insulating patterns 181 and 182 may be formed through different processes.
As the first isolation insulating patterns 181 are formed by an etching process having an etch selectivity, the contact plugs 170 may be isolated without affecting electrical properties of the transistors including the gate structures 160 and the source/drain regions 150. As the second isolation insulating patterns 182 are formed by an etching process having no etch selectivity, the second isolation insulating patterns 182 may extend by a relatively deep depth, thereby preventing leakage current caused by contact between the contact plugs 170 adjacent to each other. In the semiconductor device 100 according to the example embodiments, since the first and second isolation insulating patterns 181 and 182, two types of isolation insulating patterns, are selectively disposed for each region, the semiconductor device 100 having improved electrical properties and productivity may be provided.
The interlayer insulating layer 190 may cover the source/drain regions 150 and the gate structures 160, and may cover the device isolation layers 107. The interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low-k material.
In an example embodiment, the semiconductor device 100 may further include an insulating liner 191 covering a lower surface of the interlayer insulating layer 190. The insulating liner 191 may include a material different from that of the interlayer insulating layer, such as, for example, silicon nitride or a silicon nitride-based insulating material. The insulating liner 191 may be disposed between the device isolation layers 107 and the interlayer insulating layer 190 and may extend to surfaces of the source/drain regions 150 not in contact with the contact plugs 170. Also, the insulating liner 191 may extend to side surfaces of the gate structures 160.
In an example embodiment, a lower surface of the capping layer 166 may cover the gate electrode 165, the spacer structure 164, and the insulating liner 191 extending to side surfaces of the spacer structure 164.
Referring to
The contact plugs 170′ may have a relatively large width in the second horizontal direction (e.g., the y direction). In an example embodiment, the first and second contact plugs 170a′ and 170b′ may be in contact with the third side surface 181S3 of the first isolation insulating pattern 181 in the second horizontal direction. The first isolation insulating pattern 181 may be spaced apart from the first and second source/drain regions 150a and 150b. Each of the first and second contact plugs 170a′ and 170b′ may include extension portions 170a_P and 170b_P extending to a space between the first and second source/drain regions 150a and 150b and first isolation insulating pattern 181. The extension portions 170a_P and 170b_P may cover a lower end of the third side surface 181S3 or a portion of a lower surface of the first isolation insulating pattern 181. However, the extension portions 170a_P and 170b_P of the first and second contact plugs 170a′ and 170b′ may be spaced apart from each other.
In an example embodiment, the third and fourth contact plugs 170c′ and 170d′ may be in contact with the second isolation insulating pattern 182 in the second horizontal direction.
The second isolation insulating pattern 182 may be in contact with the third and fourth source/drain regions 150c and 150d. Differently from the first and second contact plugs 170a′ and 170b′, the third and fourth contact plugs 170c′ and 170d′ may not include extension portions. This is because there may be no space between the source/drain regions 150 and the second isolation insulating patterns 182 as the second isolation insulating patterns 182 in contact with the source/drain regions 150 have a relatively great width and great depth as compared to the first isolation insulating pattern 181.
The contact plugs 170′ according to the example embodiments may have a structure formed through, for example, a wet etching process. When an opening having a relatively larger width (defined in the second horizontal direction) as compared to the example in
Referring to
The third length L3 of the second isolation insulating pattern 182′ in the z direction may be greater than the first length L1 of the first isolation insulating pattern 181 in the z direction. The third length L3 may be greater than the second length L2 of the second isolation insulating pattern 182 in
Referring to
The second isolation insulating pattern 182″ may be in contact with the gate electrode 165. A portion of a side surface of the second isolation insulating pattern 182″ may be in contact with the gate electrode 165 of the gate structures 160 and with the capping layer 166. This may be because the second isolation insulating pattern 182″ is formed in the opening having a relatively large width as compared to
Referring to
The active regions 105 may include fifth and sixth active regions 105e and 105f extending in a first horizontal direction, spaced apart from each other in a second horizontal direction, and extending in parallel to each other. The source/drain regions 150 may include a fifth source/drain region 150e disposed on the fifth active region 105e and a sixth source/drain region 150f disposed on the sixth active region 105f. The contact plugs 170 may include a fifth contact plug 170e connected to a fifth source/drain region 150e and a sixth contact plug connected to a sixth source/drain region 150f between the gate structures 160 adjacent to each other.
The third isolation insulating pattern 183 may isolate the fifth and sixth contact plugs 170e and 170f. The third isolation insulating pattern 183 may be an insulating pattern in which an insulating material is filled in a line-shaped trench. The third isolation insulating pattern 183 may extend in the first horizontal direction parallel to the active regions 105.
The third isolation insulating pattern 183 may penetrate through a plurality of gate structures 160 adjacent to each other (e.g., a plurality of adjacent gate structures). Accordingly, the gate structures 160 may include first isolation gate structures 160S1 and second isolation gate structures 160S2 spaced apart from the first isolation gate structures 160S1 in the second horizontal direction by the third isolation insulating pattern 183.
The third isolation insulating pattern 183 may include the same material as that of the second isolation insulating pattern 182 (see
In the semiconductor device 100d according to an example embodiment, the isolation insulating patterns 180 may further include the third isolation insulating pattern 183 together with the first and second isolation insulating patterns 181 and 182 in
Referring to
The fourth isolation insulating pattern 184 may isolate the seventh and eighth contact plugs 170g and 170h adjacent to each other.
The fourth isolation insulating pattern 184 may be configured as an insulating pattern in which a dam-shaped opening surrounding the closed space is filled with an insulating material to allow a specific closed space to be distinct.
In an example embodiment, the fourth isolation insulating pattern 184 may surround a plurality of active regions 105 adjacent to each other among the active regions 105 (e.g., a plurality of adjacent active regions) and a plurality of gate structures 160 intersecting the plurality of active regions 105 among the gate structures 160. In an example embodiment, the number of the plurality of active regions 105 may be two and the number of the plurality of gate structures 160 may be four, but the number of the plurality of active regions 105 and the number of the plurality of gate structures 160 are not limited thereto.
The fourth isolation insulating pattern 184 may include the same material as that of the second isolation insulating pattern 182 (see
This may be because the fourth isolation insulating pattern 184 is formed through the same etching process as the second isolation insulating pattern 182.
In the semiconductor device 100e according to the example embodiment, the isolation insulating patterns 180 may further include the fourth isolation insulating pattern 184 together with the first and second isolation insulating patterns 181 and 182 in
Referring to
Sacrificial layers 111 and channel layers 140 alternately stacked on the substrate 101 may be formed, and a trench defining the active regions 105 may be formed by at least a portion of the sacrificial layers 111, the channel layers 140, and the substrate 101. The sacrificial layers 111 and the channel layers 140 may be formed by an epitaxial growth process. The sacrificial layers 111 may be formed of a material having etch selectivity with respect to the channel layers 140. The sacrificial layers 111 and the channel layers 140 may include, for example, a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), and may include different materials. The sacrificial layers 111 may include, for example, silicon germanium (SiGe), and the channel layers 140 may include silicon (Si).
The active regions 105 may be defined by the trench. The active regions 105 may be formed to protrude to the upper surface of the substrate 101 by removing a portion of the substrate 101. The active regions 105 may have a shape protruding in the z-direction, which may be a direction perpendicular to the substrate 101, and may be formed of the same material as that of the substrate 101. The active regions 105 may be formed in a line shape extending in a first horizontal direction (e.g., x-direction), and may be spaced apart from each other in a second horizontal direction (e.g., y direction). In an example embodiment, the active regions 105 may include first and second active regions 105a and 105b, and third and fourth active regions 105c and 105d, spaced apart from each other in they direction.
The device isolation layers 107 may be formed in the region from which the substrate 101 is partially removed by filling the insulating material therein and partially removing the insulating material to allow the active regions 105 to protrude. The device isolation layers 107 may cover a portion of side surfaces of the active regions 105. A level of an upper surface of the device isolation layers 107 may be lower than a level of an upper surface of the active regions 105. The device isolation layers 107 may include silicon oxide.
Thereafter, the sacrificial gate structures SG intersecting the active regions 105 and parallel to each other may be formed. Each of the sacrificial gate structures SG may have a line shape extending in one direction, that is, for example, the y direction. The sacrificial gate structures SG may be sacrificial structures formed in a region in which the gate dielectric layer 162 and the gate electrode 165 are disposed on the channel layers 140 through a subsequent process. The sacrificial gate structures SG may include a sacrificial gate layer SGL and a sacrificial gate capping layer stacked in order. The sacrificial gate layer SGL may be formed of, for example, polysilicon, and the sacrificial gate capping layer may be formed of a silicon nitride layer. However, the structure and material of the sacrificial gate structures SG may be varied.
Spacer structures 164 may be formed on both sidewalls of the sacrificial gate structures SG. The spacer structure 164 may be formed by forming a film having a uniform thickness along the upper and side surfaces of the sacrificial gate structures SG and the upper surface of the active regions 105 and performing an anisotropic etching process. The spacer structure 164 may include an insulating material, such as, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.
Thereafter, the active regions 105 may be exposed by etching portions of the sacrificial layers 111 and the channel layers 140 using the sacrificial gate structures SG and the spacer structure 164 as an etch mask, and the source/drain regions 150 may be formed on the exposed active regions 105.
A recess portion may be formed by removing the exposed sacrificial layers 111 and the channel layers 140 between the sacrificial gate structures SG, and the active regions 105 may be exposed. A portion of the substrate 101 may be recessed by forming the recess portion deeply, but an example embodiment thereof is not limited thereto, and the recess portion may be recessed such that a lower surface of the recess portion may be in contact with the substrate 101.
The source/drain regions 150 may be formed by performing an epitaxial growth process in the recess portion. The source/drain regions 150 may include impurities by, for example, in-situ doping.
Thereafter, the insulating liner 191 and the interlayer insulating layer 190 may be formed in order, and a planarization process may be performed until the sacrificial gate layer SGL is exposed.
The insulating liner 191 may cover the sacrificial gate structures, the spacer structure 164, the source/drain regions 150, and the device isolation layers 107. The interlayer insulating layer 190 may cover a side surface and an upper surface of the insulating liner 191. The interlayer insulating layer 190 may be formed of silicon oxide or a low dielectric material, and the insulating liner 191 may be formed of a material different from that of the interlayer insulating layer 190, such as, for example, silicon nitride or a silicon nitride-based insulating material. A portion of the spacer structure 164 and the sacrificial gate capping layer may be removed through the planarization process.
Referring to
The sacrificial layers 111 and the sacrificial gate structures may be selectively removed with respect to the spacer structure 164, the interlayer insulating layer 190, and the channel layers 140. First, upper gap regions may be formed by removing the sacrificial gate layer SGL exposed through the planarization process, and lower gap regions may be formed by removing the sacrificial layers 111 exposed through the upper gap regions. For example, when the sacrificial layers 111 include silicon germanium (SiGe) and the channel layers 140 include silicon (Si), the sacrificial layers 111 may be selectively removed by performing a wet etching process using peracetic acid as an etchant.
A gate dielectric layer 162 and a gate electrode 165 may be formed in order in the upper gap region and the lower gap region. The gate dielectric layer 162 may be formed to conformally cover internal surfaces of the upper gap regions and the lower gap regions. The gate electrode 165 may be formed by entirely filling the upper gap regions and the lower gap regions.
The capping layer 166 may be formed by lowering the level of the upper surface by partially etching from the upper portion of the gate electrode 165 and the upper portion of the spacer structure 164 by a predetermined depth, filling an insulating material in the space formed as the upper surface is lowered, and performing a planarization process. The planarization process may be performed such that the upper surface of the interlayer insulating layer 190 may be exposed, but in example embodiments, a portion of the upper surface of the interlayer insulating layer 190 may be recessed. The capping layer 166 may be formed of silicon nitride or a silicon nitride-based insulating material. Accordingly, each of the gate structures 160 including the gate dielectric layer 162, the spacer structure 164, the gate electrode 165, and the capping layer 166 may be formed. In an example embodiment, the gate structures 160 may include first and second gate structures 160a and 160b intersecting the first and second active regions 105a and 105b, wherein the first and second gate structures 160a and 160b are spaced apart from each other and extend in parallel to each other. Also, the gate structures 160 may include third and fourth gate structures 160c and 160d intersecting the third and fourth active regions 105c and 105d, wherein the third and fourth gate structures 160c and 160d are spaced apart from each other and extend in parallel to each other.
Referring to
The first isolation insulating pattern 181 may be formed by forming an opening penetrating the interlayer insulating layer 190 on the device isolation layers 107 between the first and second gate structures 160a and 160b and filling the opening with an insulating material. The insulating material may include oxide, nitride, carbide, or a combination thereof, and may include, for example, silicon nitride. The opening may be formed by performing a patterning process, such as an exposure process, on a region corresponding to the opening, and performing an etching process. The etching process may be, for example, a dry etching process. In an example embodiment, the etching process may be a process of selectively removing the interlayer insulating layer 190 with respect to the gate structures 160 under a specific etching condition. In the etching process, a portion of the capping layer 166 may be removed even in a process having an etch selectivity. Alternatively, in example embodiments, the capping layer 166 may not be removed.
As the planarization process is performed after filling the opening with an insulating material, the upper surface of the first isolation insulating pattern 181 may be substantially coplanar with the upper surface of the capping layer 166. The first isolation insulating pattern 181 may have a first length L1 in the z direction. A lower surface of the first isolation insulating pattern 181 may be disposed on a level higher than a level of lower surfaces of the source/drain regions 150. This may be because the first isolation insulating pattern 181 may be a region corresponding to the opening having a relatively small width and extending by a thin depth by the etching process having the etch selectivity. As the first isolation insulating pattern 181 is formed by an etching process having the etch selectivity, the first isolation insulating pattern 181 may not affect electrical properties of the adjacent gate structures 160.
Referring to
The second isolation insulating pattern 182 may be formed by forming an opening penetrating the interlayer insulating layer 190 on the device isolation layers 107 between the third and fourth gate structures 160c and 160d, and filling the opening with an insulating material. The insulating material may include oxide, nitride, carbide, or a combination thereof, such as, for example, silicon nitride. The second isolation insulating pattern 182 may include an insulating material different from that of the first isolation insulating pattern 181, but an example embodiment thereof is not limited thereto and the first isolation insulating pattern 181 and the second isolation insulating pattern 182 may include the same insulating material. The opening may be formed by performing a patterning process, such as an exposure process, on a region corresponding to the opening, and performing an etching process. The etching process may be, for example, a dry etching process. In an example embodiment, the etching process may be performed to form the opening by anisotropic etching without an etching selectivity. Accordingly, the etching process may remove at least a portion of the insulating liner 191 and the spacer structure 164 together with the interlayer insulating layer 190. Also, in an example embodiment, the etching process may remove a portion of the source/drain regions 150 (see, e.g.,
As the planarization process is performed after filling the opening with an insulating material, the upper surface of the second isolation insulating pattern 182 may be substantially coplanar with the upper surface of the capping layer 166. The second isolation insulating pattern 182 may have a second length L2 in the z direction. A lower surface of the second isolation insulating pattern 182 may be disposed on a level lower than a level of the lower surface of the source/drain regions 150. This may be because the second isolation insulating pattern 182 may be a region corresponding to an opening having a relatively large width and extending by a deep depth by an etching process without an etching selectivity. As the second isolation insulating pattern 182 is formed by an etching process without an etching selectivity, the second isolation insulating pattern 182 may extend by a deep depth such that leakage current caused by contact between adjacent contact plugs 170 formed through a subsequent process may be prevented or addressed.
In an example embodiment, as described with reference to
Referring to
The contact openings OP1, OP2, OP3, and OP4 penetrating the interlayer insulating layer 190 and exposing the source/drain regions 150 may be formed by performing an etching process. The etching process may include a dry etching process or a wet etching process. The contact openings OP1, OP2, OP3, and OP4 may further extend from the source/drain regions 150 by a predetermined depth, but an example embodiment thereof is not limited thereto.
In an example embodiment, the contact openings OP1, OP2, OP3, and OP4 may be formed by etching the interlayer insulating layer 190 in a direction perpendicular to the substrate 101 along side surfaces of the capping layer 166, the first isolation insulating pattern 181, and the second isolation insulating pattern 182. Since the capping layer 166, the first isolation insulating pattern 181, and the second isolation insulating pattern 182 may include a material having strong etch resistance with respect to the interlayer insulating layer 190, the openings OP1, OP2, OP3, and OP4 may be formed without the components being etched. The capping layer 166, the first isolation insulating pattern 181, and the second isolation insulating pattern 182 may form contact openings OP1, OP2. OP3. OP4 for forming a self-aligning contact (SAC). Alternatively, the contact openings OP1, OP2, OP3, and OP4 may be formed to correspond to the patterned region through a mask patterned through an exposure process and an etching process.
In an example embodiment, the contact openings OP1, OP2, OP3, and OP4 may include a first contact opening OP1 exposing the first source/drain region 150a, a second contact opening OP2 exposing the second source/drain region 150b, a third contact opening OP3 exposing the third source/drain region 150c, and a fourth contact opening OP4 exposing the fourth source/drain region 150d.
The first and second contact openings OP1 and OP2 may be spaced apart from each other by the first isolation insulating pattern 181. The first and second contact openings OP1 and OP2 may expose a portion of a side surface of the first isolation insulating pattern 181.
The third and fourth contact openings OP3 and OP4 may be spaced apart from each other by the second isolation insulating pattern 182. The third and fourth contact openings OP3 and OP4 may expose a portion of a side surface of the second isolation insulating pattern 182.
In this process, when the first and second contact openings OP1 and OP2 are formed by a wet etching process and the openings are formed by a relatively deep depth, the first and second contact plugs 170a′ and 170b′ in
Thereafter, referring to
According to the aforementioned example embodiments, by forming the isolation insulating patterns having different depths in different regions, a semiconductor device having improved electrical properties and productivity in which a leakage current defect between contact plugs formed through a subsequent process may be controlled may be provided.
While the example embodiments have been illustrated and described above, it will be configured as apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1020220047647 | Jan 2022 | KR | national |
