Patent Application
20100237382
The present invention relates to semiconductor light emitting elements, in which compound semiconductor layers are stacked on single crystal substrates, and semiconductor light emitting devices using the elements.
Technology for improving light extraction efficiency and luminance of a semiconductor light emitting element is described in Patent Document 1. In a gallium nitride compound semiconductor element in Patent Document 1, asperities are formed by etching, on a side surface of a substrate or a side surface of a gallium nitride compound semiconductor element stacked on the substrate.
As such, when an emitting surface for emitting light has the asperities, the degree of total reflection of light coming from the inside on the surface can be reduced more than in a smooth surface. Thus, an improvement in the light extraction efficiency can be expected.
PATENT DOCUMENT 1: Japanese Patent Publication No. 2004-6662
However, in the gallium nitride compound semiconductor element described in Patent Document 1, asperities are formed by etching, on the side surface of the substrate or the side surface of the gallium nitride compound semiconductor stacked on the substrate. Thus, in the manufacturing process, an etching step needs to be added after stacking the gallium nitride compound semiconductor on the substrate. This complicates the manufacturing process and increases the manufacturing cost. In this method, since the asperities are reduced with an increase in an etching depth, it is difficult to form the asperities over the entire surface.
An objective of the present invention is to form asperities over the entire surface of a side surface of a semiconductor light emitting element without adding any manufacturing step so as to provide a semiconductor light emitting element capable of improving light extraction efficiency, a semiconductor light emitting device using the element, and a method of manufacturing the device.
The semiconductor light emitting element of the present invention includes a compound semiconductor layer stacked on a single crystal substrate, and is formed by separating the single crystal substrate into individual pieces. A side surface of the separated single crystal substrate is different from a cleavage plane of the single crystal substrate.
In particular, in the semiconductor light emitting element of the present invention, each of the individual pieces separated from the single crystal substrate, on which the compound semiconductor is stacked, has a rectangular shape. Neither of side surfaces on the longer sides of the rectangle is a cleavage plane.
The present invention only requires that the side surface of the single crystal substrate be different from the cleavage plane, when separating the single crystal substrate in a manufacturing process. There is thus no need to add an extra manufacturing step to improve the light extraction efficiency. Therefore, the present invention can provide a semiconductor element with high luminance efficiency without increasing manufacturing costs.
Since each individual piece separated from the single crystal substrate has a rectangular shape, and neither of the side surfaces on the longer sides is the cleavage plane; the light extraction efficiency of the entire semiconductor light emitting element can be improved as compared to the case where all the side surfaces are the cleavage planes; even if the side surfaces on the shorter sides are the cleavage planes totally reflecting light.
A semiconductor light emitting element according to an embodiment of the present invention will be described hereinafter with reference to
As shown in
Referring to
Referring to
The compound semiconductor layer 3 may be a gallium nitride compound semiconductor layer, when the individual piece 2 is made of, e.g., nitride compound semiconductor (e.g., GaN, MN, InN, AlGaN, InGaN, InAlN, or InAlGaN), silicon carbide semiconductor (SiC), or zinc oxide compound semiconductor (e.g., ZnO, or ZnMgO); and it may be a zinc oxide compound semiconductor layer, when the substrate is made of zinc oxide compound semiconductor. In particular, when the individual piece 2 is made of nitride compound semiconductor, the compound semiconductor layer 3 is preferably made of gallium nitride compound semiconductor. When the individual piece 2 is made of zinc oxide compound semiconductor, the compound semiconductor layer 3 is preferably a zinc oxide compound semiconductor layer.
When the compound semiconductor layer 3 made of such a material is grown on a single crystal substrate 2, the compound semiconductor layer 3 is stacked, with the orientation of the cleavage plane of the single crystal substrate 2 being identical to the orientation of the cleavage plane of the compound semiconductor layer 3. Therefore, the side surface of the compound semiconductor layer 3 also has fine asperities.
The compound semiconductor layer 3 includes an n-type semiconductor layer 31, an active layer 32, and a p-type semiconductor layer 33. A buffer layer can be provided between the n-type semiconductor layer 31 and the individual piece 2. The compound semiconductor layer 3 is formed by sequentially growing the n-type semiconductor layer 31, the active layer 32, and the p-type semiconductor layer 33 on the single crystal substrate (wafer) 2 using a crystal growing apparatus.
Above the wafer provided with the compound semiconductor layer 3, the p-type semiconductor layer 33, the active layer 32, and a part of the n-type semiconductor layer 31 are removed by dry etching or the like to expose a region, on which the n-type electrode 4 is to be formed. When the single crystal substrate 2 has n-type conductivity, the n-type semiconductor layer 31 may be also removed to expose the single crystal substrate 2 to form the n-type electrode 4 on the single crystal substrate 2. When the single crystal substrate 2 has the n-type conductivity, an n-type electrode may be formed on a surface opposite to the surface of the single crystal substrate 2, on which the compound semiconductor layer 3 is stacked. In this case, dry etching is not necessarily required.
The n-type electrode 4 is preferably formed on and in contact with the n-type semiconductor layer 31 or a conductive substrate, and is preferably made of Al with high reflectivity so that the light emitting plane reflects light. On the other hand, the surface of the n-type electrode 4 is preferably made of Au to function as an electrode for bonding. Therefore, it is preferable that an Al layer is formed, on which a barrier metal layer made of an element of Ti, Pt, or Ni is formed; and then an Au layer is formed on the barrier metal layer.
The p-type electrode 5 is an electrode for bonding, and is made of Au. The p-type electrode 5 may have a multilayer structure. For example, a contact layer can be formed to obtain ohmic contact with the p-type semiconductor layer 33. The contact layer can be made of one of In, Zn, Pt, Pd, Ni, Co, and Mg; or an alloy or a conductive film containing at least one of the metals. When the contact layer is the conductive layer, it can be made of ITO or ZnO.
After forming the contact layer, a reflective layer for reflecting light passing from the p-type semiconductor layer 33 toward the single crystal substrate 2 may be formed. The reflective layer can be made of Ag, Al, or Rh; or an alloy containing at least one of the metal's. Ag or an Ag alloy is preferable, since they have high reflectivity.
Referring to
The semiconductor light emitting element 1 formed by separating the single crystal substrate 2 will be further described specifically with reference to
As shown in
In
Note that the shape of the wafer 10 is not limited to rectangular, but the wafer may have a substantially disk shape or other shapes, as long as it has the OF plane 11 or a mark corresponding to the plane.
In
At this time, the side surface 21 being one of the surfaces adjacent to the side surface 24 is oriented at an angle of 90° with respect to the (10-10) plane, at an angle of 30° with respect to the (01-10) plane, and at an angle of 150° with respect to the (1-100) plane. That is, the side surface 21 does not coincide with any of the cleavage planes.
In the present invention, since each individual piece has a rectangular shape, the side surface 22 opposite to the side surface 24 has the same cleavage planes as the side surface 24, and like the side surface 21, the side surface 23 opposite to the side surface 21 does not coincide with any of the cleavage planes.
Therefore, by separating the wafer 10 being a single crystal substrate into individual pieces, the long side surface 21 (and the long side surface 23) of the individual piece 2 can be different from the cleavage planes. While the short side surface 24 is the cleavage plane at this time, when the individual piece has a rectangular shape, light extraction efficiency of the entire semiconductor light emitting element can be improved with an increase in light extraction efficiency of the long side surfaces. Therefore, with an increase in the length ratio of the long sides to the short sides, the degree of the improvement in the light extraction efficiency can be increased.
In this case, the light extraction efficiency is improved more than in the case where the short side surfaces are the cleavage planes, and a more desirable semiconductor light emitting element can be obtained. Note that, when the long side surface 21 is located between (10-10) and (01-10), or between (10-10) and (1-100), the long side surfaces are not the cleavage planes, and similar circumstances occur.
The substrate can be easily separated by forming a groove for segmenting a wafer, which includes a compound semiconductor layer on a single crystal substrate using a laser scribing apparatus; and breaking the groove. The depth of the groove preferably ranges from 5 to 50% of the thickness of a side surface. When the depth of the groove is smaller than 5%, the wafer cannot be broken at the height of the groove, thereby reducing yields of the separation. When the depth of the groove is larger than 50%, the area of the fine asperities formed on the side surface is reduced to decrease the light extraction efficiency.
That is, when the laser scribing apparatus is used to cut out a part not being the cleavage plane as a side surface, the groove formed by the laser scribing apparatus has a relatively smooth side surface. Thus, a portion with fine asperities and a portion without the fine asperities are formed in the thickness direction of the substrate. This means that, in the semiconductor light emitting element of the present invention, the fine asperities are formed on a half or more of the side surface of the substrate in the thickness direction of the substrate.
Note that the groove by the laser scribing apparatus may be formed on the surface of the wafer provided with the compound semiconductor layer 3, or on the surface opposite to the surface provided with the compound semiconductor layer 3.
As such, simply by setting the long side surfaces of the individual piece 2 to be different from the cleavage planes, when the single crystal substrate is separated in a manufacturing process; the asperities are formed on the side surface of the semiconductor light emitting element 1 to improve the light extraction efficiency. There is no need to add an extra manufacturing step. Therefore, complication in the manufacturing process and an increase in the manufacturing cost can be alleviated.
This embodiment describes the case where the wafer is separated so that the short side surfaces of the individual piece 2 are oriented at an angle of 0° with respect to the cleavage planes. This is because, when the reference side surface of the individual piece 2 is oriented at an angle of 0° with respect to the cleavage planes, the long side surfaces can be oriented at an angle of 30° or more with respect to each of the cleavage planes. However, since the cleavage planes are necessarily oriented at an angle of 60° with respect to each other, the long side surfaces of the individual piece 2 may be oriented at an angle of more than 0° and less than 60° with respect to the cleavage planes.
However, when the angle is close to 0° or 60°, the wafer may crack from the cleavage planes, which are easily cleaved. Therefore, by setting the angle to be a range from 5° to 55°, the long side surfaces of the individual piece 2 can be oriented with an extra angle of 5° or more with respect to the cleavage planes. This reduces cracking of the wafer from the cleavage planes, when separating the wafer except for the cleavage planes.
Furthermore, when the long side surfaces of the individual piece 2 are oriented at an angle ranging from 10° to 50° with respect to the cleavage planes, each of the side surfaces of the individual piece 2 can be oriented with an extra angle of 10° or more with respect to the cleavage planes. This reliably reduces the cracking from the cleavage planes, and enables formation of a larger number of asperities, thereby further increasing the light extraction efficiency.
It is further preferable that the long side surfaces are oriented at an angle ranging from 0° to 30° with respect to the cleavage planes, since the short side surfaces can be different from the cleavage planes. With an extra angle of 5° or 10° with respect to the cleavage planes, the cracking from the cleavage planes in processing can be reduced. Specifically, the long side surfaces are preferably oriented at an angle ranging from 5° to 25°, and more preferably ranging from 10° to 20° with respect to the cleavage planes.
In the present invention, when a rectangular semiconductor light emitting element is manufactured and the long side surfaces of the element are not the cleavage planes of the single crystal, the fine asperities can be formed on the long side surfaces only by separating the element from the wafer. As a result, the light extraction efficiency can be improved. In a hexagonal single crystal, there is a combination of crystal planes capable of implementing the present invention other than the combination shown in
When the long side surfaces are oriented at an angle of 90° with respect to the c plane, the short side surfaces occasionally coincide with the c plane to be the cleavage planes. However, similar to the case where the main surface is the c plane, even when the short side surfaces are the cleavage planes, the light extraction efficiency of the entire element is improved, as long as fine the asperities can be formed on the long side surfaces having large areas. That is, the present invention includes the case where the short side surfaces are the cleavage planes. The long side surfaces are preferably oriented at an angle ranging from 0° to 90° with respect to the c plane, since none of the planes is the cleavage plane.
However, when the long side surfaces are oriented at an angle of 90° with respect to the c plane, the long side surfaces other than the groove for laser scribing are not vertical to the main surface, even if the groove is formed vertically to the main surface and the element is broken along the groove using the laser scribing apparatus. It is highly possible that the long side surfaces other than the groove would crack at another m plane: the m plane (01-10) or the (10-10) plane, which intersects the main surface at an angle of 60° or 120°, respectively. Therefore, the long side surfaces are more preferably oriented at an angle ranging from 0° to 60° with respect to the c plane. When the extra angle with respect to the cleavage planes is 5° as described above, the long side surfaces may be oriented at an angle ranging from 5° to 60°.
As described above, in the semiconductor light emitting element of the present invention, the c plane, the a plane, and the m plane of the hexagonal single crystal are the main surfaces; and the element is cut out from the substrate in a predetermined surface direction, thereby improving the light extraction efficiency. This semiconductor light emitting element can be used for various types of semiconductor light emitting devices.
A submount 121 is provided with extraction electrodes 122 and 123. The extraction electrodes are for applying currents to the semiconductor light emitting element 1. There are the n-side extraction electrode 122 coupled to the n-type layer side of the semiconductor light emitting element, and the p-side extraction electrode 123 coupled to the p-type layer side.
The submount 121 can be made of, e.g., silicon zener diode, silicon diode, silicon, aluminum nitride, alumina, or other ceramics.
The extraction electrodes are provided with bumps 124 and 125. As the extraction electrodes are, there are the bumps of the n-side bump 124 coupled to the n-type layer side, and the p-side bump 125 coupled to the p-type layer side.
The bumps have the function of fixing the semiconductor light emitting element 1 onto the submount 121, and electrically coupling the extraction electrode 122 to the extraction electrode 123.
The bumps can be made of, e.g., gold, gold-tin, solder, an indium alloy, and conductive polymer. In particular, gold or a material containing gold as a main component is preferable. The bumps can be formed, e.g., by plating, vacuum deposition, screen-printing, spraying, and wire bumping using these materials.
For example, a gold wire is formed by wire bumping, and the end of the wire is boded to the extraction electrodes on the submount using a bonder. Then, the wire is cut off, thereby forming a gold bump. Also, spraying can be used, in which liquid containing fine nanoparticles of a high conductive material such as gold dispersed in a volatile solvent is sprayed by a method similar to ink jet printing, and the solvent is volatilized to form a bump as an aggregation of the nanoparticles.
Also, at least one of the p-side bumps is located near the long side surface on the same side as the n-side bump, and at least one of the p-side bumps is located near the long side surface on the opposite side to the n-side bump. Specifically, referring to
Furthermore, the p-side bump 125-2 disposed at the side of the side surface, which is on the same side as the n-side bump, is preferably disposed apart from the n-side bump 124 as far as possible. This is to increase the area of the triangle formed by the three bumps. When the triangle has a large area, the semiconductor light emitting element 1 is firmly fixed. The third and subsequent p-side bumps may be disposed in any position.
In the present invention, a compound semiconductor layer is formed using any of the c plane, the a plane, and the m plane of a hexagonal single crystal as the main surface, the cutting direction of the substrate is oriented at a predetermined angle so that the long side surfaces are not the cleavage planes, and fine asperities are formed only by the step of separating the substrate, thereby improving the light extraction efficiency. Clearly, the fine asperities may be formed on the light emitting plane itself.
There are several methods of forming the fine asperities 147, and any method may be used. However, a method applying less mechanical stress is preferable. Specifically, a method with etching may be used. Forming the asperities on a surface by etching is a simple step and improves the light extraction efficiency. However, as a feature, the method has difficulty in accurately controlling the asperities, and exactly same asperities cannot be formed on the light emitting plane. Wet etching or dry etching can be used as etching. For example, ion milling or a chlorine gas method can be used as dry etching. An etchant containing alkali as a main component may be used in wet etching.
The asperities can be formed on the outer surface of the light emitting plane by ink jet printing. The method can be easily implemented, since it does not include the step of etching the light emitting plane. Furthermore, the light extraction efficiency can be further improved by adjusting refractivity of a material for asperities mixed into ink.
Moreover, if mechanical stress may be applied to some extent, a mechanical processing method using, e.g., nanoimprint technology can be used. In the nanoimprint technology, a sealing resin is applied to the light emitting plane and cured, and then asperities can be formed on the light emitting plane 36 by blasting.
Also, after the sealing resin is cured once, the surface is polished to be smooth, and a liquid resin is thinly applied to the polished surface to form a film, which is subjected to nanoimprinting to form asperities. Note that a sealing layer containing a fluorescent material may be provided between the light emitting plane and the surface subjected to anti-reflection treatment of the substrate.
The present invention enables formation of asperities on the side surface of a semiconductor light emitting element without requiring any additional manufacturing step, thereby improving light extraction efficiency, and is thus preferable as a semiconductor light emitting element formed by staking a semiconductor layer on a translucent substrate.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-274998 | Oct 2007 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/002557 | 9/17/2008 | WO | 00 | 4/12/2010 |
