Claims
- 1. A semiconductor memory testing device comprising:
- a redundancy circuit for compensating incorrect data created when there is a failure in a semiconductor memory; and
- failure data digit destination means for designating a digit of a failure data related to said failure in said semiconductor memory, wherein
- said redundancy circuit includes:
- a plurality of signal lines connected in correspondence to data of a plurality of digits of said semiconductor memory;
- an extra line disposed adjacent to said signal lines;
- a binary signal designating part for supplying first and second values, said binary signal designating part supplying said first value to signal lines on a first side to a signal line which is associated with a digit which is designated as a failure bit by said failure data digit designating means and supplying the second value to signal lines on a second side to said signal line which is associated with said digit which is designated as said failure bit; and
- a selector group for receiving a binary signal from said binary signal designating part, in response to said binary signal, said selector group disconnecting said signal line associated with said digit designated as said failure bit by said failure data digit designating means and for connecting an outer most signal line to said extra line and remaining signal lines to respective next signal lines.
- 2. A semiconductor memory testing device in accordance with claim 1, wherein said failure data digit designating means includes a binary data holding means for holding one of said first and second values in correspondence to said digit of said failure data and holding another of said first and second values in correspondence to other digits,
- wherein said binary signal designating part includes a plurality of AND circuits which correspond to data of said plurality of digits of said semiconductor memory,
- wherein first input terminals of said plurality of AND circuits are connected respectively to digits which correspond to said binary data holding means, and
- wherein second input terminals of said plurality of AND circuits are each connected to an output terminal of an adjacent AND circuit.
- 3. A semiconductor memory testing device in accordance with claim 2, wherein said binary data holding means includes a register whose digit number corresponds to a data digit number of said semiconductor memory.
- 4. A semiconductor memory testing device in accordance with claim 2, wherein said binary data holding means includes a plurality of flip-flops connected to data feedback loop wires.
- 5. A semiconductor memory testing device in accordance with claim 1, wherein said failure data digit designating means includes a binary data holding means for holding one of said first and second values in correspondence to said digit of said failure data and holding another of said first and second values in correspondence to other digits,
- said selector group includes:
- a plurality of primary selector parts for selecting mutually adjacent signal lines; and
- a plurality of secondary selector part for selecting output terminals of said plurality of primary selector parts,
- said binary signal designating part includes:
- a primary control circuit for switching said plurality of primary selector parts of said selector group; and
- a secondary control circuit for switching said plurality of secondary selector parts of said selector group,
- said primary control circuit includes a plurality of primary AND circuits which correspond to at least a portion of said plurality of digits of said semiconductor memory,
- wherein first input terminals of said plurality of primary AND circuits are connected to digits which correspond to said binary data holding means,
- wherein second input terminals of said plurality of primary AND circuits are each connected to an output terminal of an adjacent primary AND circuit,
- wherein said secondary control circuit includes a plurality of secondary AND circuits which correspond to at least a portion of said plurality of primary AND circuits,
- wherein first input terminals of said plurality of secondary AND circuits are connected to said plurality of primary AND circuits, respectively, and
- wherein second input terminals of said plurality of secondary AND circuits are each connected to an output terminal of an adjacent secondary AND circuit.
- 6. A semiconductor memory testing device in accordance with claim 5, further including a plurality of ports disposed to correspond to said data digit number of said semiconductor memory, and said semiconductor memory testing device further comprising an AND circuit for calculating a logical product for each port and supplying said logical product to said binary data holding means.
- 7. A semiconductor memory testing device in accordance with claim 1, wherein said failure data digit designating means includes a binary data holding means for holding one of said first and second values in correspondence to said digit of said failure data and holding another of said first and second values in correspondence to other digits, said selector group includes:
- a plurality of first-layer selector parts for selecting mutually adjacent signal lines; and
- a second- to N-th layer selector parts for selecting output terminals of said plurality of first-layer selector parts (where N is an integer not smaller than 2),
- said binary signal designating part includes a first- to N-th layer control circuits for switching said first- to N-th layer selector parts of said selector group,
- said first-layer control circuit includes a plurality of first-layer AND circuits which correspond to at least a portion of said plurality of digits of said semiconductor memory,
- wherein first input terminals of said plurality of first-layer AND circuits are respectively connected to digits which correspond to said binary data holding means,
- wherein second input terminals of said plurality of first-layer AND circuits are each connected to an output terminal of an adjacent first-layer AND circuit,
- said second- to N-th layer control circuits each include at least:
- a plurality of control selectors for receiving signals from said first- to (N-1)-th layer AND circuits of said first-to (N-1)-th layer control circuits and disconnecting said binary data holding means adjacent to said failure data digit designating means; and
- a plurality of a second- to N-th layer AND circuits which correspond to said control selectors,
- wherein first input terminals of said second to N-th layer AND circuits are connected to corresponding ones of said control selectors, and
- wherein second terminals of said second to N-th layer AND circuits are each connected to an output terminal of an adjacent-layer AND circuit.
- 8. A semiconductor memory testing device in accordance with claim 7, further including a plurality of ports disposed to correspond to said data digit number of said semiconductor memory, and said semiconductor memory testing device further comprising an AND circuit for calculating a logical product for each port and supplying said logical product to said binary data holding means.
Priority Claims (4)
Number |
Date |
Country |
Kind |
6-112638 |
May 1994 |
JPX |
|
6-147450 |
Jun 1994 |
JPX |
|
6-172348 |
Jul 1994 |
JPX |
|
6-286631 |
Nov 1994 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/434,999, filed on May 4, 1995, now U.S. Pat. No. 5,815,512, which is a continuation-in-part of application Ser. No. 08/316,485, filed on Sep. 30, 1994, now abandoned.
US Referenced Citations (19)
Foreign Referenced Citations (14)
Number |
Date |
Country |
52-103933 |
Aug 1977 |
JPX |
53-62953 |
Jun 1978 |
JPX |
59-94086 |
May 1984 |
JPX |
60-120269 |
Jun 1985 |
JPX |
61-61300 |
Mar 1986 |
JPX |
62-282280 |
Dec 1987 |
JPX |
63-134970 |
Jun 1988 |
JPX |
1-73267 |
Mar 1989 |
JPX |
2-67976 |
Mar 1990 |
JPX |
2-210280 |
Aug 1990 |
JPX |
2-278173 |
Nov 1990 |
JPX |
3-29872 |
Feb 1991 |
JPX |
4-145380 |
May 1992 |
JPX |
4-270976 |
Sep 1992 |
JPX |
Non-Patent Literature Citations (2)
Entry |
International Test Conference, pp. 608-614, Sep. 20-24, 1992, H. Maeno, et al., "LSSD Compatiable and Concurrently Testable Ram". |
International Test Conference, pp. 120-125, 1992, Sybille Hellebrand, et al., "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers". |
Divisions (1)
|
Number |
Date |
Country |
Parent |
434999 |
May 1995 |
|
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
316485 |
Sep 1994 |
|