The present invention relates generally to methods for manufacturing semiconductor packages. More specifically, the present invention relates to manufacturing semiconductor packages with reduced package stress.
Semiconductor packages are incorporated into most conventional electronic devices such as, for example, laptop computers, mobile telephones, games, medical devices, vehicles, and so forth. These semiconductor packages are typically formed from a metal lead frame that usually includes an arrangement of external connection leads and a flag (also referred to as a die pad) to which is mounted a semiconductor die. Electrical connection pads of the semiconductor die are electrically connected to the leads of the lead frame with wires. The semiconductor die and wires are then encapsulated, typically by a molding compound, to form the final semiconductor package.
Many semiconductor packages are sensitive to temperature stresses due to mismatched Coefficients of Thermal Expansion (CTE) of the various materials used inside the semiconductor package, as well as due to coupling of the semiconductor package to a system printed circuit board (PCB). The CTE describes how the size of an object changes with a change in the temperature. The mismatch of CTE's of the materials within a semiconductor package, as well as to the PCB substrate, can result in damage to the semiconductor package (such as cracking, delamination, solder fatigue, package and die warpage, and the like) under thermal shock or thermal cycling conditions. These problems can occur at the time of joining the semiconductor package to the PCB substrate or subsequently during the operating life of the semiconductor package. Accordingly, there remains a need for improved packaging of semiconductor dies to reduce or minimize the adverse effects of CTE mismatch in semiconductor packages.
The accompanying figures in which like reference numerals refer to identical or functionally similar elements throughout the separate views, the figures are not necessarily drawn to scale, and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.
In overview, the present disclosure concerns semiconductor packages and methods of their manufacture. The semiconductor packages described herein each include at least one semiconductor die that is fully surrounded by an encapsulant, i.e., a mold compound. Methodology entails encapsulating a flagless lead frame in a first encapsulant to form a molded structure, mounting the semiconductor die or dies directly to the first encapsulant, forming electrically conductive interconnects between die pads on the semiconductor die and the leads of the lead frame, then encapsulating the semiconductor die, the interconnects, and the leads in a second encapsulant. The various inventive concepts and principles embodied in the methods and semiconductor packages may reduce or minimize the adverse affects of CTE mismatch in semiconductor packages for improved manufacturing yield, improved reliability, and cost savings.
The instant disclosure is provided to further explain in an enabling fashion the best modes, at the time of the application, of making and using various embodiments in accordance with the present invention. The disclosure is further offered to enhance an understanding and appreciation for the inventive principles and advantages thereof, rather than to limit in any manner the invention. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.
Referring to
In a particular embodiment, molded structure 24 includes a lead frame 26 embedded in a first encapsulant 28. Lead frame 26 includes a plurality of external connection leads 30 (two shown in
Semiconductor die 22 includes a first surface, referred to herein as a connection pad surface 38, and a second surface, referred to herein as a mounting surface 40. Mounting surface 40 of semiconductor die 22 is mounted to encapsulant 28 in central region 32 of lead frame 26. The central region of a conventional lead frame typically includes a flag (also called a die pad) upon which a semiconductor die, multiple dies, or a die stack is mounted. In an embodiment, lead frame 26 does not include a flag at central region 32. Hence, lead frame 26 is “flagless” so that mounting surface 40 of semiconductor die 22 can be coupled directly to first encapsulant 28.
Connection pad surface 38 has die pads 42 formed thereon. Electrically conductive interconnects 44, such as bond wires, are connected between die pads 42 and top surface 34 of respective ones of leads 30 of lead frame 26. Leads 30 are laterally displaced from semiconductor die 22 and may surround one or more sides of semiconductor die 22. Semiconductor die 22, conductive interconnects 36, and top surface 34 of leads 30 are covered, i.e., encapsulated, by, a second encapsulant 46.
Lead frame 26 exhibits a first height 48 and molded structure 24 has a second height 50 that is approximately equivalent to first height 48. Accordingly, it should be readily observed that when semiconductor die 22 is mounted to first encapsulant 28 in central region 32, mounting surface 40 of semiconductor die 22 is approximately coplanar with top surface 34 of leads 28. That is, mounting surface 40 of semiconductor die 22 is vertically displaced away from an external surface of semiconductor package 20 so that semiconductor die 22 is sandwiched between first encapsulant 28 and second encapsulant 46.
In
First and second encapsulants 28, 46 protect semiconductor die 22 from exposure to external elements, e.g., air, moisture, liquids, and/or the substance of interest. Thus, first and second encapsulants 28, 46 provide robust mechanical and environmental protection. Furthermore, first and second encapsulants 28, 46 fully surround semiconductor die 22 thereby isolating semiconductor die 22 in order to effectively reduce package induced stresses on semiconductor die 22. First and second encapsulants 28, 46 may be formed in any suitable manner, as will be discussed in greater detail below, and any suitable molding material (e.g., epoxy- or silicone-based compounds) may be used.
At a block 62 of semiconductor package manufacturing process 60, conductive sheet 52 of lead frames 26 is provided. Conductive sheet 52 may be fabricated by the manufacturing facility that is executing process 60. Alternatively, conductive sheet 52 may be fabricated by an outside manufacturing facility and is thus provided by that outside manufacturing facility.
At a block 64, conductive sheet 52 that includes the plurality of flagless lead frames 26 is encapsulated with first encapsulant 28, which may be, for example, a mold compound or protective resin. Encapsulation block 64 can entail taping the bottom of conductive sheet 52 and then encapsulating conductive sheet 52. When conductive sheet 52 is encapsulated with first encapsulant 28, the tape will prevent first encapsulant 28 from bleeding out onto bottom surfaces 36 of leads 30. Additionally, conductive sheet 52 will be molded to the same height as lead frames 26 so that top surfaces of leads 30 are not covered with first encapsulant 28. As such, top surfaces 34 and bottom surfaces 36 of leads 30 are exposed from first encapsulant 28 following encapsulation. Thus, molded structure 24 is formed.
At a block 68, semiconductor dies 22 are mounted on first encapsulant 28 located in each central region 32 of each lead frame 26 formed in conductive sheet 52. Semiconductor dies 22 may be adhered, glued, or otherwise fixed to first encapsulant 28 located in each central region 32 using, for example, a die attach film, wafer backside coating, dispensed epoxy die attach, and so forth.
At a block 70, electrically conductive interconnects 44 (e.g., bond wires) are formed between die pads 42 of semiconductor dies 22 and top surfaces 34 of respective ones of leads 30. At a block 72, semiconductor dies 22, conductive interconnects 44, and top surfaces 34 of leads 30 are encapsulated in second encapsulant 46, which may be, for example, a mold compound or protective resin, to form a composite structure. Thereafter, at a block 74, the composite structure is separated into individual semiconductor packages 20 and process 60 ends.
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At a block 92 of semiconductor package manufacturing process 60, an electrically conductive sheet is provided. However, unlike conductive sheet 52, described above, the conductive sheet at block 92 may simply be a sheet (e.g., copper) that has not yet been patterned or shaped to include leads. At a block 94, the bottom side of the conductive sheet is patterned with a final lead pattern. That is, the conductive sheet is suitably masked at those locations where leads that will be used for external connections will be formed in subsequent processing operations. The remainder of the conductive sheet is not covered by the mask material.
At a block 96, semiconductor dies 22 are mounted on the conductive sheet at suitable locations. Semiconductor dies 22 may be adhered, glued, or otherwise fixed to the flags using, for example, a die attach film, wafer backside coating, dispensed epoxy die attach, and so forth. At a block 98, electrically conductive interconnects 44 (e.g., bond wires) are formed between die pads 42 of semiconductor dies 22 and top surfaces of respective ones of the leads that will eventually be formed in the conductive sheet.
At a block 100, semiconductor dies 22, conductive interconnects 44, and the top surface of the conductive sheet are encapsulated in first encapsulant, which may be, for example, a mold compound or protective resin. Next at a block 102, the conductive sheet is etched leaving the final pattern of leads which was suitably masked at block 94.
At a block 104, the structure is molded in a bottom molding process with a second encapsulant to embed or otherwise encapsulate the remaining leads. Thus, following execution of block 104, semiconductor dies 22 are sandwiched between first and second encapsulants. At a block 106, the bottom surfaces of the remaining leads may be exposed from the second encapsulant (if needed) and from the mask material. Thereafter, at a block 108, the composite structure is separated into individual semiconductor packages 20 and process 90 ends.
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Embodiments described herein entail semiconductor packages and methods of their manufacture. An embodiment of a method for manufacturing a semiconductor package comprises providing a lead frame, the lead frame being formed from an electrically conductive sheet having a plurality of leads extending from a lead frame boundary towards a central region of the lead frame, and encapsulating the lead frame with a first encapsulant such that a top surface of each of the leads is exposed from the first encapsulant. The method further comprises mounting a semiconductor die on the first encapsulant located in the central region of the lead frame, forming electrically conductive interconnects between die pads on the semiconductor die and the top surface of respective ones of the plurality of leads, and encapsulating the semiconductor die, the conductive interconnects, and the top surface of the leads with a second encapsulant.
An embodiment of a method for manufacturing a plurality of semiconductor packages comprises providing an electrically conductive sheet of flagless lead frames, each of the flagless lead frames having a plurality of leads extending from a lead frame boundary towards a central region of the lead frame, and encapsulating the electrically conductive sheet of flagless lead frames with a first encapsulant such that a top surface of each of the leads is exposed from the first encapsulant. The method further comprises mounting semiconductor dies on the first encapsulant located in each the central region of each of the flagless lead frames by directly coupling the semiconductor dies to the first encapsulant, forming electrically conductive interconnects between die pads on the semiconductor dies and the top surface of respective ones of the plurality of leads, encapsulating the semiconductor dies, the conductive interconnects, and the top surface of the leads with a second encapsulant to form a composite structure, and separating the composite structure into the plurality of semiconductor packages following both of the encapsulating operations, each of the semiconductor dies being sandwiched between a portion of the first encapsulant and a portion of the second encapsulant.
An embodiment of a semiconductor package comprises a lead frame embedded in a first encapsulant, the lead frame being formed from an electrically conductive sheet having a plurality of leads extending from a lead frame boundary towards a central region of the lead frame, wherein a top surface of each of the leads is exposed from the first encapsulant. The semiconductor package further comprises a semiconductor die in direct contact with the first encapsulant located in the central region of the lead frame, conductive interconnects electrically connected between die pads on the semiconductor die and the top surface of respective ones of the plurality of leads, and a second encapsulant covering the semiconductor die, the conductive interconnects, and the top surface of the leads.
The semiconductor packages described herein each include at least one semiconductor die that is fully surrounded by an encapsulant, i.e., a mold compound. A flagless lead frame is embedded in an encapsulant, semiconductor dies are coupled with the encapsulant, electrically conductive interconnects are formed between die pads on the semiconductor die and the leads of the lead frame, and the semiconductor die, the interconnects, and the leads in a second encapsulant. Thus, the semiconductor die is sandwiched between and fully surrounded by encapsulant to provide isolation for the semiconductor die from package stresses. The various inventive concepts and principles embodied in the methods and semiconductor packages may reduce or minimize the adverse affects of CTE mismatch in semiconductor packages for improved manufacturing yield, improved reliability, and cost savings.
This disclosure is intended to explain how to fashion and use various embodiments in accordance with the invention rather than to limit the true, intended, and fair scope and spirit thereof The foregoing description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Modifications or variations are possible in light of the above teachings. The embodiment(s) was chosen and described to provide the best illustration of the principles of the invention and its practical application, and to enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims, as may be amended during the pendency of this application for patent, and all equivalents thereof, when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.