Patent Application
20090032922
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2007-199342, filed Jul. 31, 2007, the entire contents of which are incorporated herein by reference.
1. Field
One embodiment of the present invention relates to a semiconductor package handling a differential signal and an electronic apparatus mounted with the semiconductor package.
2. Description of the Related Art
In an electronic apparatus such as personal computer, a circuit board is received as a main constituent component in a body of the electronic apparatus. The circuit board is mounted with a semiconductor device called as a chip set forming a CPU and peripheral circuits for the CPU.
This kind of the circuit board mounted with the semiconductor device requires high density wiring and high density mounting to achieve high speed signal processing and high performance. In order to meet the foregoing requirements, a high-density mounting technique has been proposed. According to the technique, one main surface of a multi-layer stacked board is mounted with an integrated circuit, and the other main surface thereof is mounted with a BGA (ball grid array) component. See Jpn. Pat. Appln. KOKAI Publication No. 2003-101432, for example.
A high-speed bus interface using a differential signal is applied as a technique for achieving high speed processing. The high-speed bus interface using the differential signal is provided with a coupling capacitor between an input circuit device and an output circuit device for preventing a direct current component from flowing between the input and output circuit devices. The coupling capacitor is used to reduce an influence of jitter caused by a potential difference between a voltage at an input side circuit device sending the differential signal and a voltage at an output side circuit device receiving the differential signal. The coupling capacitor is inserted in a differential signal transmission line connecting between the foregoing output and input side circuit devices. Conventionally, the foregoing coupling capacitor (pair) is inserted in the differential signal transmission line (pair) formed on a circuit board mounted with the foregoing input and output side circuit devices. In an actual high-speed bus interface circuit, many differential signal transmission lines (pairs) are arrayed on the circuit board. Each of the differential signal transmission lines (pairs) is provided with the coupling capacitor (pair). For this reason, the mounting area on the circuit board occupied by the differential signal lines is a factor of blocking the requirements of high density wiring and high density mounting. In particular, this kind of high-speed bus interface circuit using the differential signal requires an isometric wiring technique to prevent jitter caused by a transmission delay. For this reason, differential signal wiring must be carried out under strictly limited condition. This problem is further remarkable with respect to the foregoing requirements. In addition, this kind of high-speed bus interface circuit using the differential signal employs a plurality of lanes (transmitting/receiving) configuration. Further, an isometric wiring technique is required in every lane or line pair. For this reason, the differential signal interface configuration becomes remarkably complicated. As a result, a work load of a pattern design of a printed wiring board is very high, and there is a problem to achieve high density and miniaturization of the printed wiring board.
A general architecture that implements the various feature of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention.
Various embodiments according to the present invention will be hereinafter described with reference to accompanying drawings. In general, according to one embodiment of the present invention, there is provided a semiconductor package comprising: a substrate having one surface mounted with a semiconductor chip, and the other surface mounted with a plurality of arrayed external connection electrodes; a differential line pair provided on the surface of the substrate mounted with the semiconductor chip for connecting the semiconductor chip and a predetermined pair of electrodes included in the external connection electrodes; and a coupling capacitor pair inserted in the differential line pair.
A semiconductor package (hereinafter, referred to as BGA component) 10 according to the first embodiment of the present invention is composed of a substrate 12, a plurality of pairs of the differential lines 14, a plurality of pairs of the differential lines 15 and a plurality of pairs of the coupling capacitors 13. More specifically, the substrate 12 has one surface (front surface) mounted with a semiconductor chip (die) 11 handling a differential signal. The substrate 12 further has the other surface (back surface) mounted with a plurality of arrayed solder balls 18, 18, . . . , 18 functioning as external connection electrodes. The pairs of differential lines 14 and 15 are formed on the surface of the substrate 12, and make a connection between the semiconductor chip 11 and a predetermined pair of solder balls 18. The pair of coupling capacitors 13 is interposed between the differential lines 14 and 15.
As shown in
The surface (front surface) of the substrate 12 mounted with the semiconductor chip 11 is formed with a wiring (interconnection) pattern. The wiring pattern is used for connecting connection terminals of the differential circuit built in the semiconductor chip 11 to the solder balls 18 mounted on the back surface of the substrate 12 and functioning as external connection electrodes. The wiring pattern is composed of the differential lines 14 and 15. The differential lines 14 make a connection between differential circuit terminals of the semiconductor chip 11 and the terminals of the coupling capacitors 13 at one end. The differential lines 15 make a connection between the solder balls 18 and the terminals of the coupling capacitors 13 at the other end.
A differential signal transmission path is composed of differential lines 14, 15 and the coupling capacitors 13. In this case, two transmission lines are formed as one pair. The paired two transmission lines are configured as a signal line synchronous with a high speed clock. Thus, the line length is set to operate within a predetermined limited error range in order to reduce jitter by transmission delay. In other words, the length of the paired two transmission lines is adjusted within a predetermined limited error range, and thus, substantial isometric wiring is achieved.
The surface (front surface) of the substrate 12 mounted with the semiconductor chip 11 is provided with a plurality of arrayed pairs of coupling capacitors 13. In this case, the coupling capacitors 13 are provided around the semiconductor chip 11 as a unit of pairs in compliance with the rule of the foregoing isometric wiring. In
As seen from
As described above, according to the first embodiment of the present invention, the BGA component 10 has the following configuration. Specifically, the substrate 12 is provided with the coupling capacitor 13, which cuts a direct current component to prevent jitter caused by a potential difference between differential circuits (driver-receiver). In addition, the isometric wiring of the paired differential lines 14 and 15 formed via the coupling capacitors 13 on the substrate 12 is achieved. Thus, there is no need of providing a wiring structure for inserting the coupling capacitors on a differential wiring pattern conductors 21a, 21b in the printed wiring board (or circuit board) 20 mounted with the BGA component 10. Therefore, this serves to simplify a pattern design of a printed wiring board, and to achieve high density wiring, high density mounting and miniaturization of the printed wiring board. In particular, this kind of high-speed bus interface circuit using a differential signal employs the configuration of a plurality of lanes (transmitting/receiving) as described above. In addition, an isometric wiring technique is required every lane or paired lines in the conventional printed wiring board structure, thereby resulting a problem that the differential signal interface configuration becomes remarkably complicated. However, according to the first embodiment, it is possible to solve the foregoing problem, and to easily achieve simplification of a pattern design, high density and miniaturization in a printed wiring board. For example, in a high-speed bus interface such as PCI-Express and SATA (Serial-ATA), 16-lane configuration high-speed bus interface is built up. In the conventional case, 64 coupling capacitors 13 and 64 differential lines (isometric wiring) are required, whereby the interface configuration is remarkably troublesome. However, the first embodiment of the present invention largely contributes to solving the foregoing problem.
As shown in
The BGA component 10 is composed of a substrate 12, pairs of differential lines 14, pairs of differential lines 15 and pairs of coupling capacitors 13. More specifically, the substrate 12 has a front surface mounted with a semiconductor chip (die) 11 using a differential signal, and has a back surface to which a plurality of arrayed solder balls 18 each functioning as an external connection electrode is attached. The paired differential lines 14 and 15 are formed on the substrate 12 and make a connection between the semiconductor chip 11 and a predetermined pair of solder balls 18. The coupling capacitors 13 are inserted between the differential lines 14 and 15. One terminal of the differential line 15 having the other terminal connected with the coupling capacitor 13 is connected to a joint portion 17 mounted with the solder ball 18 via an interlayer through via 16 including a pad 17a.
The printed wiring board 20 is provided with a connector 23 and a pair of differential wiring pattern conductors 22a, 22b. More specifically, the connector 23 functions as a differential circuit component, and handles a differential signal. The paired differential wiring patterns 22a, 22b each has one terminal jointed to the paired solder balls 18 of the BGA component 10 and the other terminal connected to a terminal of the connector 23.
A component mounting surface of the printed wiring board 20 is mounted with the BGA component 10. The solder balls 18 of the BGA component 10 are soldered to one terminal of the differential wiring pattern conductors 22a, 22b. The differential circuit built in the semiconductor chip 11 of the BGA component 10 and the connector handling a differential signal are connected with each other via the foregoing differential lines 14, coupling capacitors 13, differential lines 15, interlayer through vias 16, connection pads 17a, solder balls 18 and differential wiring pattern conductors 22a, 22b, which are arranged on the substrate 12 and a surface of the printed wiring board 20.
The printed wiring board structure shown in
The electronic apparatus shown in
The circuit board 2 configured using the printed wiring board 20 does not requires coupling capacitors on the differential signal transmission path on the circuit board 2. Therefore, it is possible to provide an electronic apparatus 1, which can achieve high density and miniaturization at low cost.
According to the foregoing embodiments, the BOA component 10 is given as an example of the semiconductor package, however, the present invention is not limited to the BGA component. For example, the foregoing embodiments of the present invention are applicable to an area array type semiconductor package such as land grid array (LGA) and pin grid array (PGA).
While certain embodiments of the invention have been described, there embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the invention. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-199342 | Jul 2007 | JP | national |
