Patent Application
20140231977
The present invention is directed to a semiconductor package and, more particularly, to semiconductor packages with low stand-off interconnections between chips.
Multi-functional semiconductor dies, for example microcontroller units (MCUs), microprocessor units (MPUs), memory, and the like, often are packaged with other circuits together in order to produce better system integration and to reduce component size. One conventional method stacks multiple dies in a package and provides bond wires between each die and the supporting substrate or lead frame. This solution can result in lengthy interconnection paths and large package surface areas.
Another type of structure, such as a “flip-chip” or a “chip-to-chip” configuration, allows interconnection among the dies. For example, a base die is connected directly to a top die through solder bumps, copper pillars, or the like, and the base die is wire bonded to the substrate. In this way, a smaller package can be achieved because the wires connecting the top die to the substrate are not present. However, this configuration is not without its disadvantages.
In particular, this configuration can be very costly due to the increase in manufacturing steps and materials. For example, copper pillaring itself is an expensive and time-consuming process. As for the solder bump configuration, many semiconductor dies use bonding pads containing aluminum for making the electrical connections. While aluminum makes a good electrical conductor, the material is not compatible with most solder materials. Thus, before the solder bumps can be bonded to the aluminum pads, the pads must undergo an under bump metallization (UMB) process or the like so that the solder bumps will adequately bond to the aluminum pads.
In addition, formation of solder bumps on the top and/or base dies typically occurs at the wafer-level, i.e., prior to singulation of the individual dies. This subjects the bumps to further processing, increasing the risk and amount of oxidation and other intermetallic compound (IMC) formations. Still further, soldering processes require the use of solder masks, again adding to the cost and materials needed for manufacture.
It is therefore desirable to provide a semiconductor package with a low stand-off and low manufacturing costs.
The present invention is illustrated by way of example and is not limited by embodiments thereof shown in the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. Notably, certain vertical dimensions have been exaggerated relative to certain horizontal dimensions.
In the drawings:
Referring to the drawings, wherein the same reference numerals are used to designate the same components throughout the several figures, there is shown in
The support 12 may alternatively be a laminate substrate, in which case the support 12 is preferably made from polymer-based materials, such as fiberglass, polyimide, or the like, although other types of materials may be used as well. In the case of a laminate substrate, a plurality of electrical conductors (not shown), in the form of copper traces or the like, may be formed on the first and/or second main surfaces 12a, 12b of the support 12. However, the electrical conductors may also be embedded or partially embedded in the support 12. The support 12 may further be coated with a protective layer (not shown), such as a lacquer-like layer of polymer that can be used to provide a permanent protective coating for the electrical conductors.
It should be noted that the support 12 is not so limited and may alternatively be comprised of other structures and include other materials than those described above.
Each package 10 further includes a first or base semiconductor die 14 having opposing first and second main surfaces 14a, 14b. The first semiconductor die 14 is preferably formed from any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. In the configuration shown in
In the configuration shown in
Electrical connection between the first semiconductor die 14 and the support 12 is preferably made using at least one wire 16. Preferably, a first end 16a of the wire 16 is bonded to the first main surface 14a of the first semiconductor die 14 and a second end 16b of the wire 16 is bonded to the first main surface 12a of the support 12. However, other connection points for the wire 16 on the first semiconductor die 14 and the support 12 may be used as well. The wires 16 are preferably in the form of gold wires attached via a conventional wire bonding process, although other materials and attachment techniques may be used. Electrical interconnections between the support 12 and the first semiconductor die 14 may alternatively be made through other structures, such as solder balls or the like.
To facilitate the attachment of the wires 16, the first main surface 14a of the first semiconductor die 14 preferably includes pads 18 disposed on the first main surface 14a or at least partially embedded therein. The pads 18 are preferably formed of aluminum, although other materials exhibiting good electrical conductance may be used as well.
The pads 18 may also be used for the formation of one or more stud bumps 20 on the first main surface 14a of the first semiconductor die 14. The stud bumps 20 are preferably formed of a copper (Cu) material to enable the use of solder filler particles in an adhesive 32 (
The second or top semiconductor die 22 having first and second opposing main surfaces 22a, 22b is also provided. Like the first semiconductor die 14, the second semiconductor die 22 is preferably formed from any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
The second main surface 22b of the second semiconductor die 22 preferably includes one or more electrical conductors 24, which may be disposed on the second main surface 22b or at least partially embedded therein. The electrical conductors 24 are preferably formed by an electroless nickel immersion gold (ENIG) process, elecroless tin plating, or the like. The electrical conductors 24 facilitate electrical connections to the stud bumps 20 on the first main surface 14a of the first semiconductor die 14. Through bonding of the electrical conductors 24 of the second main surface 22b of the second semiconductor die 22 to the stud bumps 20, electrical connection to the first semiconductor die 14 is established. Moreover, the stud bumps 20 may provide an indirect electrical connection for the second semiconductor die 22 to the support 12.
The package 10 further includes a mold compound 26 that is disposed on the first main surface 12a of the support 12 and encapsulates the first and second semiconductor dies 14, 22, the wires 16, and the stud bumps 20. The mold compound 26 may be made from a ceramic material, a polymeric material, or the like.
Additional dies (not shown) can also be added, prior to encapsulation, using the techniques described herein. For example, one or more additional dies may be attached to the first main surface 22a of the second semiconductor die 22 using additional stud bumps (not shown).
Referring now to
Any or all steps in the preparation of the second semiconductor die 22 may take place before, simultaneously with, or after preparation of the support 12 and first semiconductor die 14 described below.
Referring to
Referring to
While this process may be performed at the wafer level, it is preferred that the stud bumps 20 are formed after the first semiconductor die 14 has been singulated. The stud bumps 20 are therefore subjected to fewer processing steps than conventional connections to the first semiconductor die 14, which reduces oxidation and/or IMC formation on the stud bumps 20.
Referring to
Referring to
Referring to
As previously described, additional dies (not shown) may be attached to the second semiconductor die 22 using similar techniques prior to encapsulation.
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.
Those skilled in the art will recognize that boundaries between the above-described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Further, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
The terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
In the claims, the word ‘comprising’ or ‘having’ does not exclude the presence of other elements or steps then those listed in a claim. Further, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
