Patent Application
20210296253
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-046781, filed on Mar. 17, 2020; the entire contents of which are incorporated herein by reference.
Embodiments of the present invention relate to a semiconductor storage device and a manufacturing method of the same.
For semiconductor storage devices such as three-dimensional memories, there is known a technology of bonding metal pads respectively formed on two wafers together. With this technology, dishing arises when the metal pads are polished too much.
Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments.
A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.
The array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating layer 12 (for example, a silicon nitride film) on the memory cell array 11, an insulating layer 13 (for example, a silicon oxide film) on the insulating layer 12, and an interlayer insulating film 14 beneath the memory cell array 11.
Moreover, the array chip 1 includes, as electrode layers in the memory cell array 11, a plurality of word lines WL, a buried source line BSL and a selection gate SG. In a step structure part 21 of the memory cell array 11, each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. Likewise, the buried source line BSL is electrically connected to a source line 25 via a contact plug 24, and the selection gate SG is electrically connected to a selection gate wiring layer 27 via a contact plug 26. Columnar parts CL penetrating the word lines WL, the buried source line BSL and the selection gate SG are electrically connected to bit lines BL via plugs 28.
Furthermore, the array chip 1 includes a pad 41 electrically connected to a wiring layer 37 via a not-shown via plug, an external connection electrode 42 provided on the pad 41, and an external connection pad 43 provided on the external connection electrode 42. The external connection pad 43 can be connected to a mount substrate and/or another device via solder balls, metal bumps, bonding wires or the like.
The circuit chip 2 is provided beneath the array chip 1 via an insulating layer 15. The circuit chip 2 includes an interlayer insulating film 16 and a substrate 17 beneath the interlayer insulating film 16. The substrate 17 is exemplarily a semiconductor substrate such as a silicon substrate. In the following description, directions which are parallel to a surface of the substrate 17 and perpendicular to each other are regarded as an X-direction and a Y-direction, and the direction perpendicular to the surface of the substrate 17 is regarded as a Z-direction. While in the present specification, the +Z-direction is regarded as an upward direction and the −Z-direction is regarded as a downward direction, the −Z-direction may coincide or does not have to coincide with the direction of gravity.
Moreover, the circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 provided on the substrate 17 via a gate insulating film, and not-shown source diffusion layer and drain diffusion layer provided in the substrate 17. Moreover, the circuit chip 2 includes a plurality of plugs 33 provided on the source diffusion layers or the drain diffusion layers, a wiring layer 34 provided on these plugs 33, and a wiring layer 35 provided on the wiring layer 34. The transistors 31, the plugs 33, the wiring layer 34 and the wiring layer 35 constitute a circuit electrically connected to the memory cell array 11.
A plurality of metal pads 36 are provided on the wiring layer 35. Each metal pad 36 is enclosed by the insulating layer 15. The wiring layer 37 of the array chip 1 is provided on the metal pads 36.
The columnar part CL includes a block insulating film 52 which is exemplarily a first insulating film, a charge storage layer 53, a tunnel insulating film 54 which is exemplarily a second insulating film, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is exemplarily a silicon nitride film and is formed on lateral surfaces of the word lines WL and the insulating layers 51 via the block insulating film 52. The channel semiconductor layer 55 is exemplarily a silicon layer and is formed on a lateral surface of the charge storage layer 53 via the tunnel insulating film 54. The block insulating film 52, the tunnel insulating film 54 and the core insulating film 56 are exemplarily silicon oxide films and/or metal insulating film.
Hereafter, a manufacturing method of the semiconductor storage device according to the present embodiment is described.
First, an array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2 are formed as shown in
Meanwhile, a second insulating layer 61 and a plurality of second metal pads 62 are formed at the upper surface of the circuit wafer W2. The second metal pads 62 are formed on the upper surface of the wiring layer 35. Herein, a manufacturing method of the second metal pads 62 is described in detail with reference to
First, second metal pads 62a a main component of which is copper (Cu) is formed on the wiring layer 35. After the second metal pads 62a are polished afterward, there occasionally arises dishing resulting from the upper surfaces of the second metal pads 62a being recessed relative to the upper surface of the second insulating layer 61 as shown in
Therefore, in the present embodiment, as shown in
Subsequently, a thermal treatment is performed to heat the second metal pad 62a. As a result, as shown in
Meanwhile, the first metal pad 72 can also be formed similarly to the second metal pad 62. Namely, when dishing has arisen in polishing the first metal pad 72 a main component of which is copper, by performing the aforementioned alkanethiol treatment and thermal treatment, the first metal pad 72 including carbon as an impurity is formed. In this case, the lower surface of the first metal pad 72 becomes a flat surface positioned at substantially the same height as that of the lower surface of the first insulating layer 71. Moreover, the first metal pad 72 also has a concentration gradient at which a carbon concentration is lowered as advancing in the thickness direction (Z-direction) from its surface (lower surface), that is, as separating in a depth direction apart from the surface.
After the first metal pads 72 and the second metal pads 62 are formed as above, the array wafer W1 and the circuit wafer W2 are pasted together under mechanical pressure. Thereby, the first insulating layer 71 and the second insulating layer 61 are adhesively bonded together to form the insulating layer 15.
Next, the array wafer W1 and the circuit wafer W2 are annealed, for example, at 400° C. Thereby, the first metal pads 72 and the second metal pads 62 are bonded together to form the plurality of metal pads 36.
After the metal pads 36 are formed, the substrate 18 is removed by chemical mechanical polishing (CMP) or wet etching, and the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. As above, the semiconductor storage device in
According to the present embodiment, the volumes of the metal pads are increased by introducing carbon as an impurity to the metal pads and performing a thermal treatment. Therefore, even when dishing arises due to polishing the metal pads, the volumes of the metal pads can be increased. Thereby, defective bonding between the array chip 1 and the circuit chip 2 can be reduced.
Notably, while in the present embodiment, carbon is introduced to both the first metal pads 72 and the second metal pads 62, such introductions of carbon may be determined depending on the degrees of recess of the metal pads. Therefore, carbon may be introduced to either the first metal pads 72 or the second metal pads 62 depending on the degrees of recess of the metal pads.
Moreover, while in the present embodiment, the thermal treatment is performed before the array wafer W1 and the circuit wafer W2 are bonded together when the first metal pads 72 and the second metal pads 62 are formed, it may be performed in bonding these wafers. Since both wafers are annealed, for example, in 400° C. heat in bonding these array wafer W1 and circuit wafer W2 together, this annealing may be used for the thermal treatment. Since also in this case, the volumes are increased through diffusion of carbon having been introduced as the impurity, the first metal pads 72 and the second metal pads 62 can be bonded together with no gaps as shown in
Hereafter, a second embodiment is described mainly on its differences from the first embodiment. The present embodiment is different from the first embodiment in manufacturing methods of the first metal pads 72 and the second metal pads 62. A manufacturing method of the second metal pad 62 in the present embodiment is hereafter described with reference to
When dishing arises on the second metal pad 62a as shown in
Cu+AgNO3→2Ag+Cu(NO3)2 (1)
The aforementioned substitution reaction allows silver to be precipitated on the surface of the second metal pad 62a to form a silver layer 63 as shown in
Next, a thermal treatment is performed to heat the second metal pad 62a. As a result, as shown in
Meanwhile, the first metal pad 72 can also be formed similarly to the second metal pad 62. Namely, when dishing has arisen in polishing the first metal pad 72 a main component of which is copper, by performing the aforementioned substitution reaction and thermal treatment, the first metal pad 72 including silver as an impurity is formed. In this case, the lower surface of the first metal pad 72 becomes a flat surface positioned at substantially the same height as that of the lower surface of the first insulating layer 71 similarly to the first embodiment. Moreover, the first metal pad 72 also has a concentration gradient at which a silver concentration is lowered as advancing in the thickness direction (Z-direction) from its surface (lower surface).
After that, similarly to the first embodiment, the array wafer W1 and the circuit wafer W2 are pasted together under mechanical pressure to form the insulating layer 15. Furthermore, the array wafer W1 and the circuit wafer W2 are annealed, for example, at 400° C. to form the plurality of metal pads 36.
According to the present embodiment, the volumes of the metal pads are increased by introducing silver as an impurity to the metal pads and performing a thermal treatment. Therefore, even when dishing arises due to polishing the metal pads, the volumes of the metal pads can be increased. Thereby, defective bonding between the array chip 1 and the circuit chip 2 can be reduced.
Notably, while in the present embodiment, silver nitrate is introduced to the second metal pads 62a, silver chloride (AgCl) may be introduced in place of silver nitrate. Since silver is precipitated on the surfaces of the second metal pads 62a also in this case, the thermal treatment can increase the volumes of the second metal pads 62a.
Moreover, as to the introduction of silver nitrate or silver chloride, it may be introduced to either the first metal pads 72 or the second metal pads 62 depending on the degrees of recess of the metal pads after polishing similarly to the first embodiment.
Hereafter, a third embodiment is described mainly on its differences from the first embodiment. The present embodiment is different from the first embodiment in manufacturing methods of the first metal pads 72 and the second metal pads 62. A manufacturing method of the second metal pad 62 in the present embodiment is hereafter described with reference to
When dishing arises on the second metal pad 62a as shown in
Meanwhile, the first metal pad 72 can also be formed similarly to the second metal pad 62. Namely, when dishing has arisen in polishing the first metal pad 72 a main component of which is copper, by performing the aforementioned thermal treatment under a silane atmosphere, the first metal pad 72 including silicon as an impurity is formed. In this case, the lower surface of the first metal pad 72 becomes a flat surface positioned at substantially the same height as that of the lower surface of the first insulating layer 71 similarly to the first embodiment. Moreover, the first metal pad 72 also has a concentration gradient at which a silicon concentration is lowered as advancing in the thickness direction (Z-direction) from its surface (lower surface).
After that, similarly to the first embodiment, the array wafer W1 and the circuit wafer W2 are pasted together under mechanical pressure to form the insulating layer 15. Furthermore, the array wafer W1 and the circuit wafer W2 are annealed, for example, at 400° C. to form the plurality of metal pads 36.
According to the present embodiment, the volumes of the metal pads are increased by introducing silicon as an impurity to the metal pads. Therefore, even when dishing arises due to polishing the metal pads, the volumes of the metal pads can be increased. Thereby, defective bonding between the array chip 1 and the circuit chip 2 can be reduced.
Notably, while in the present embodiment, the thermal treatment is performed under a silane atmosphere, the thermal treatment may be performed under a disilane (Si2H6) atmosphere. Since silicide in which copper combines with silicon diffuses in the second metal pads 62a also in this case, the volumes of the second metal pads 62a can be increased.
Moreover, in the present embodiment, the thermal treatment under a silane atmosphere or a disilane atmosphere may be performed in bonding the array wafer W1 and the circuit wafer W2 together. Since the array wafer W1 and the circuit wafer W2 are annealed, for example, in 400° C. heat in bonding the array wafer W1 and the circuit wafer W2 together, this annealing may be used for the thermal treatment of the metal pads. Since diffusion of silicon introduced as the impurity increases the volumes of the metal pads also in this case, the first metal pads 72 and the second metal pads 62 can be bonded together with no gaps as shown in
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-046781 | Mar 2020 | JP | national |
