Patent Application
20210151349
The present application claims priority to Chinese Patent Application No. 201811637245.X, filed on Dec. 29, 2018, entitled “SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF”, which is incorporated by reference herein for all purposes.
The present disclosure relates to a semiconductor structure and a method of fabricating the same, and in particular to a VIA structure and a method of fabricating the same.
Since the disclosure of integrated circuits by Dr. Jack Kilby of Texas Instruments in early years, scientists and engineers have made numerous disclosures and improvements in semiconductor devices and processes. Over 50 years, the dimensions of semiconductors have been significantly reduced, which translates into an increasing processing speed and decreasing power consumption. To date, the development of semiconductors has largely followed Moore's Law, which roughly states that the number of transistors in dense integrated circuits doubles about every two years. At present, semiconductor processes are developing toward below 20 nm, and some companies are embarking on 14 nm processes. Just to provide a reference herein, a silicon atom is about 0.2 nm, which means that the distance between two separate components manufactured by a 20 nm process is about only one hundred silicon atoms. Semiconductor device manufacturing has therefore become increasingly challenging and advancing toward the physically possible limit.
How to improve the performance of 28 nm semiconductor devices has become a top priority in the semiconductor manufacturing industry, and it is also a huge challenge. At present, the performance of a 28 nm semiconductor device can be improved by reducing the resistance of a Kelvin VIA in the metal layer of the back surface of the semiconductor device. Amplifying the feature size (also known as CD, Critical Dimension)) of the Kelvin VIA is considered to be an effective method in reducing the resistance of the Kelvin VIA.
However, as previously mentioned, in the case where the feature sizes of the semiconductor devices are increasingly shrinking, the feature size of the enlarged Kelvin VIAs means the possibility of short circuiting with the Kelvin VIAs and other VIAs or metal wires in the back metal layer is greatly increased, resulting in a decrease in the yield of the semiconductor device.
Furthermore, it is the most common practice to modify the layout of the device by modifying the mask to achieve a method of amplifying the feature size of the Kelvin VIA. However, since the particularity of the Kelvin VIA position that is located in a turning area, changing the feature size of a Kelvin VIA requires extensive modification of the layout of the entire semiconductor device, to increase the cost of the semiconductor device manufacturing process.
Therefore, there is a need for a method of fabricating a semiconductor structure that can reduce the resistance of the Kelvin VIA by changing the feature size of the Kelvin VIA without changing the mask. At the same time, the appearance of the Kelvin VIA fabricated by the above manufacturing method does not increase the possibility of short circuiting with other VIAs or metal lines in the back metal layer to ensure the yield of the semiconductor structure.
A brief summary on one or more aspects is given below to provide the basic understanding for these aspects. This summary is not an exhaustive overview of all the contemplated aspects and is neither intended to indicate critical or decisive elements of all aspects nor to attempt to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a preface for a more detailed description presented later.
As described above, in order to solve the above problems, the present disclosure provides a method of manufacturing a semiconductor structure for forming a VIA going throughout a dielectric layer along a height direction of the semiconductor structure, the method of manufacturing comprising:
providing a substrate, and a front device of the semiconductor structure is formed in the substrate, the front device is electrically connected to a back metal wire of the semiconductor structure through the VIA, and an upper portion of the substrate is formed with the dielectric layer covering the substrate; performing a first etching process in a position corresponding to the front device, the first etching process forms a partial VIA in an upper portion of the dielectric layer; and performing a second etching process, the second etching process enable the VIA go throughout the dielectric layer in the height direction to expose the front device, and a first dimension of the cross section of the formed VIA orthogonal to the height direction in an extending direction of the above-mentioned back metal wire is greater than a second dimension in an direction vertical to the extending direction by performing the first etching process and the second etching process.
In the above embodiment, the first etching process comprises using a gas combination comprising CF4 gas, and the CF4 gas accounts for 20-35% of the gas combination.
In the above embodiment, the CF4 gas accounts for 28% of the gas combination.
In the above embodiment, the second etching process comprises setting the dissociation power of the etching gas to 270-350 W.
In the above embodiment, the set dissociation power is 280-330 W.
In the above embodiment, the dissociation of the set power 300 W.
In the above embodiment, said second etching process comprises using a gas combination comprising CF4 gas, and the CF4 gas accounts for 25-40% of the gas combination.
In the above embodiment, the CF4 gas accounts for 35% of the gas combination.
In the above embodiment, a ratio of the first dimension to the second dimension is greater than 1.2.
In the above embodiment, the ratio of the first dimension to the second dimension is 1.2-1.5.
In the above embodiment, performing the second etching process further comprises forming a trench in an upper portion of the dielectric layer, and the back metal wire is formed in the trench; and the manufacturing method further comprises forming a patterned hard mask layer on an upper surface of the dielectric layer before performing the second etching process, the patterned hard mask layer defining an etching pattern of the trench.
In the above embodiment, the hard mask layer is a metal mask, and/or the hard mask layer is made of TiN.
In the above embodiment, and a ratio of the first dimension to the second dimension is 1.5-1.8.
The disclosure also provides a semiconductor structure including a VIA going throughout a dielectric layer in a height direction of the semiconductor structure, the VIA interconnecting a front device of the semiconductor structure and a back metal wire of the semiconductor structure, a first dimension of the cross section of the VIA orthogonal to the height direction in an extending direction of the back metal wire is larger than a second dimension in an direction vertical to the extending direction.
In the above embodiment, a ratio of the first dimension to the second dimension is greater than 1.2.
In the above embodiment, the ratio of the first dimension to the second dimension is 1.2-1.5.
In the above embodiment, the ratio of the first dimension to the second dimension is 1.5-1.8.
According to the semiconductor structure and the method of fabricating the same provided by the present disclosure, the feature size of the VIA is increased by adjusting the etching process, and the cross-section of the VIA is maintained in one direction larger than the other in the vertical direction. Therefore, short circuit between the VIA and other VIAs or metal lines is not caused due to the increase of the feature size, to ensure the yield of the semiconductor structure.
The following description is presented to enable one of ordinary skill in the art to implement and use the present disclosure and incorporate it into the context of a particular application. Various modifications, as well as various usages in various applications, will be readily apparent to those skilled in the art, and the generic principles defined herein may be applicable to a wide range of embodiments. Thus, the present disclosure is not limited to the embodiments presented herein, but rather should be given its broadest scope consistent with the principles and novel features disclosed herein.
In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without limitations from these specific details. In other words, well-known structures and devices are shown in a block diagram form and are not shown in detail, to avoid obscuring the present disclosure.
The reader is cautioned as to all files and documents which are filed at the same time as this specification and which are open for the public to consult, and the contents of all such files and documents are incorporated herein by reference. Unless directly stated otherwise, all features disclosed in this specification (including any of the appended claims, the abstract, and the accompanying drawings) may be replaced by alternative features serving the same, equivalent, or similar purposes. Therefore, unless expressly stated otherwise, each of the features disclosed is only one example of a group of equivalent or similar features.
Note that when used, the flags left, right, front, back, top, bottom, front, back, clockwise, and counter-clockwise are used for convenience purposes only and do not imply any specific fixed direction. In fact, they are used to reflect the relative position and/or direction between various parts of an object.
As used herein, the terms “over . . . “under . . . ”, “between . . . and . . . ”, and “on . . . ” means the relative position of that layer relative to another layer. Likewise, for example, a layer that is deposited or placed over or under another layer may be in direct contact with another layer or there may be one or more intervening layers. In addition, a layer that is deposited or placed between layers may be in direct contact with the layers or there may be one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with the second layer. In addition, a relative position of a layer relative to another layer is provided (assuming that film operations of deposition, modification, and removal are performed in relative to a starting substrate, without considering the absolute orientation of the substrate).
As described above, in order to change the feature size of the Kelvin VIA without changing the mask, the present disclosure provides a manufacturing method by adjusting the etching process. To get the manufacturing method, all experiments were performed on TEL Tactras™ Vigus chamber, which is a typical capacitive coupled plasma (CCP) etcher with superimposed direct current (DC), with dual RF power with 40 MHz and 13 MHz applied at bottom electrode. The cross-sections of devices and critical dimension (CD) of devices of the experiments have been confirmed by transmission electron microscope (TEM) and CDSEM.
Please refer to
The drawings are provided for illustration only and should not unduly limit the scope of the claims. Those skilled in the art will appreciate that there are many alternatives, and variations. One or more steps may be added, removed, repeated, rearranged, modified, replaced, and/or overlap depending on the implementation and this does not affect the scope of the claims.
As shown in
Further, the back metal wire to be formed in the present disclosure and the back metal layer in which the VIA is located are formed by using the dielectric layer 400 as an intermediate dielectric layer, that is, the VIA formed by the present disclosure is to go throughout the dielectric layer 400.
Those skilled in the art will appreciate that the above-described manufacturing process for forming a dielectric layer on the front device layer, then etching the dielectric layer to form VIAs or trenches, and filling the VIAs or trenches with the metal dielectric is a damascene process. The manufacturing method of the present disclosure is constructed in a damascene process, but is different from the existing damascene process by improving the process therein.
With further reference to
Although partial VIA needs to be formed first, at the beginning of the process step, a hard mask layer of trenches including the hard mask layer 700 shown in
Those skilled in the art will appreciate that the above patterning process may include photo-resist coating (e.g., spin coating), soft bake, photo-mask alignment, exposure, post-exposure bake, photo-resist development, rinsing, drying (e.g., hard roasting), other suitable processes, and/or combinations of the foregoing. Moreover, the above etching process can also be performed by existing or future processes, and details are not described herein again.
With further reference to
As described above, Kelvin VIAs are through holes at the turning point, if the shape of the through hole is changed by changing the layout of the mask, the design of the parts adjacent to the Kelvin VIA needs to be changed accordingly, so the manufacturing cost is greatly increased. Therefore, the photo-mask used in patterning the patterned photo-resist layer 912 as shown in
Please further refer to
Further, the above gas combination may further include other etching gases such as C4F8, O2, Ar, and the like. Those skilled in the art should know that the gas composition and the proportion of other gases of the above gas combination can be adjusted according to actual conditions, but it is necessary to ensure that the proportion of CF4 gas in the above gas combination used in the first etching step is 20%-35%, and in one embodiment 28%.
Please refer to
With further reference to
The etching process parameters adopted in the above-mentioned steps of the manufacturing method of the present disclosure include etching the VIAs and the trenches by using a gas combination containing CF4 gas playing the role of bringing out the product during the etching process. Still further, in the gas combination containing CF4 gas used in this step, the proportion of CF4 is 25%-40%, and in one embodiment the ratio of the CF4 gas is 35%. It should be noted that in this step, the proportion of CF4 in the gas combination used in the method of the present disclosure is much larger than the proportion of CF4 gas in the gas combination used in the conventional etching VIA process. Moreover, it is further higher than the proportion of CF4 gas set in the first etching process of the manufacturing method of the present disclosure. Therefore, in this step, the feature size of the etched VIA can be increased due to the function of the CF4 gas of taking the product out.
Further, in the second etching process of the manufacturing method of the present disclosure, the etching process parameters used further include adjusting the dissociation power of the etching gas to be between 270-350 W. By reducing the dissociation power to reduce the ion bombardment energy, the etching ability of the VIA can be improved. In one embodiment, in this step, the dissociation power of the etching gas can be adjusted between 280-330 W, and within the above range, in one embodiment, the dissociation power of the etching gas can be adjusted to 300 W to balance etching ability and ability to take out residual products.
Please refer to
As shown in
Since the formed Kelvin VIA is located above the trench, the appearance of the Kelvin VIA here is also subject to the patterning of the trench. As described above, the manufacturing method of the present disclosure defines a pattern of trenches by using a patterned hard mask layer, that is, a hard mask layer is formed in a light gray portion as in
As described above, since the metal hard mask layer (which can be TiN material) is additionally provided, as a substitute for the photo-resist, to be a mask for the trench, the hard mask layer is more protective in the X direction. By using the first etching process and the second etching process of the present disclosure, the ratio of the first dimension in the Y direction of the formed VIA to the second dimension in the X direction can be in the range of 1.5-1.8.
Through experiments, even if a hard mask layer is not used, it is still possible to use the photo-resist having weak protection ability to achieve the ratio of the first dimension in the Y direction of the formed VIA to the second dimension in the X direction in the range of 1.2-1.5 by the first etching process and the second etching process provided by the present disclosure.
By the first etching process and the second etching process condition improved by the present disclosure, the size of the VIA in the extending direction of the back metal wire can be made larger than the dimension in direction perpendicular to the extending direction. Therefore, a short circuit between the VIA and other VIA or between the VIA and the back metal wire would not be caused, and the yield of the semiconductor device can be ensured.
At the same time, since the cross-sectional area of the cross-section of the VIA is increased, the impedance value of the metal medium in the VIA can be reduced, so that the performance of the semiconductor device can be effectively improved.
As can be seen from
The present disclosure also provides a semiconductor structure formed by the above manufacturing method, the semiconductor structure including a VIA going throughout a dielectric layer in a height direction of the semiconductor structure, the VIA interconnecting a front device of the semiconductor structure and a back metal wire of the semiconductor structure, a first dimension of the cross section of the VIA orthogonal to the height direction in an extending direction of the back metal wire is larger than a second dimension in an direction vertical to the extending direction.
Further, the ratio of the first dimension to the second dimension is greater than 1.2.
Further, the ratio of the first dimension to the second dimension is 1.2-1.5.
In one embodiment, the ratio of the first dimension to the second dimension described above can be made 1.5-1.8 by using a metal hard mask layer during the etching process.
By the increase in the feature size of the VIA, the resistance of the metal medium located in the VIA can be lowered. And the cross-section of the VIA is kept in a dimension larger than the dimension in the other vertical direction, so that the short-circuiting between the VIA and the other VIA or the metal wire is not caused by the increase of the feature size, guaranteeing the yield of the semiconductor structure.
Although the present disclosure has been described with respect to certain exemplary embodiments, it will be apparent that various modifications and changes may be made to these embodiments without departing from the more general spirit and scope of the disclosure. Accordingly, the specification and the accompanying drawings are to be regarded in an illustrative rather than a restrictive sense.
It is to be understood that this description is not intended to explain or limit the scope or meaning of the claims. In addition, in the detailed description above, it can be seen that various features are combined together in a single embodiment for the purpose of simplifying the disclosure. The method of the present disclosure should not be interpreted as reflecting the intention that the claimed embodiments require more features than those expressly listed in each claim. Rather, as reflected by the appended claims, an inventive subject matter lies in being less than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
One embodiment or embodiments mentioned in this description is/are intended to be, combined with a particular feature, structure, or characteristic described in the embodiment, included in at least one embodiment of a circuit or method. The appearances of phrases in various places in the specification are not necessarily all referring to a same embodiment.
