Patent Application
20250015179
This application claims the benefit of People's Republic of China patent application Serial No. 202310802694.X, filed Jul. 3, 2023, the invention of which are incorporated by reference herein in its entirety.
This disclosure relates to a semiconductor structure and a method for fabricating the same, in particular to a semiconductor structure including a separated gate and a method for fabricating the same.
With the development of integrated circuit technology, composite semiconductor structures with different transistors have become one of the most important structures in integrated circuits. In a composite semiconductor structure, different transistors are required to provide different critical voltages.
For example, for a transistor that is subjected to a higher voltage, a thicker gate insulating layer is usually used to avoid the electrical breakdown of other core areas which may not withstand the high voltage. However, a gate insulating layer that is too thick does not allow for the desired switching current. In addition, as the critical dimensions of semiconductor structures shrink, the integrated circuits become denser and the process steps more complex.
This disclosure relates to a semiconductor structure and a method for fabricating the same, capable of withstanding high voltage and having better electrical performance, and solving the problems of flatness and high/low landing contacts caused by the existing manufacturing process.
According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, a source region, a drain region and a gate structure. The source region is located in the substrate. The drain region is located in the substrate. The gate structure is disposed on the substrate and located between the source region and the drain region, and includes a first sub-gate structure and a second sub-gate structure. The first sub-gate structure is adjacent to the source region and includes a first sub-gate insulating layer. The second sub-gate structure is adjacent to the drain region and includes a second sub-gate insulating layer. The second sub-gate insulating layer and the first sub-gate insulating layer are separated from each other. The first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness greater than the first thickness.
According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate has a first element area and a second element area. The first transistor is formed in the first element area of the substrate, and includes a first gate structure. The first gate structure includes a first sub-gate insulating layer and a second sub-gate insulating layer separated from each other. The first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness greater than the first thickness. The second transistor is formed in the second element area of the substrate, and includes a second gate structure. The second gate structure includes a second gate insulating layer having a third thickness substantially equal to the first thickness.
According to still another aspect of the present disclosure, a method for fabricating a semiconductor structure is provided. The method includes the following steps. First, a substrate is provided. The substrate includes a first element area and a second element area. Then, a first transistor and a second transistor are respectively formed in the first element area and the second element area of the substrate. The first transistor includes a first gate structure. The first gate structure includes a first sub-gate insulating layer and a second sub-gate insulating layer separated from each other. The first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness greater than the first thickness. The second transistor includes a second gate structure. The second gate structure includes a second gate insulating layer. The first sub-gate insulating layer and the second gate insulating layer are formed by patterning the same gate insulation material layer.
The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
Each embodiment of the present disclosure will be described in detail hereinafter, and illustrated with drawings. In addition to these detailed descriptions, the disclosure may be broadly implemented in other embodiments, and any easily substituted, modified, or equivalent variations of the described embodiments are included within the scope of the present disclosure, which is subject to the scope of the claims thereafter. In the description of the specification, many specific details and examples of embodiments are provided in order to provide the reader with a more complete understanding of the disclosure; however, these specific details and examples of embodiments should not be considered as limitations of the disclosure. In addition, well-known steps or elements are not described in detail to avoid unnecessary limitations of the present disclosure.
It should be noted that the drawings of the present disclosure are simplified in order to clearly illustrate the contents of the embodiments and to highlight the features of the present disclosure, and the dimensions on the drawings are not drawn to the same scale as the actual product. Accordingly, the specification and the drawings are for the purpose of describing the embodiments only and are not intended to limit the scope of the disclosure. Identical or similar element symbols are used to represent identical or similar elements.
In addition, the terms such as “first”, “second”, “third”, etc. used in the specification and the claims are for the purpose of distinguishing different elements, and they do not imply and represent any previous sequence of the elements, nor do they represent the sequence of an element and another element, or the sequence of the manufacturing method, and the use of these terms is only for the purpose of making a clear distinction between an element with a certain name and another element with the same name.
Furthermore, the term “thickness” as used herein, if not otherwise specified, refers to a straight distance between the upper and lower surfaces of the referred element structure (e.g., an insulating layer).
Moreover, words of approximation, such as “about,” “almost,” “substantially,” “approximately,” and the like, can be used herein to mean “at,” “near,” “nearly at,” “within 3-5% of,” “within acceptable manufacturing tolerances of,” or any logical combination thereof. Similarly, terms “vertical” or “horizontal” are intended to additionally include “within 3-5% of” a vertical or horizontal orientation, respectively. Besides, for the sake of description, the terms such as “underneath”, “below”, “under”, “above”, “over”, “on”, and other spatial relative terms are used to describe the relationship between one element or feature and other element(s) or feature(s) as shown in the drawings. The spatial relative term is intended to cover different orientations of the element in use or operation, in addition to the orientation shown in the drawings. The element may be oriented in other ways, such as rotated 90 degrees or in other orientations, and again, the spatial relative term used herein may be interpreted accordingly.
The gate structure 110 may include a first sub-gate structure 111 and a second sub-gate structure 112. The first sub-gate structure 111 is adjacent to the source region 113; in contrast, the second sub-gate structure 112 is adjacent to the drain region 114. In addition, the first sub-gate structure 111 and the second sub-gate structure 112 are separated from each other. The first sub-gate structure 111 may include a first sub-gate insulating layer 111a and a first sub-gate electrode layer 111b formed on the first sub-gate insulating layer 111a. The second sub-gate structure 112 may include a second sub-gate insulating layer 112a and a second sub-gate electrode layer 112b formed on the second sub-gate insulating layer 112a.
In one embodiment, the semiconductor structure 110 may further include a connection region 115. The connection region 115 is located in the substrate 111 and connected to the first sub-gate insulating layer 111a and the second sub-gate insulating layer 112a. The connection region 115 may be a heavily doped region, a lightly doped region, or a well region, and may have the same conductivity type as the source region 113 and the drain region 114. For example, when the conductivity type of the source region 113 and the drain region 114 is N-type, the connection region 115 may be heavily doped or lightly doped with an N-type dopant, or form an N-type well region.
In one embodiment, the semiconductor structure 100 may further include a well region 116. The well region 116 is located in the substrate 101, and the source region 113, the drain region 114 and the connection region 115 are located in the well region 116. The well region 116 may have a different conductivity type than the source region 113 and the drain region 114. For example, when the conductivity type of the source region 113 and the drain region 114 is N-type, the well region 116 may be doped with a P-type dopant.
In one embodiment, the semiconductor structure 100 may further include a drift region 117. The drift region 117 is located in the well region 116, the drain region 114 is located in the drift region 117, and the second sub-gate structure 112 is located on an intersection of the well region 116 and the drift region 117. The drift region 117 may have the same conductivity type as the drain region 114 and be lightly doped compared to the drain region 114. For example, when the conductive type of the drain region 114 is N-type, the drift region 117 may be lightly doped with an N-type dopant.
The first sub-gate insulating layer 111a and the second sub-gate insulating layer 112a may have different thicknesses. Further, the first sub-gate insulating layer 111a may have a first thickness H1, and the second sub-gate insulating layer 112a may have a second thickness H2 greater than the first thickness H1. Since the high voltage is typically applied to the drain region 114, the second sub-gate insulating layer 112a closer to the drain region 114 may be formed with a thicker thickness to prevent the second sub-gate insulating layer 112a from breaking due to the high voltage and thus adversely affecting the device characteristics. In addition, the first sub-gate insulating layer 111a that is farther away from the drain region 114 may be formed with a thinner thickness, so that the desired switching current and a better gate control capability may be maintained, thereby improving the electrical performance of the device.
Furthermore, when viewed horizontally from a cross-section of the semiconductor structure 100 (the upper surface 101u extending horizontally and perpendicular to the substrate 101), i.e., when viewed from the drawing of
In one embodiment, the lower surface F1 of the first sub-gate insulating layer 111a and the lower surface F2 of the second sub-gate insulating layer 112a may be located at the upper surface 101u of the substrate 101. In other words, when viewed horizontally from a cross-section of the semiconductor structure 100 (the upper surface 101u extending horizontally and perpendicular to the substrate 101), i.e., when viewed from the drawing of
In detail, referring to
The first element area R1, the second element area R2, and the third element area R3 may respectively have different operating voltage ranges. In one embodiment, the second element area R2 may be a low voltage area, and the second transistor T2 may be a low-voltage transistor, such as a core device. The second transistor T2 may include a second gate structure 120, a source region 123, and a drain region 124. The second gate structure 120 is disposed on the substrate 101 and located between the source region 123 and the drain region 124. The source region 123 and the drain region 124 may be formed in a well region 125. The second gate structure 120, the source region 123, and the drain region 124 may be used as being a gate G2, a source S2, and a drain D2, respectively, via contact plugs (not shown) to receive an externally applied voltage. The second gate structure 120 may include a second gate insulating layer 120a and a second gate electrode layer 120b formed on the second gate insulating layer 120a.
The first sub-gate insulating layer 111a of the first gate structure 110 of the first transistor T1 and the second gate insulating layer 120a of the second gate structure 120 of the second transistor T2 may be the same patterned film layer. That is, the first sub-gate insulating layer 111a and the second gate insulating layer 120a may be fabricated in the same manufacturing process such that the first thickness H1 of the first sub-gate insulating layer 111a is substantially equal to the third thickness H3 of the second gate insulating layer 120a, for example, being less than or equal to 25 angstroms (Å).
The third element area R3 may be a high voltage area, and the third transistor T3 may be an I/O transistor. The third transistor T3 may include a third gate structure 130, a source region 133, and a drain region 134. The third gate structure 130 is disposed on the substrate 101 and located between the source region 133 and the drain region 134. The source region 133 and the drain region 134 may be formed in a well region 135. The third gate structure 130, the source region 133, and the drain region 134 may be used as being a gate G3, a source S3, and a drain D3, respectively, via contact plugs (not shown) to receive an externally applied voltage. The third gate structure 130 may include a third gate insulating layer 130a and a third gate electrode layer 130b formed on the third gate insulating layer 130a.
The second sub-gate insulating layer 112a of the first gate structure 110 of the first transistor T1 and the third gate insulating layer 130a of the third gate structure 130 of the third transistor T3 may be the same patterned film layer. That is, the second sub-gate insulating layer 112a and the third gate insulating layer 130a may be fabricated in the same manufacturing process such that the second thickness H2 of the second sub-gate insulating layer 112a is substantially equal to the fourth thickness H4 of the third gate insulating layer 130a, for example, being less than or equal to 40 angstroms (Å).
The gate structure 210 may include a first sub-gate structure 211 and a second sub-gate structure 212. The first sub-gate structure 211 is adjacent to the source region 113; in contrast, the second sub-gate structure 212 is adjacent to the drain region 114. In addition, the first sub-gate structure 211 and the second sub-gate structure 212 are separated from each other. The first sub-gate structure 211 may include a first sub-gate insulating layer 211a and a first sub-gate electrode layer 211b formed on the first sub-gate insulating layer 211a. The second sub-gate structure 212 may include a second sub-gate insulating layer 212a and a second sub-gate electrode layer 212b formed on the second sub-gate insulating layer 212a.
Similar to the transistor T1 of
Herein, the substrate 101 may have a recess portion R recessed from the upper surface 101u. The lower surface F1′ of the first sub-gate insulating layer 211a may be located at the upper surface 101u of the substrate 101, and the second sub-gate insulating layer 212a may be formed in the recess portion R such that the lower surface F2′ of the second sub-gate insulating layer 212a is located below the upper surface 101u of the substrate 101. Accordingly, the second sub-gate insulating layer 212a may have a second thickness H2′ greater than that of
In one embodiment, the first thickness H1′ of the first sub-gate insulating layer 211a may be the same as the thickness of the gate insulating layer of an I/O transistor, and the second thickness H2′ of the second sub-gate insulating layer 212a may be thicker than the thickness of the gate insulating layer of the I/O transistor to withstand a higher voltage. For example, if the I/O transistor is an I/O device in the I/O area of the semiconductor structure, the first thickness H1′ of the first sub-gate insulating layer 211a may be less than or equal to 40 angstroms (Å), and the second thickness H2′ of the second sub-gate insulating layer 212a may be greater than 40 angstroms (Å). In other embodiments, the first thickness H1′ of the first sub-gate insulating layer 211a may be the same as the thickness of the gate insulating layer of the core device in the core area of the semiconductor structure, for example, being less than or equal to 25 angstroms (Å); and the second thickness H2′ of the second sub-gate insulating layer 212a may be greater than the thickness of the I/O transistor, for example, being greater than 40 angstroms (Å), to withstand a higher voltage.
In detail, referring to
The first element area R1′ and the second element area R2′ may respectively have different operating voltage ranges. In one embodiment, the second element area R2′ may be a high voltage area, and the second transistor T2′ may be an I/O transistor. In another embodiment, the second element area R2′ may be a low voltage area, and the second transistor T2′ may be a low-voltage transistor, such as a core device. The second transistor T2′ may include a second gate structure 220, a source region 123, and a drain region 124. The second gate structure 220 is disposed on the substrate 101 and located between the source region 123 and the drain region 124. The source region 123 and the drain region 124 may be formed in a well region 125. The second gate structure 220, the source region 123, and the drain region 124 may be used as being a gate G2′, a source S2, and a drain D2, respectively, via contact plugs (not shown) to receive an externally applied voltage. The second gate structure 220 may include a second gate insulating layer 220a and a second gate electrode layer 220b formed on the second gate insulating layer 220a.
The first sub-gate insulating layer 211a of the first gate structure 210 of the first transistor T1′ and the second gate insulating layer 220a of the second gate structure 220 of the second transistor T2′ may be the same patterned film layer. That is, the first sub-gate insulating layer 211a and the second gate insulating layer 220a may be fabricated in the same manufacturing process such that the first thickness H1′ of the first sub-gate insulating layer 211a is substantially equal to the third thickness H3′ of the second gate insulating layer 220a. For example, if the second transistor T2′ is an I/O transistor, the first thickness H1′ may be less than or equal to 40 angstroms (Å); if the second transistor T2′ is a core device, the first thickness H1′ may be less than or equal to 25 angstroms (Å).
With respect to the second sub-gate insulating layer 212a of the first gate structure 210 of the first transistor T1′, after the step of forming the recess portion R of the substrate 101, then the second sub-gate insulating layer 212a with thickness thicker than the first thickness H1′ may be formed.
Referring to
Referring to
As described hereinabove, the present disclosure prevents the second sub-gate insulating layer from breaking due to the high voltage, which adversely affects the characteristics of the device, by forming a thicker thickness of the second sub-gate insulating layer closer to the drain region. The present disclosure also enhances the electrical performance of the device by forming a thinner thickness of the first sub-gate insulating layer farther away from the drain region, which preserves the desired switching current and the better gate control capability. In addition, the first sub-gate insulating layer and the second sub-gate insulating layer are separated from each other and fabricated separately to avoid landing contact problems between the first sub-gate electrode layer and the second sub-gate electrode layer.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310802694.X | Jul 2023 | CN | national |
