SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME

FIELD

The present disclosure generally relates to fabrication of semiconductor device, and more particularly pertains to providing interconnect structure for semiconductor device having enhanced electrical characteristics.

BACKGROUND

As integrated circuits (IC) are developed, the desire for higher device density and operation speed becomes never-ending quests for those skilled in the art. With millions of miniature circuit elements connected through a network of interconnect components, the electrical properties of the interconnect structure greatly affect the device performance.

For one thing, diffusion or electromigration of metal materials in the interlayer dielectrics may generate contamination and shorting issues. Moreover, in some applications, different conductive materials are employed in different interconnect components. The interface between different interconnect components where different metal materials meet may encounter intermetallic composites (IMCs) non-uniformity issues that leads to reduced electrical performance.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

FIG. 1 shows a regional cross section view of an exemplary semiconductor device in accordance with some embodiments of the instant disclosure.

FIG. 2 illustrates a schematic regional cross-sectional view of an exemplary interconnect structure.

FIGS. 3(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure.

FIGS. 4(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure.

FIGS. 5(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure.

FIGS. 6(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure.

FIG. 7 illustrates a schematic regional cross-sectional view of an exemplary interconnect structure in accordance with some embodiments of the present disclosure.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

DETAILED DESCRIPTION

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” or “has” and/or “having” when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The description will be made as to the exemplary embodiments in conjunction with the accompanying drawings in FIGS. 1 to 5. Reference will be made to the drawing figures to describe the present disclosure in detail, wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by same or similar reference numeral through the several views and same or similar terminology.

FIG. 1 shows a regional cross section view of a semiconductor device in accordance with some embodiments of the instant disclosure. The exemplary device includes a substrate 100 over which multiple layers of integrated circuit devices and features are formed. For illustrational simplicity and clarity, some detail/sub components of the exemplary device are not explicitly labeled in the instant figure.

The substrate 100 may comprise a crystalline silicon substrate. The substrate may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). The doped regions may be doped with p-type dopant, such as boron or BF2; n-type dopant, such as phosphorus or arsenic; and/or combinations thereof. In some alternative embodiments, the substrate 100 may be made of other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor material, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, SiGeSn, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; other suitable materials; or combinations thereof. Furthermore, although a bulk substrate is utilized in the instant illustrative example, in some embodiments, the substrate may include an epitaxial layer (epi-layer) and/or may include a silicon-on-insulator (SOI) structure, such as a silicon-on-insulator (SOI) structure, SiGe-on insulator (SiGeOI), Ge on insulator (GeOI) and the like.

Several functional regions may be arranged laterally (e.g., horizontally across the page as shown in FIG. 1) over the substrate. By way of example, FIG. 1 shows a substrate of an exemplary device that includes two co-planar arranged functional regions defined thereon, e.g., a cell region 110 and a periphery region 120. In the illustrated example, the cell region 110 provides space to accommodate active circuit components (e.g., selection transistor 112) and passive circuit components (e.g., storage element, such as capacitor 116) of a dynamic random access memory (DRAM) device. Meanwhile, the periphery region 120 houses circuit components for supporting various functions of the DRAM operation, such as read out circuits, decoder circuits, and amplifier circuits. Different functional regions may include circuit components of different critical dimensions based on different design rules. The devices in different functional regions may be designed to function under different operational requirements (e.g., different voltage rage). Devices of different feature dimensions may be arranged on the same plane of a substrate (e.g., circuit chip) to achieve higher degree of integration, hence reduce signal path and enhance device performance.

The cell region may comprise array of memory unit cells. Each of the memory cell units typically includes a bit storage component (e.g., storage capacitor 116) and a selection component (e.g., transistor 112). The unit cells may employ suitable cell architecture, e.g., a 1-T cell format (as shown in the instant example) or other types of cell arrangement (such as a 3T cell layout, not shown). The cell region 110 of the illustrated device are shown to have two gate structures 112 embedded (buried) under a top surface of the substrate 100 in an active area that rests between isolation features 111 (e.g., shallow trench isolation (STI) structure). In some embodiments, the active area may be a raised island structure (with respect to a lower surface of the substrate) comprising an elongated strip overhead profile and surrounded by isolation structure (e.g., STI 111). In some embodiments, the active area may be obliquely arranged with respect to the traversing direction of a word line (e.g., the extending direction of the gate structure 112, which is in/out of the page in the illustrated example) at a slanting angle. The oblique arrangement of the active areas in folded/offset layout may allow more units cells to be packed in a same area while maintaining sufficient distance there-between, thus achieving higher device density while reducing inter-cell interference (e.g., cross talk).

The gate structure 112 may be part of a memory cell selection device, such as a buried channel array transistor (BCAT). In the illustrated example, the active area (defined between a pair of isolation features 111) comprises a pair of gate structures 112 (corresponding to a pair of BCATs whose respective source/drain (S/D) regions connected to a contact plug, e.g., contact plug/via 114). The contact plug 114 enables electrical connection between the selection transistor (e.g., BCAT) to a lower electrode (e.g., 116L) of a storage capacitor 116 (e.g., through a pad not specifically labeled). The gate structure 112 of an exemplary buried type device may comprise a recess-filling structure (in a cross sectional profile) buried in a gate trench in the active area of the substrate. In DRAM applications, the gate structure 112 may be a laterally traversing linear structure (e.g., extending in/out of the page of, e.g., FIG. 1) that intercepts multiple adjacent active areas (and serves as a word line (WL) for a memory device).

The gate structure 112 comprises a gate electrode (not labeled) embedded at a lower portion of the gate trench (e.g., partially filling) in the active area. The gate electrode may include one or more conductive material such as doped polysilicon, or metal material such as tungsten, ruthenium, and cobalt. The gate structure 112 also comprises a gate insulation liner that lines the bottom portion of the trench, and is arranged between the gate electrode and the semiconductive material of the active area. The gate insulation liner may be a conformally formed insulating layer covering an inner side wall of the gate trench. The gate insulating liner may be made of insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a metal oxide. The metal oxide may include, for example, hafnium oxide, aluminum oxide, or titanium oxide. High-K dielectric materials may be utilized to complement metal based gate electrodes for enhancing the performance of a field effect transistor. In some embodiments, the gate structure 112 may further comprise a barrier liner conformally disposed between the gate insulating liner and the gate electrode. The gate barrier liner may comprise a barrier metal compound, such as, titanium nitride (TiN) or tantalum nitride (TaN).

In the quest to pursuit the ever-shrinking device form factor, the utilization of buried type transistor as selection device may ensure extended channel length (e.g., from a S/D region under a contact plug 114 vertically down to the bottom tip of the gate structure 112, then laterally across the tip of to the buried gate electrode and back up to the opposite S/D region under a neighboring contact plug), thereby achieving higher device density while alleviating the accompanied short channel effect. Nevertheless, selection device of other structural architecture may be utilized. For instance, in some embodiments, planar channel device or raised channel multi-gate devices (e.g., fin-type field effect transistor, FINFET) may also be used as selection device for a memory cell.

In the illustrated embodiment, a shared S/D region is defined between the pair of neighboring gate structures 112 in the active area (between STI structures 111). In some embodiments, bit line 113 is arranged over the shared S/D region formed between the gate structures 112 at a central region of the active area (between STI structures 111). The bit line 113 may be a linear conductive structure that extends in/out of the page as shown in the instant illustration, and electrically connects a plurality of S/D regions (at the respective central regions) of multiple active areas (e.g., the respective S/D region of a plurality of active areas that are arranged in a roll; not shown in the instant regional cross section view).

The contact plug 114 may be formed in and through a dielectric layer (e.g., interlayer dielectric, ILD) above the active area, thereby establishing a vertical conductive path from the surface of the substrate 100 to upper layers of the device stack over the active area. In some embodiments, the contact plug 114 may serve as a storage node via/plug that enables vertical electrical connection with a lower electrode of a storage element (e.g., electrode 116L of the capacitor element 116). The dielectric layer may be made of materials such as oxide or nitride of silicon. In some embodiments, the dielectric layer may include low-K material having dielectric constant lower than, e.g., 3.9. The contact plug 114 may be made of one or more metal or non-metal conductive material, such as poly-silicon, tungsten, aluminum, etc.

Storage element (such as storage capacitor 116) may be formed over the contact plug 114 (e.g., above the corresponding contact pad over the plug) in a dielectric layer 117. The storage capacitor 116 comprises lower electrode 116L, upper electrode 116U, and capacitor dielectric 116D arranged between the upper and the lower electrodes.

A separation layer (e.g., layer 115) may be provided over the contact plug 114, through which the lower electrode of the storage capacitor 116 (e.g., bottom electrode 116L) is formed to establish electrical connection with the contact plug 114. The separation layer may comprise nitride material, e.g., silicon nitride, and serve as etch stop during the fabrication process of the capacitor structure. It is noted that the term “lower” electrode is made with respect to the surface of the substrate for the ease of referral, and shall not be construed as an undue limitation as to device orientation. The contact plug 114 provides a vertical conduction path between the source/drain region of the selection device (e.g., transistor 112) and the lower electrode of the storage element (e.g., electrode 116L).

In some embodiments, the lower electrode 116L may be a cylindrical conductive structure having high aspect ratio (i.e., high depth to width ratio), which corresponds to a tall upward opening U-shaped cross sectional profile (as shown the instant example). In some embodiments, a lateral width of the conductive structure may be few tens of nanometer in scale, e.g., having critical dimension of about 40 nm. In some embodiments, the aspect ratio of the lower electrode 116L may range from about 10 to 40. The lower electrode 116L may be formed from a conformal conductive film made of one or more conductive material(s) such as BSRO ((Ba,Sr)RuO₃), CRO (CaRuO₃), LSCo ((La,Sr)CoO₃), TiN, TiAlN, TaN, TaAlN, W, WN, Ru, RuO₂, SrRuO₃, Ir, IrO₂, Pt, PtO, SRO (SrRuO₃).

The capacitor dielectric 116D may be a conformally formed layer that comprises a nitride, an oxide, a metal oxide, or a combination thereof. For example, the capacitor dielectric 116D may include a single or a multilayered film formed from silicon nitride, silicon oxide, a metal oxide (e.g., HfO₂, ZrO₂, Al₂O₃, La₂O₃, Ta₂O₃, and TiO₂), a perovskite dielectric material (e.g., STO (SrTiO₃), BST ((Ba,Sr)TiO₃), BaTiO₃, PZT, and PLZT, or a combination thereof. In some embodiments, high-K dielectric material may be applied to boost capacitor performance, e.g., enhance capacitance for a given electrode surface area.

The upper electrode 116U may be formed of one or more conductive material such as doped semiconductor, conductive metal nitride, metal, metal silicide, conductive oxide, or a combination thereof. For instance, the upper electrode 116U may be formed of conducive material(s) including BSRO ((Ba,Sr)RuO₃), CRO (CaRuO₃), LSCo ((La,Sr)CoO₃), TiN, TiAlN, TaN, TaAlN, W, WN, Ru, RuO₂, SrRuO₃, Ir, IrO₂, Pt, PtO, SRO (SrRuO₃), though the list of suitable material is merely exemplary and not exhaustive.

Additional conductive features, such as interconnect features 118 and 119 may be formed in additional inter metal dielectric layers over the upper electrode 116U to enable interconnection between circuit elements.

As the level of device integration increases, feature density also increases. By way of example, the feature density among the interconnect features (e.g., lateral interconnect components such as features 118/119/129, or vertical interconnect components such as features 114/124/126/128) is increased considerably in modern semiconductor devices compared to their preceding counterparts. As such, not only the feature dimension thereof shrinks, the inter-feature distance/separation is also reduced. Densely aggregated interconnect patterns in an inter metal dielectric layer may lead to adverse cross talk or parasitic effects. In some embodiments, voids (e.g., air gaps) may be incorporated between interconnect features to alleviate the above-mentioned undesirable effects.

The periphery region 120 may comprise various active device regions laterally separated by isolation features, such as STI 121. The active area may comprise active circuit components (such as transistors) that make up the periphery support circuits, e.g., read-out, decoder, or amplifier circuits. Over the active area there may be upper inter device layers, such as dielectric layer 127, through which contact via/plug 124 may be provided to enable vertical signal conduction from the surface of the substrate 100 to a higher device layer. The contact plug 124 may be connected to a corresponding contact pad (not specifically labeled) there-above in a fashion similar to that in the cell region 110.

Over the contact plug 124 of the presently illustrated embodiment is a dielectric layer 127, through which one or more high aspect ratio interconnect features (e.g., contact via 126) are formed. In some embodiments, the aspect ratio of the contact via 126 may have a range from about 10 to about 40. In some embodiments, the dielectric layer 127 may be (at least partially) a lateral extension of the dielectric layer 117 from the cell region 110. In some embodiments, the design rules for the devices in periphery region 120 may assume a greater feature sizes than that in the cell region 110. In some embodiments, the active circuit components in the periphery region 120 are designed to operate at a higher voltage level than those in the cell region 110.

In some applications, metal materials are employed in the interconnect structure (e.g., lateral components 118/119/129 or vertical interconnect components 114/124/126/128) to provide enhanced electrical characteristics. For one thing, reduced electrical resistance in the interconnect may enable faster device switching speed. However, the incorporation of metal material in the interconnect structure leads to another sets of challenge. By way of example, diffusion or electromigration of metal materials in the interlayer dielectrics may generate contamination and shorting issues. Moreover, in some applications, different conductive materials are employed in different interconnect components. The interface between different interconnect components where different metal materials meet, for example, may encounter intermetallic composites (IMCs) non-uniformity issues that leads to reduced electrical performance.

FIG. 2 illustrates a schematic regional cross-sectional view of an exemplary interconnect structure. The lower most portion of the illustrated interconnect structure includes a lower conductive feature 221. In some embodiments, the lower conductive feature 221 may be a landing pad above the landing plug 124 as shown in FIG. 1. In some embodiments, the lower conductive feature 221 may be a portion of a laterally traversing lower metal line that enables horizontal signal conduction. An inter-metal dielectric layer 227 is disposed over the lower conductive feature 221, and is patterned to form a vertical recess feature (to accommodate the vertical interconnect component 226) and a lateral recess feature (to accommodate the lateral interconnect component 225).

In order to prevent diffusion and increase adhesion at the hetero-material interface (e.g., between the dielectric material 227 and the metal material 225/226) of the interconnect structure, a liner 222 of a barrier material is first disposed on the exposed recess surfaces of the vertical and lateral recess features before conductive material is filled into the recesses to form the vertical component 226 and the lateral component 225, respectively. In some embodiments, the liner formation process comprises disposing a liner material that includes one or more of Titanium (Ti), Tantalum (Ta), or Chromium (Cr). Subsequently, conductive material that includes aluminum (Al) or copper (Cu) is disposed on the liner material to concurrently fill the remaining vertical and lateral portions of the recesses, thereby forming the interconnect structure.

As feature size decreases, it becomes more difficult to fill the vertical and lateral portions of the interconnect recess in a same deposition process (e.g., with a single conductive material). Moreover, in order to reduce electrical resistance and obtain interconnecting metal line of higher conductive quality, a higher deposition (or a subsequent reflow) temperature is applied (e.g., 350° C. to 550° C. range) when depositing the conductive material (e.g., Al) over the liner material (e.g., Ti). However, the high temperature process condition facilitates reactions between the conductive material and the liner material in an unpredictable manner, which leads to the random generation of IMC of different phase compositions. For example, the thermal energy may cause reactions between aluminum (Al) interconnect metal and titanium (Ti) liner material, which results in the random generation among three possible major IMCs of titanium aluminide, namely, gamma TiAl, alpha 2-Ti₃Al and TiAl₃. As the atomic constitution of these IMCs are non-identical, the thickness variation in the resultant liner layer (e.g., layer 222) increases (as illustrated by the wavy curve of the liner 222 in FIG. 2). In some applications, non-uniformity in the liner/interconnect metal layer affects the electrical property of the interconnect structure adversely.

FIGS. 3(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure. For instance, FIG. 3(a) schematically illustrates a conductive feature 321 in a lower device layer over a substrate (e.g., the landing pad under the vertical interconnect component 126 as shown in FIG. 1). In some embodiments, the conductive feature 321 may be a portion of a lateral interconnect component in a lower device layer.

Referring to FIG. 3(b), a dielectric layer 327 is disposed over and covers the conductive feature 321 in a lower device layer. In some embodiments, the dielectric layer 327 may include oxide materials such as silicon oxide, which forms part of an inter-metal dielectric (IMD) layer. In some embodiments, low-K materials may be used in the inter-metal dielectric layer to reduce parasitic coupling between interconnect features, thereby reducing signal delay and enhance device performance. In some embodiments, voids (e.g. air gaps) may be provided in the IMD to further decrease overall dielectric constant of the IMD layer.

Referring to FIG. 3(c), the dielectric layer 327 is patterned and etched to form a recess feature that enables access to a designated portion of the conductive feature 321. In some embodiments, a recess feature with high aspect ratio (i.e., depth/width >1) is formed through suitable etching technique(s). In some embodiments, the aspect ratio of the recess feature may be in a range of about 10 to about 40.

FIGS. 4(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure. Particularly, the instant figures illustrate a formation process for a vertical component of an interconnect structure capable of mitigating metal filling challenges in small form-factor, high aspect ratio recesses in interconnect structures.

Referring to FIG. 4(a), a liner 422 is disposed over exposed surfaces of the vertically extending recess feature (e.g., the recess feature shown in FIG. 3(c)) that provides selective access to an interconnect feature 321 in a lower device layer. The material for the liner 422 may be selected to improve adhesion between the underlying dielectric material (e.g., of the IMD 327) and the subsequently disposed conductive material (e.g., vertical component 425 as shown in FIG. 4(c)). The material for the liner 422 may also be selected to prevent diffusion of the subsequently disposed conductive material in the vertical component of the interconnect structure as set forth in previous embodiments. In some embodiments, the liner 422 may include a titanium containing material. In some embodiments, liner material such as Ti, TiN, W, WN, Ta, TaN may be formed by thin film deposition techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). As illustrated in FIG. 4(a), the liner 422 is formed with a substantially uniform thickness over exposes surfaces (e.g., top horizontal portion, vertical portion, and the bottom horizontal portion) of the recess feature without filling the via hole.

Referring to FIG. 4(b), conductive material 425′ is disposed over the liner 422 to fill the remaining portion of the via hole. Suitable deposition processes such as PVD, CVD, ALD, or plating may be employed. In some embodiments, the conducive material 425′ for forming the vertical interconnect component may include W, Al, or Cu. As shown in the instant figure, excessive conductive material 425′ is also formed over the horizontal portions of the liner 422. The deposition process substantially fills the via hole (between the vertical/bottom portion of the liner 422) with conductive material.

Referring to FIG. 4(c), a planarization process (e.g., chemical mechanical polishing, CMP) is performed to remove the excessive lateral coverage of the conductive material, thereby forming a vertical conductive feature (which includes the vertical conductive filling 425) in the IMD 327. In some embodiment (such as that shown in the instant illustration), the CMP process leaves a horizontal liner portion 422h over the IMD layer 327. Meanwhile, a vertical liner portion 422v extends downwardly from the horizontal liner portion 422h and situates between the vertical conductive filling 425 and the IMD layer 327. In some embodiments, the horizontal liner portion 422h is substantially removed during the planarization process. The conductive filling 425 and the barrier liner 422 cooperatively form a cross-layer via plug that penetrates across the IMD layer 327.

FIGS. 5(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure. Particularly, the instant figures illustrate a formation process for a lateral conductive component of an interconnect structure.

Referring to FIG. 5(a), an interposing layer 523 having substantially uniform thickness is disposed over the planar surface resulted from a planarization process (e.g., as illustrated by FIG. 4(c)). The interposing layer 523 extends laterally over a planar projection of the vertical interconnect component (e.g., conductor 425) and establishes electrical connection there-with. In the illustrated embodiment, the interposing layer 523 comprises a metal material such as titanium (Ti). In some embodiments, the interposing layer 523 is formed by PVD process with a thickness of less than 100 nm.

Referring to FIG. 5(b), an interconnect metal layer 525 is disposed over the interposing layer 523. The interconnect metal 525 may include one or more materials such as W, Al, or Cu. In some embodiments, aluminum (Al) film is disposed by PVD process at a relatively high temperature range of about 350 to 450° C. to a thickness of over 100 nm. In some embodiments, metal layer deposition may be followed by a reflow process at temperature range of about 500 to 550° C. to improve grain quality. In some embodiments, the high temperature condition during the metal layer formation process causes reaction between materials from the metal layer 525 (e.g., Al) and the interposing layer 523 (e.g., Ti). The self-terminating reaction between the two different metal materials leads to random generation of IMC layer 523′ of different phases (e.g., Ti₃Al—TiAl₃). The difference in crystal structure among the various intermetallic phases translates to thickness variation in the lateral interconnect components, as illustrated in the instant figure. In some embodiments, the thickness variation in the IMC layer 523′ may be greater than about 30%. In some embodiments, a lower temperature condition may be applied during metal layer formation to reduce the level of interaction between the metal layer 525 and the interposing layer 523, at the cost of lower grain quality.

Referring to FIG. 5(c), an anti-reflective layer (ARL) 528 is disposed over the lateral component (e.g., the conductive line 525) of the interconnect structure. In some embodiments, the ARL may comprise titanium (Ti). In some embodiments, the ARL 528 is made of titanium nitride material with varying gradient content composition. For instance, a lower portion of the ARL 528 (e.g., near the metal layer 525) may comprise higher titanium content with respect to nitride. On the other hand, an upper portion (e.g., further away from the metal layer 525) of the ARL 528 may be provided with higher nitride content. The ARL 528 is provided in preparation for subsequent interconnect patterning process that forms the lateral conductive features (e.g., horizontal metal routings) of the interconnect structure, where the reduction of surface reflection over the metal layer 525 helps to maintain photolithography resolution/accuracy. Upon the completion of photolithography process, the interposing layer 523′ and the metal layer 525 cooperatively form an intra-layer component that that traverses laterally within a dielectric layer over the IMD layer 327.

FIGS. 6(a)-(c) are schematic illustrations that show intermediate structures during various stages of fabrication processes in accordance with some embodiments of the instant disclosure. Particularly, the instant figures illustrate a fabrication process for forming a lateral conductive interconnect structure capable of further mitigating the IMC uniformity issue.

Referring to FIG. 6(a), an interposing layer 623 having substantially uniform thickness is disposed over the planar surface resulted from a planarization process (e.g., as illustrated by FIG. 4(c)). The interposing layer 623 extends laterally over a planar projection of the vertical interconnect component (e.g., via plug metal 425) and establishes electrical connection there-with. The forming of the interposing layer 623 includes disposing an intermetallic material of substantially unitary composition, where the intermetallic material includes a metal component identical to that in a subsequently disposed horizontal interconnect conductor (e.g., metal layer 626 as shown in FIG. 6(b)). In some embodiments, the interposing layer 623 comprises a metal material such as titanium (Ti). In the instant embodiment, the interposing layer 623 intermetallic material of substantially unitary composition consists essentially of TiAl. In some embodiments, the interposing layer 623 is formed by PVD process with a thickness of less than 100 nm. In some embodiments, the deposition process for the interposing layer 623 is performed under a relatively low temperature condition (e.g., lower than about 350° C.). In some embodiments, the interposing layer 623 is formed by PVD process with a thickness of less than 100 nm. In some embodiments (e.g., memory applications such as dynamic random access memory (DRAM)), the interposing layer 623 may be provided with a thickness in a range of about 50-500 Å. In some embodiments, an overall thickness variation in the interposing layer 623 is no more than about 5%.

Referring to FIG. 6(b), an interconnect metal layer 626 is disposed over the interposing layer 623 at a relatively high temperature condition (e.g., higher than about 350° C.). The interconnect metal 626 may include one or more materials such as W, Al, or Cu. In the illustrated embodiment, aluminum (Al) film is disposed by PVD process at temperature range of about 350 to 450° C. to a thickness of over 100 nm. In some applications (e.g., DRAM), the interconnect metal layer 626 may be provided with a thickness in a range of about 1000 Å-1 um. In some embodiments, metal layer deposition may be followed by a reflow process at temperature range of about 500 to 550° C. In some embodiments, the thickness variation in the interposing layer 623 is no more than about 5% with respect to a regional thickness of the interposing layer 623 in the planar projection region over the vertical interconnect component (e.g., the via plug 425/422 as shown in FIG. 4(c)). In some embodiments, a thickness ratio between the interposing layer 623 and the lateral conductive feature (e.g., metal layer 626) has a value in a range from about 0.005 to 0.5. In some embodiments, the thickness ratio of interposing layer to the metal layer ranges from about 0.01 to about 0.1. In some embodiments, the thickness ratio between interposing layer to metal layer ranges from about 0.1 to about 0.4.

The presence of the IMC interposing layer 623 of unitary composition under the conductive line (e.g., interconnect metal layer) 626 prohibits the spontaneous reaction as mentioned previously, even under higher deposition temperature conditions. Meanwhile, because of the substantially unitary molecular constitution in the interposing layer 623 (e.g. gamma TiAl), the thickness uniformity of the interposing layer 623 may be maintained. Accordingly, relatively higher deposition temperature may be applied without undue worries during the metal layer formation process to improve grain quality of the interconnect metal layer 626.

Referring to FIG. 6(c), an anti-reflective layer (ARL) 628 is disposed over the lateral component (e.g., the conductive line 626) of the interconnect structure. In some embodiments, the ARL may comprise titanium (Ti). In some embodiments, the ARL 628 is made of titanium nitride material with varying gradient content composition. For instance, a lower portion of the ARL 628 (e.g., near the metal layer 626) may comprise higher titanium content with respect to nitride. On the other hand, an upper portion (e.g., further away from the metal layer 626) of the ARL 628 may be provided with higher nitride content. The ARL 628 is provided in preparation for subsequent interconnect patterning process that forms the lateral conductive features (e.g., horizontal metal routings) of the interconnect structure, where the reduction of surface reflection over the metal layer 626 helps to maintain photolithography resolution/accuracy. In addition, the ARL 628 over the metal layer 626 may increase adhesion between the lateral interconnect component with subsequently formed dielectric layer, thereby improving structural integrity and thus reliability of the electrical device.

FIG. 7 illustrates a schematic regional cross-sectional view of an exemplary interconnect structure in accordance with some embodiments of the present disclosure. The lower most portion of the illustrated interconnect structure includes a lower conductive feature 721 formed in a lower device layer (e.g., lower inter-metal dielectric layer, IMD). In some embodiments, the lower conductive feature 721 may be a landing pad above a landing plug (e.g., plug 124 as shown in FIG. 1). In some embodiments, the lower conductive feature 721 may be a portion of a laterally traversing lower metal line that enables horizontal signal conduction. An inter-metal dielectric layer 727 is disposed over the lower conductive feature 721, and is patterned to form a vertical recess feature (to accommodate the vertical interconnect component 72L). In some embodiments, a lateral recess feature is further formed over the vertical recess feature (to accommodate the lateral interconnect component 72U).

In order to prevent diffusion and increase adhesion at the hetero-material interface (e.g., between the dielectric material 727 and the metal material 725/726) of the interconnect structure, a liner 722 of a barrier material is first disposed on the exposed recess surfaces of the vertical and lateral recess features before conductive material is filled into the recesses to form the vertical component 72L and the lateral component 72U, respectively. In some embodiments, the liner formation process comprises disposing a liner material that includes one or more of Titanium (Ti), Tantalum (Ta), or Chromium (Cr). Subsequently, conductive material that includes aluminum (Al) or copper (Cu) may be disposed on the liner material to concurrently fill the remaining vertical and lateral portions of the recesses, thereby forming the interconnect structure.

In some embodiments, a horizontal liner portion 722h is formed over the IMD layer 727. In some embodiments, the horizontal liner portion 722h shares a substantially coplanar top boundary with the vertical conductive filling (e.g., plug conductor) 725 in which it laterally surrounds. Meanwhile, a vertical liner portion 722v arranged between the vertical conductive filling 725 and the IMD layer 727 extends downwardly from the horizontal liner portion 722h. In some embodiments, the horizontal liner portion 722h is substantially removed during a planarization process. The conductive filling 725 and the barrier liner (e.g., 722v) cooperatively form a cross-layer via plug that penetrates across the IMD layer 727.

An interposing layer 723 having substantially uniform thickness is disposed over the plug conductor 725 and the liner 722. The interposing layer 723 extends laterally over a planar projection of the vertical interconnect component (e.g., plug conductor 725) and establishes electrical connection there-with. In the illustrated embodiment, the interposing layer 723 comprises a metal material such as titanium (Ti). In some embodiments, the interposing layer 723 is formed by PVD process to a thickness of less than about 100 nm.

An interconnect metal layer 726 is disposed over the interposing layer 723. The interconnect metal 726 may include one or more conductive materials such as W, Al, or Cu. In some embodiments, aluminum (Al) film is disposed by PVD process at a relatively high temperature range of about 350 to 450° C. to a thickness of over 100 nm. In some embodiments, metal layer deposition may be followed by a reflow process at temperature range of about 500 to 550° C. to improve grain quality. In some embodiments, the thickness variation in the IMC layer 723 may be maintained sufficiently small (e.g., less than about 5%) to ensure predictable electrical characteristics through layer uniformity.

An overlay (e.g., etch-resisting/anti-reflective layer (ARL)) 728 is disposed over the lateral component (e.g., the conductive line 726) of the interconnect structure. In some embodiments, the overlayer 728 may comprise titanium (Ti). In some embodiments, the overlayer 728 is made of titanium nitride material with varying gradient content composition. For instance, a lower portion of the overlayer 728 (e.g., near the metal line 726) may comprise higher titanium content with respect to nitride. On the other hand, an upper portion (e.g., further away from the metal layer 726) of the overlayer 728 may be provided with higher nitride content. The overlayer 728 is provided in preparation for subsequent interconnect patterning process that forms the lateral conductive features (e.g., horizontal metal routings) of the interconnect structure, where the reduction of surface reflection over the metal layer 726 helps to maintain photolithography resolution/accuracy.

Upon completion of photolithography process, the interposing layer 723 and the metal layer 726 (as well as the remnant ARL 728) cooperatively form an intra-layer component (e.g., upper portion 72U) that that traverses laterally in a dielectric layer over the IMD layer (e.g., layer 727).

Accordingly, one aspect of the instant disclosure provides a conductive structure that comprises: a vertical component extending through a dielectric layer, including an inner conductor having an aspect ratio exceeding 1; and a lateral component arranged above the vertical component, including: an upper conductive line extending laterally over the inner conductor of the vertical component; and an interposing layer having a substantially uniform thickness arranged between the inner conductor and the upper conductive line, and extending laterally beyond a planar projection of the vertical component, wherein the upper conductive line of the lateral component is in electrical connection with the inner conductor of the vertical component through the interposing layer.

In some embodiments, a thickness variation in the interposing layer is no more than about 5%.

In some embodiments, a thickness variation in the interposing layer is no more than about 5% with respect to a regional thickness of the interposing layer in the planar projection region of the vertical component.

In some embodiments, the vertical component further includes a vertical liner that encloses a lateral boundary and a bottom boundary of the inner conductor of the vertical component.

In some embodiments, the lateral component further includes a lateral liner disposed between the interposing layer and the dielectric layer, wherein the vertical liner connects the lateral liner around a contact interface between the inner conductor and the interposing layer; and the lateral liner and the vertical liner are formed with identical material.

In some embodiments, the identical material includes a Ti containing material.

In some embodiments, the lateral component further comprises an anti-reflective layer (ARL) above the upper conductive line.

Accordingly, another aspect of the instant disclosure provides a semiconductor device that comprises: an electrical device disposed in a device layer over a substrate; a cross-layer component that forms at least part of a vertical signal path to the electrical device, the cross-layer component including an inner conductor including an upper, a lateral, and a bottom boundary, having an aspect ratio exceeding 1; and an intra-layer component arranged in a layer over the device layer and above the cross-layer component, the intra-layer component including: a conductive line extending laterally over the inner conductor of the cross-layer component; and an intermetallic layer that includes an intermetallic material with substantially unitary molecular constitution, arranged under the conductive line and extending laterally beyond a planar projection of the cross-layer component, wherein the upper boundary of the inner conductor is in contact with the intermetallic layer.

In some embodiments, the substantially unitary intermetallic material includes a metal species identical to that in the conductive line.

In some embodiments, the substantially unitary intermetallic material consists essentially of TiAl.

In some embodiments, the cross-layer component further includes a lower liner that encloses the lateral boundary and the bottom boundary of the inner conductor of the cross-layer component.

In some embodiments, the intra-layer component further includes an upper liner disposed between the intermetallic layer and the dielectric layer, wherein the upper liner connects the lower liner around the upper boundary of the inner conductor; and the lower liner and the upper liner are formed with the same material.

In some embodiments, the lateral component further comprises an anti-reflective layer (ARL) above the conductive line.

Accordingly, yet another aspect of the instant disclosure provides a method of forming a conducting structure in a semiconductor device, comprising: patterning a first recess feature having aspect ratio greater than 1 through a dielectric layer to enable access to a conductive feature in a layer under the dielectric layer; forming a vertical conductive feature in the first recess feature; forming, under a first process temperature, an interposing layer with substantially uniform thickness extending laterally over a planar projection of the vertical conductive feature and in contact with the vertical conductive feature; and forming, under a second process temperature, a metal layer over the interposing layer, wherein the second process temperature is higher than the first process temperature, patterning the interposing layer and the metal layer to form a lateral conductive feature over and in contact with the vertical conductive feature.

In some embodiments, the forming of the interposing layer includes disposing an intermetallic material of substantially unitary composition, wherein the intermetallic material includes a metal component identical to that in the lateral conductive feature.

In some embodiments, the intermetallic material consists essentially of TiAl.

In some embodiments, a thickness ratio between the interposing layer and the lateral conductive feature ranges from about 0.01 to 0.1.

In some embodiments, the method further comprises disposing a liner layer around an outer periphery of the vertical conductive feature before the forming of an interposing layer.

In some embodiments, the forming of a metal layer over the interposing layer comprises performing a physical vapor deposition process at about 350 to 450° C. to a thickness of over 100 nm.

In some embodiments, the forming of a metal layer over the interposing layer comprising performing a thermal treatment process at about 500 to 550° C.

The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a logistics data management method.

Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size, and arrangement of the parts within the principles, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.

	Number	Date	Country
	62778908	Dec 2018	US
	62778922	Dec 2018	US

SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME

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