Patent Application
20230116155
The disclosure relates to the technical field of semiconductors, and relates to but is not limited to a semiconductor structure and a method for forming the same.
The development of dynamic memory pursues the requirements of high speed, high integration density, and low power consumption. With the miniaturization of semiconductor devices, especially in the manufacturing process of Dynamic Random Access Memory (DRAM) with critical size less than 20 nanometer (nm), the structural stability of bit lines directly determines the electrical performance of DRAM.
In related art, the bit lines of dynamic random access memory are located on the surface of active areas, and are prepared separately from peripheral gates (PG) in peripheral areas. Therefore, the preparation process thereof is complex and has a high cost. In addition, the structure of the bit lines formed in the related art is unstable, resulting in poor electrical performance of the dynamic random access memory.
In view of the above, embodiments of the disclosure provide a semiconductor structure and a method for forming the same.
In a first aspect, the embodiments of the disclosure provide a method for forming a semiconductor structure. The method includes the following operations.
A semiconductor substrate including a memory area and a peripheral area is provided. An insulating layer is formed on a surface of the memory area, and a first metal layer is formed on a surface of the peripheral area.
The insulating layer and the memory area of the semiconductor substrate are etched to form a plurality of bit line trenches arranged at intervals along a first direction and etched insulating layer. Part of the bit line trench is located in the memory area of the semiconductor substrate, and the other part of the bit line trench is located in the etched insulating layer.
A second metal layer is formed on a surface of the bit line trench, the surface of the memory area and a surface of the first metal layer.
The first metal layer and the second metal layer are etched to form a semi-buried bit line structure and a peripheral gate.
In a second aspect, the embodiments of the disclosure provide a semiconductor structure formed by the method for forming the semiconductor structure as mentioned above.
The semiconductor structure at least includes a semiconductor substrate including a memory area and a peripheral area; a etched insulating layer located on a surface of the memory area; a semi-buried bit line structure, in which a part of each semi-buried bit line structure is located in the memory area, and the other part of the semi-buried bit line structure is located in the etched insulating layer; and a peripheral gate located on the surface of the peripheral area.
In the drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference symbols with different letter suffixes may denote different examples of similar components. The accompanying drawings generally illustrate the various embodiments discussed herein by way of examples but not limitation.
Exemplary embodiments of the disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the disclosure are shown in the accompanying drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are given to provide a more thorough understanding of the disclosure. However, it will be apparent to those skilled in the art that the disclosure may be practiced without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the disclosure. That is, not all features of the actual embodiments are described herein with not descripting well-known functions and structures in detail.
In the drawings, the dimension and relative dimension of a layer, an area, or an element may be exaggerated for clarity. Throughout, the same reference numerals denote the same elements.
It should be understood that when an element or layer is described as “on”, “adjacent to”, “connected to” or “coupled to” another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or may exist intervening elements or layers. On the contrary, when an element is described as “directly on”, “directly adjacent to”, “directly connected to” or “directly coupled to” another element or layer, there is no intervening element or layer. It should be understood that when the terms “first”, “second”, “third” and so on are used to describe various elements, components, areas, layers, and/or portions, such elements, components, areas, layers, and/or portions should not be limited by such terms. These terms are used only to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Thus, the first element, component, area, layer, or portion discussed below may be represented as the second element, component, area, layer, or portion without departing from the teachings of the disclosure. The discussion on the second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in the disclosure.
The terms used herein are intended to describe specific embodiments only and are not to be limitations of the disclosure. As used herein, singular forms of “a”, “an” and “said/the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “composing” and/or “including”, when used in this specification, determine the presence of said features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups. As used herein, the term “and/or” includes any and all combinations of related listed items.
Based on the problems existing in the related art, the embodiments of the disclosure provide a semiconductor structure and a method for forming the same. In this disclosure, the method for forming the semiconductor structure includes: providing a semiconductor substrate including a memory area and a peripheral area; forming an insulating layer on a surface of the memory area and forming a first metal layer on a surface of the peripheral area; etching the insulating layer and the memory area of the semiconductor substrate to form a plurality of bit line trenches arranged at intervals along a first direction and the etched insulating layer, and forming a second metal layer on surfaces of the bit line trench, the memory area and the first metal layer; and etching the first metal layer and the second metal layer, to form a semi-buried bit line structure and peripheral gate. Regarding the semiconductor structure formed by the method for forming the semiconductor structure provided by the embodiments of the disclosure, the semi-buried bit line and the peripheral gate can be formed simultaneously, and the structure of the semi-buried bit line is stable, thereby greatly simplifying the preparation process of the semiconductor structure, reducing the preparation cost of the semiconductor structure, and improving the electrical performance of the semiconductor structure.
The embodiments of the disclosure provide a method for forming a semiconductor structure.
At S101, a semiconductor substrate including a memory area and a peripheral area is provided. An insulating layer is formed on a surface of the memory area, and a first metal layer is formed on a surface of the peripheral area.
The semiconductor substrate may be a silicon substrate. The semiconductor substrate may further include other semiconductor elements such as germanium (Ge), or semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys such as silicon germanium (SiGe), arsenic gallium phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP) and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.
In the embodiments of the disclosure, the memory area of the semiconductor substrate is used to form memory devices of the semiconductor device, such as storage capacitors. The peripheral area of the semiconductor substrate is used to form a peripheral control circuit of the semiconductor device. The insulating layer may be a material layer composed of any insulating material, such as a silicon nitride layer or a silicon oxynitride layer. The first metal layer may be a polysilicon layer, a doped silicon layer, or a silicide layer.
At S102, the insulating layer and the memory area of the semiconductor substrate are etched to form a plurality of bit line trenches arranged at intervals along a first direction and the etched insulating layer. Part of the bit line trench is located in the memory area of the semiconductor substrate, and the other part of the bit line trench is located in the etched insulating layer.
In the embodiments of the disclosure, the semiconductor substrate may include a top surface at a front face and a bottom surface at a back face opposite to the front face. A direction perpendicular to the top surface and the bottom surface of the semiconductor substrate is defined as a third direction, in the case of ignoring the flatness of the top surface and the bottom surface. A first direction and a second direction, which are intersecting each other (e.g. perpendicular to each other), are defined in the directions of the top surface and the bottom surface of the semiconductor substrate (that is, the plane where the semiconductor substrate is located). For example, an arrangement direction of the plurality of bit line trenches may be defined as the first direction, and a plane direction of the semiconductor substrate may be determined based on the first direction and second direction. Herein, the first direction, the second direction, and the third direction are pairwise perpendicular. In the embodiments of the disclosure, the first direction is defined as X-axis direction, the second direction is defined as Y-axis direction, and the third direction is defined as Z-axis direction.
In the embodiments of the disclosure, a part of the bit line trench is located in the memory area of the semiconductor substrate, and the other part of the bit line trench is located in the etched insulating layer. That is, the bit line trench in the embodiments of the disclosure is semi-buried in the semiconductor substrate.
At S103, a second metal layer is formed on a surface of the bit line trench, a surface of the memory area and a surface of the first metal layer.
The second metal layer may be composed of any conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
At S104, the first metal layer and the second metal layer are etched to form a semi-buried bit line structure and a peripheral gate.
In the embodiments of the disclosure, part of the semi-buried bit line structure is located in the memory area of the semiconductor substrate, and the other part of the semi-buried bit line structure is located in the etched insulating layer. The peripheral gate is a structural device located in the peripheral area.
First, referring to
In some embodiments, the insulating layer located on the surface of the memory area includes first word line insulating layers, and a bit line insulating layer located between adjacent first word line insulating layers and covering the first word line insulating layers. The method for forming the semiconductor structure further includes an operation that a buried word line structure is formed in the memory area. Herein, the buried word line structure includes at least a first word line insulating layer, and the first word line insulating layer extends beyond a top surface of the peripheral area.
In some embodiments, the formation of the buried word line structure in a memory area includes the following operations.
At S11, a first isolation layer is formed on the surfaces of the memory area and the peripheral area.
The first isolation layer is a material layer formed of any insulating material. For example, the first isolation layer may be a silicon oxide layer or a silicon oxynitride layer. In the embodiments of the disclosure, the first isolation layer may be formed by any suitable deposition process, for example, a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a spin-coating process, or a coating process.
At S12, the first isolation layer on the surface of the memory area and the memory area are etched to form a plurality of word line trenches arranged at intervals along the second direction.
In the embodiments of the disclosure, a dry etching process, such as a plasma etching process, reactive ion etching process or ion milling process may be used to etch the first isolation layer on the surface of the memory area and the memory area, to form the word line trenches.
At S13, a buried word line structure is formed in the word line trench.
In some embodiments, S13 may include the following operations:
At S131, a gate oxide layer is formed on an inner wall of the word line trench.
At S132, a word line metal layer is formed in the word line trench where the gate oxide layer is formed.
At S133, a word line insulating layer is formed on a surface of the word line metal layer. The word line insulating layer includes a second word line insulating layer and a first word line insulating layer located on a surface of the second word line insulating layer.
In the embodiments of the disclosure, the gate oxide layer may be a silicon oxide layer. The metal material constituting the word line metal layer may be metal tungsten, titanium nitride or a combination thereof. The word line insulating layer may be a silicon nitride layer or a silicon oxynitride layer.
In some embodiments, the top surface of the first word line insulating layer 103d extends the top surface of the peripheral area by 70 to 90 nanometers (nm). In the embodiments of the disclosure, the top surface of the first word line insulating layer is arranged beyond the top surface of the peripheral area, so that sufficient space can be provided for subsequent buried bit line.
In some embodiments, after forming the buried word line, the method for forming the semiconductor structure further includes the following operations.
At S14, part of the first isolation layer is removed from the peripheral area and the memory area to expose the first word line insulation layer.
At S15, after exposing the first word line insulating layer, the first isolation layer is removed from the remaining surface of the peripheral area to expose the surface of the peripheral area.
In some embodiments, the first metal layer on the surface of the peripheral region may be formed by the following operations.
At S16, a first initial metal layer, a first mask layer and a first photoresist layer are sequentially formed on surfaces of the peripheral area, the memory area, and the first word line insulating layer.
At S17, the first mask layer is etched through the first photoresist layer to transfer the first preset pattern to the first mask layer, obtaining a patterned first mask layer.
At S18, the first initial metal layer is etched through the patterned first mask layer to form the first metal layer.
Continuing to refer to
In the embodiments of the disclosure, the first photoresist layer and the patterned first mask layer may be removed by using a wet or dry etching technique.
In some embodiments, the formation of the bit line insulating layer located between the adjacent first word line insulating layers and covering the first word line insulating layers is illustrated with reference to S102.
Next, referring to
Part of the bit line trench is located in the memory area of the semiconductor substrate, and the other part of the bit line trench is located in the etched insulating layer.
In some embodiments, S102 may be performed by the following operations.
At S1021, a bit line insulating layer, a bit line mask layer and a second photoresist layer are sequentially formed on the surfaces of the first metal layer, the memory area, and the first word line insulating layer. The second photoresist layer has a second preset pattern including a plurality of sub-patterns arranged in parallel along the first direction. Each sub-pattern is used to form one bit line trench.
In the embodiments of the disclosure, the bit line insulating layer may be a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer. The bit line mask layer may be composed of one hard mask layer or multiple hard mask layers.
In the embodiments of the disclosure, the second photoresist layer 109 has the second preset pattern including a plurality of sub-patterns B arranged in parallel along the X-axis direction. Each sub-pattern B is used for forming one bit line trench.
It should be noted that, in the embodiments of the disclosure, the window for forming the bit line trench is large and extends to the peripheral area, because it is necessary to lead the bit line from the memory area to the peripheral area, so as to facilitate the access and lead-out of the bit line electrical signal.
At S1022, the bit line mask layer is etched through the second photoresist layer to transfer the sub-pattern to the bit line mask layer, obtaining a patterned bit line mask layer.
At S1023, the bit line insulating layer, the first word line insulating layer and the memory area are etched through the patterned bit line mask layer to form a bit line trench.
It should be noted that in the embodiments of the disclosure, the first word line insulating layer is partially etched along the height direction during the formation of the bit line trench.
Referring to
Next, referring to
The second metal layer may also be composed of any conductive material, such as tungsten, cobalt, copper, aluminum, titanium nitride, polysilicon, doped silicon, silicide, or any combination thereof.
In some embodiments, the first metal layer and the second metal layer may be the same or different. In the embodiments of the disclosure, the first metal layer is different from the second metal layer. For example, the first metal layer may be a polysilicon layer, while the second metal layer may be a metallic tungsten layer.
Next, referring to
In some embodiments, S104 may include the following operations.
At S1041, a second mask layer is formed on the surface of the second metal layer in the peripheral area.
In the embodiments of the disclosure, the second mask layer is used for forming the peripheral gate, and the second mask layer may be a silicon nitride layer.
At S1042, the second metal layer is etched through the second mask layer to form etched second metal layers. The etched second metal layer located in the bit line trench constitutes a semi-buried bit line structure.
In the embodiments of the disclosure, part of the formed buried bit line structure is located in the memory area A of the semiconductor substrate, and the other part is located in the insulating layer on the surface of the semiconductor substrate in the memory area, so that the semi-buried bit line structure can be formed.
At S1043, the first metal layer is etched through the etched second metal layer to form etched first metal layer. The etched first metal layer and the etched second metal layer located in the peripheral area together constitute a peripheral gate.
It should be noted that, in the embodiments of the disclosure, the etched second metal layer 112a located in the bit line trench would not be etched when the first metal layer is etched through the etched second metal layers to form the etched first metal layer, due to the etching load effect caused by the different pattern densities of the array area A and the peripheral area C.
In some embodiments, the method for forming the semiconductor structure further includes an operation that a second isolation layer is formed on surfaces of the peripheral area, the memory area, and the peripheral gate, after forming the semi-buried bit line structure and the peripheral gate.
When forming a semiconductor structure by the method for forming a semiconductor structure provided by the embodiments of the disclosure, the semi-buried bit line and the peripheral gate can be formed simultaneously, and the structure of the semi-buried bit line is stable, thereby greatly simplifying the preparation process of the semiconductor structure, reducing the preparation cost of the semiconductor structure, and improving the electrical performance of the semiconductor structure.
In addition, the embodiments of the disclosure also provide a semiconductor structure formed by the method for forming the semiconductor structure provided by the above embodiments.
In the semiconductor structure, the semiconductor substrate 100 includes the memory area A and the peripheral area C. The memory area A is used for forming a memory device of the semiconductor device, such as storage capacitors. The peripheral area is used for forming a peripheral control circuit of the semiconductor device.
The etched insulating layer 111 is located on the surface of the memory area A. Part of the semi-buried bit line structure 114 is located in the memory area n A of the semiconductor substrate, and the other part of the semi-buried bit line structure 114 is located in the etched insulating layer 111.
The peripheral gate 115 is located on the surface of the peripheral area C, and is a functional device in the peripheral circuit.
In the embodiments of the disclosure, the etched insulating layer 111 includes at least etched first word line insulating layer. The semiconductor structure 30 also includes buried word line structure (not shown in the figure). The buried word line structure is located in the memory area A, and includes at least the etched first word line insulating layer. The etched first word line insulating layer exceeds the top surface of the peripheral area C by 70 to 90 nm.
In some embodiments, the semiconductor structure further includes a second isolation layer (not shown in the figure) on surfaces of the peripheral area C, the memory area A, the semi-buried bit line structure 114 and the peripheral gate 115. The second isolation layer is used to isolate the peripheral gates from other devices of the semiconductor structure, and also used to isolate the semi-buried bit line structure from other devices of the semiconductor structure.
It should be noted that, in the embodiments of the disclosure, through the method for forming the semiconductor structure provided by embodiments, the buried bit line structure and the peripheral gate can be prepared and formed simultaneously, thereby greatly simplifying the preparation process of the semiconductor structure.
Similar to the method for forming the semiconductor structure in the embodiments described above, regarding the semiconductor structure in the embodiments of the disclosure, technical features not disclosed in detail can be understood with reference to the above-mentioned embodiments, and the details will not be repeated here.
In the semiconductor structure provided by the embodiments of the disclosure, a part of the bit line is buried in the semiconductor substrate and the other part is buried in the insulating layer on the surface of the semiconductor substrate, so that the bit line structure can have a larger area, and thus the bit line has a stronger control ability.
In the several embodiments provided by the disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-target manner The device embodiments described above is only schematic. For example, the division of the unit is only a logical function division, and there may be another division mode in actual implementation. For example, a plurality of units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the components shown or discussed are coupled with each other, or directly coupled.
The units described as the above-mentioned separated components may or may not be physically separated. The components displayed as units may or may not be physical units. That is, they may be located in one place or distributed over multiple network units. Some or all of the units can be selected according to the actual needs to achieve the purpose of the embodiments.
The features in several methods or devices embodiments provided by the disclosure can be arbitrarily combined without conflict to obtain a new method embodiment or device embodiment.
The above descriptions are only some implementation modes of the embodiments of the disclosure, but the scope of protection of the embodiments of the disclosure is not limited thereto. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the disclosure shall fall within the scope of protection of the disclosure. Therefore, the scope of protection of the embodiments in the disclosure shall be subject to the scope of protection of the claims.
A semiconductor structure and a method for forming a semiconductor structure are provided by the embodiments of the disclosure. The method for forming the semiconductor structure of the disclosure includes: providing a semiconductor substrate including a memory area and a peripheral area; forming an insulating layer on a surface of the memory area and forming a first metal layer on a surface of the peripheral area; etching the insulating layer and the memory area of the semiconductor substrate to form a plurality of bit line trenches arranged at intervals along a first direction and the etched insulating layer, and forming a second metal layer on surfaces of the bit line trench, the memory area and the first metal layer; and etching the first metal layer and the second metal layer, to form a semi-buried bit line structure and peripheral gate. Regarding the semiconductor structure formed by the method for forming the semiconductor structure provided by the embodiments of the disclosure, the semi-buried bit line and the peripheral gate can be formed simultaneously, and the structure of the semi-buried bit line is stable, thereby greatly simplifying the preparation process of the semiconductor structure, reducing the preparation cost of the semiconductor structure, and improving the electrical performance of the semiconductor structure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111181092.4 | Oct 2021 | CN | national |
This application is a U.S. continuation application of International Application No. PCT/CN2022/070599, filed on Jan. 6, 2022, which claims priority to Chinese Patent Application No. 202111181092.4, filed on Oct. 11, 2021. The disclosures of International Application No. PCT/CN2022/070599 and Chinese Patent Application No. 202111181092.4 are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2022/070599 | Jan 2022 | US |
| Child | 17849987 | US |
