Patent Application
20120003815
This patent application claims priority to Korean Patent Application No. 10-2009-63943, which was filed on Jul. 2, 2010, by the same inventor, the contents of which are incorporated by reference as though fully set forth herein.
1. Field of the Invention
This invention relates to semiconductor circuitry formed using bonding.
2. Description of the Related Art
Advances in semiconductor manufacturing technology have provided computer systems with integrated circuits that include many millions of active and passive electronic devices, along with the interconnects to provide the desired circuit connections. A typical computer system includes a computer chip, with processor and control circuits, and an external memory chip. As is well-known, most integrated circuits include laterally oriented active and passive electronic devices that are carried on a single major surface of a substrate. The current flow through laterally oriented devices is generally parallel to the single major surface of the substrate. Active devices typically include transistors and passive devices typically include resistors, capacitors, and inductors. However, these laterally oriented devices consume significant amounts of chip area. Sometimes laterally oriented devices are referred to as planar or horizontal devices. Examples of laterally oriented devices can be found in U.S. Pat. No. 6,600,173 to Tiwari, U.S. Pat. No. 6,222,251 to Holloway and U.S. Pat. No. 6,331,468 to Aronowitz.
Vertically oriented devices extend in a direction that is generally perpendicular to the single major surface of the substrate. The current flow through vertically oriented devices is generally perpendicular to the single major surface of the substrate. Hence, the current flow through a vertically oriented semiconductor device is generally perpendicular to the current flow through a horizontally oriented semiconductor device. Examples of vertically oriented semiconductor device can be found in U.S. Pat. No. 5,106,775 to Kaga, U.S. Pat. No. 6,229,161 to Nemati, U.S. Pat. No. 7,078,739 to Nemati. It should be noted that U.S. Pat. No. 5,554,870 to Fitch, U.S. Pat. No. 6,229,161 to Nemati and U.S. Pat. No. 7,078,739 to Nemati disclose the formation of both horizontal and vertical semiconductor devices on a single major surface of a substrate.
It is desirable to provide computer chips that can operate faster so that they can process more data in a given amount of time. The speed of operation of a computer chip is typically measured in the number of instructions in a given amount of time it can perform. Computer chips can be made to process more data in a given amount of time in several ways. For example, they can be made faster by decreasing the time it takes to perform certain tasks, such as storing and retrieving information to and from the memory chip. The time needed to store and retrieve information to and from the memory chip can be decreased by embedding the memory devices included therein with the computer chip. This can be done by positioning the memory devices on the same surface as the other devices carried by the substrate.
However, there are several problems with doing this. One problem is that the masks used to fabricate the memory devices are generally not compatible with the masks used to fabricate the other devices on the computer chip. Hence, it is more complex and expensive to fabricate a computer chip with memory embedded in this way. Another problem is that memory devices tend to be large and occupy a significant amount of area. Hence, if most of the area on the computer chip is occupied by memory devices, then there is less area for the other devices. Further, the yield of the computer chips fabricated in a run decreases as their area increases, which increases the overall cost.
Instead of embedding the memory devices on the same surface as the other devices, the memory chip can be bonded to the computer chip to form a stack, as in a 3-D package or a 3-D integrated circuit (IC). Conventional 3-D packages and 3-D ICs both include a substrate with a memory circuit bonded to it by a bonding region positioned therebetween. The memory chip typically includes lateral memory devices which are prefabricated before the bonding takes place. In both the 3-D package and 3-D ICs, the memory and computer chips include large bonding pads coupled to their respective circuits. However, in the 3-D package, the bonding pads are connected together using wire bonds so that the memory and computer chips can communicate with each other. In the 3-D IC, the bonding pads are connected together using high pitch conductive interconnects which extend therebetween. Examples of 3-D ICs are disclosed in U.S. Pat. Nos. 5,087,585, 5,308,782, 5,355,022, 5,915,167, 5,998,808 and 6,943,067.
There are several problems, however, with using 3-D packages and 3-D ICs. One problem is that the use of wire bonds increases the access time between the computer and memory chips because the impedance of wire bonds and large contact pads is high. The contact pads are large in 3-D packages to make it easier to attach the wire bonds thereto. Similarly, the contact pads in 3-D ICs have correspondingly large capacitances which also increase the access time between the processor and memory circuits. The contact pads are large in 3-D ICs to make the alignment between the computer and memory chips easier. These chips need to be properly aligned with each other and the interconnects because the memory devices carried by the memory chip and the electronic devices carried by the computer chip are prefabricated before the bonding takes place.
Another problem with using 3-D packages and 3-D ICs is cost. The use of wire bonds is expensive because it is difficult to attach them between the processor and memory circuits and requires expensive equipment. Further, it requires expensive equipment to align the various devices in the 3-D IC. The bonding and alignment is made even more difficult and expensive because of the trend to scale devices to smaller dimensions. It is also very difficult to fabricate high pitch conductive interconnects.
Some references disclose forming an electronic device, such as a dynamic random access memory (DRAM) capacitor, by crystallizing polycrystalline and/or amorphous semiconductor material using a laser. One such electronic device is described in U.S. patent Application No. 20040131233 to Bhattacharyya. The laser is used to heat the polycrystalline or amorphous semiconductor material to form a single crystalline semiconductor material. However, a disadvantage of this method is that the laser is capable of driving the temperature of the semiconductor material to be greater than 800 degrees Celsius (° C.). In some situations, the temperature of the semiconductor material is driven to be greater than about 1000 (° C.). It should be noted that some of this heat undesirably flows to other regions of the semiconductor structure proximate to the DRAM capacitor, which can cause damage.
Accordingly, it is highly desirable to provide a new method for forming electronic devices using wafer bonding which is cost effective and reliable, and can be done at low temperature.
The present invention involves a semiconductor circuit structure, and a method of forming the semiconductor circuit structure. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.
A method for fabricating a semiconductor substrate and a method for fabricating a semiconductor device by using the same, more specifically relates to a method for fabricating a semiconductor substrate and a method for fabricating a semiconductor device by using the same more reliable and repeatable is provided. The method is comprised of, providing a first semiconductor substrate including a detaching layer in a pre-defined depth from the surface; forming ion-implanted layer around edge of the detaching layer; bonding a second semiconductor substrate to the first semiconductor substrate; forming crack in the ion-implanted layer by adding stress to the ion-implanted layer; and detaching portion of the first semiconductor substrate by spreading out the crack from the ion-implanted layer through the detaching layer, and also the method is comprised of providing a first semiconductor substrate including a detaching layer in a pre-defined depth from the surface; forming ion-implanted layer around edge of the detaching layer; bonding a second semiconductor substrate on surface of the first semiconductor substrate, wherein the second semiconductor substrate includes semiconductor devices and an isolation layer which covers the semiconductor devices on top; adding stress to the ion-implanted layer to create crack in the ion-implanted layer; detaching a portion of the first semiconductor substrate by spreading out the crack from the ion-implanted layer through the detaching layer; and forming second semiconductor devices on the first semiconductor substrate which is remained on the surface of the second semiconductor substrate. More information regarding the method disclosed herein can be found in U.S. patent application Ser. Nos. 12/581,722, 12/874,866 and 12/847,374, by the same inventor, the contents of which are incorporated by reference as though fully set forth herein.
More information regarding some of the steps disclosed herein can be found in U.S. Pat. Nos. 7,052,941, 7,378,702, 7,470,142, 7,470,598, 7,632,738, 7,633,162, 7,671,371, 7,718,508, 7,799,675, 7,800,199, 7,846,814, 7,867,822, 7,888,764, the contents of which are incorporated by reference as though fully set forth herein. More information regarding some of the steps disclosed herein can be found in U.S. Patent Application Nos. 20050280154, 20050280155, 20050280156, 20060275962, 20080032463, 20080048327, 20090267233, 20100038743, 20100133695, 20100190334, 20110001172, 20110003438 and 20110053332, the contents of which are incorporated by reference as though fully set forth herein.
More information regarding some of the steps disclosed herein can be found in U.S. Pat. Nos. 5,250,460, 5,277,748, 5,374,564, 5,374,581, 5,695,557, 5,854,123, 5,882,987, 5,980,633, 6,103,597, 6,380,046, 6,380,099, 6,423,614, 6,534,382, 6,638,834, 6,653,209, 6,774,010, 6,806,171, 6,809,009, 6,864,534, 7,067,396, 7,148,119, 7,256,104, RE39,484, as well as in U.S. Patent Application Nos. 20030205480, 20030224582 and 20070190746, the contents of which are incorporated by reference as though fully set forth herein.
A detaching layer 11 is formed on the single crystalline semiconductor substrate. The detaching layer 11 can be a porous layer which includes micro pores in the layer. The detaching layer 11 can be formed to have very small diameter cavities by anodizing silicon substrate in the HF solution (Hydrofluoric Acid). The detaching layer 11 includes many crystal structure defects in crystal so that the defects the defective crystal structure enables precise and easy detaching of the single crystalline semiconductor substrate 10 after bonding to the base substrate. A single crystalline epitaxial layer 15 can be formed on the detaching layer 11 by epitaxial growth process.
The mask pattern 17 can be circular shape which has a smaller diameter than the single crystalline semiconductor substrate 10 which is also a circular shape. By locating the mask pattern 17 on the single crystalline semiconductor substrate 10, the edge of the single crystalline epitaxial layer 15 can be exposed.
As following steps, gas-phase gases such as Hydrogen can be ion-implanted to the detaching layer 11 using the mask pattern 17 as ion-implant mask so that a ion-implanted layer 12 is formed. The ion-implanted layer 12 can aid detaching of the single crystalline semiconductor substrate 10 after bonding the single crystalline epitaxial layer 15 and the base substrate.
By forming the ion-implanted layer 12 only in the edge of the detaching layer 11 while masking inner region of the single crystalline epitaxial layer 15 using the mask pattern 17, crystal lattice structure of the single crystalline epitaxial layer 15 can be protected during the ion-implantation process.
The mask pattern 17 on the single crystalline epitaxial layer 15 is removed after forming the ion-implanted layer 12.
The base substrate 20 can be bulk silicon, bulk silicon-germanium, or silicon or silicon-germanium epitaxial layer grown on the bulk silicon or bulk silicon-germanium substrate. Also, the first semiconductor substrate 100 can include silicon-on-saphire(SOS), silicon-on-insulator(SOI), thin film transistor(TFT), doped or undoped semiconductors, silicon epitaxial layer on the base semiconductor substrate, or any other semiconductor materials that are well known to those skilled in the art.
A bonding layer 30 can be formed with, for example, photo-setting adhesive such as reaction-setting adhesive, thermal-setting adhesive, photo-setting adhesive such as UV-setting adhesive, or anaerobe adhesive. Further, the bonding layer can be, such as, metallic bonds(Ti, TiN, Al), epoxy, acrylate, or silicon adhesives. The bonding layer 30 can be used to increase bonding strength when bonding the base substrate 20 on the bonding layer 30, and also can be used to decrease micro defects which can be occurred during the bonding process.
As shown in
a illustrate a method of adding stress to sidewall of single crystalline semiconductor substrate 10 into the locally formed ion-implanted layer 12 in order to create crack at the boundary of single crystalline semiconductor substrate 10 and the single crystalline epitaxial layer 15, i.e. the ion-implanted layer 12, which is formed at the edge of the detaching layer 11, is cracked.
For example, in order to detach the single crystalline semiconductor substrate 10, a laser 50 can be irradiated to the sidewall of the ion-implanted layer 12 and locally heat up the ion-implanted layer 12. The laser 50 can heat up the ion-implanted layer 12 at the temperature of 350˜600 degree Celsius so that a crack is formed in the boundary of single crystalline semiconductor substrate 10 and the single crystalline epitaxial layer 15. Specifically, by locally heating up the ion-implanted layer 12, the volume of a cavity that comprises the detaching layer 11 is expanded and the expansion creates crack in the detaching layer 11.
Also, a high pressure waterjet can be injected into the sidewall of the ion-implanted layer 12 to add physical shock to the sidewall of the ion-implanted layer 12 so that a crack is formed in the boundary of single crystalline semiconductor substrate 10 and the single crystalline epitaxial layer 15.
The base substrate 20 on which the single crystalline semiconductor substrate 10 is bonded can be rotated while irradiating the laser 50 or injecting the waterjet in order to uniformly adding the stress to the ion-implanted layer 12 which is locally formed in the edge of the detaching layer 11. The laser 50 and waterjet can be arranged single or multiple around the single crystalline semiconductor substrate 10.
By adding local stress, the ion-implanted layer 12 is cracked to form the crack, then the crack spreads out to the detaching layer 11 continuously along with the area where crystal lattice structure is weak, as a result the single crystalline semiconductor substrate 10 and the single crystalline epitaxial layer 15 can be detached.
As shown in
By treating the surface of the single crystalline epitaxial layer 15, as shown in the
In addition to the method of detaching the single crystalline semiconductor substrate 10 and the single crystalline epitaxial layer 15 as shown
As shown in
The base substrate 20, to which the single crystalline semiconductor in
By heating the ion-implanted layer 12 using the heating device 2, a crack can be created in between the circumference of the single crystalline semiconductor substrate 10 and the single crystalline epitaxial layer 15.
As shown in
In
As a following step, isolation films 102 are formed in order to define active region. The isolation films 102 can be formed by forming trenches in the first semiconductor substrate 100 and then filling in the trenches with isolation materials such as High Density Plasma(HDP) oxide.
Then, lower region semiconductor devices are formed on the first semiconductor substrate 100 in where active region is defined.
For example, a gate conductor 110 is formed by depositing and patterning gate dielectric film and gate conductor film. After forming the gate conductor 110, dopants are ion-implanted into the first semiconductor substrate 100 at each side of the gate conductor 110 to form source/drain region 112. As a result, transistors are formed on the first semiconductor substrate 100.
In another embodiment of this invention, wirings, capacitors, diodes and/or memory devices can be formed as lower region semiconductor devices on the first semiconductor substrate 100.
Then, a first interlayer dielectric film 120 is formed which covers transistors which has a good step coverage.
Contacts and wirings 135 are formed in the first interlayer dielectric film 120. The contacts 135 can formed by etching anisotropic the first interlayer dielectric film 120, forming contacts holes which exposes source/drain region 112 or gate conductor 110, and then filling in the holes with conducting material. The wirings 135 can be connected to the contacts 135 on the first interlayer dielectric film 120.
A multiple number of second interlayer dielectric film 140 can be formed on the first interlayer dielectric film 120.
When the contacts and wirings 135 are formed, refractory metals can be used in order to decrease thermal affect from the following process steps. That is, the contacts and wirings 135 can be of many different types, such as tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride, and alloys thereof.
A third interlayer dielectric film 150, which lastly covers the cell circuitry of the semiconductor memory device formed on the first semiconductor substrate 100, and deposited and then planarized.
A bonding layer 300 is formed on the third interlayer dielectric film 150, in order to provide a single crystalline semiconductor layer on which other semiconductor devices are formed. The bonding layer 300 can be photo-setting adhesive such as reaction-setting adhesive, thermal-setting adhesive, photo-setting adhesive such as UV-setting adhesive, or anaerobe adhesive. Further, the bonding layer 300 can be, for example, metallic bond (Ti, TiN, Al), epoxy, acrylate, or silicon adhesive, and desirably can be formed with titanium which has good stability at high temperature.
The bonding layer 300 can increase bonding strength when bonding a second semiconductor substrate on the bonding layer 300, and also can decrease micro defects which can be occurred during the bonding process.
Following step is bonding the second semiconductor substrate 200 (illustrated in
A detaching layer 210 which is formed of porous layer is formed on the second semiconductor substrate 200 and then single crystalline epitaxial layer follows. At the edge boundary of the detaching layer 201, as illustrated in
Surface of the third interlayer dielectric film 150 on the first semiconductor substrate 100 and surface of the single crystalline epitaxial layer 220 are bonded each other. A thermal treatment under pre-defined pressure can be performed after bonding the second semiconductor substrate 200 on the first semiconductor substrate 100 to increase bonding strength.
As shown in
For example, a laser 500 can be irradiated to the sidewall of the ion-implanted layer 212 and locally heat up the ion-implanted layer 212. The laser 500 can heat up the ion-implanted layer 212 at the temperature of 350˜600 degree Celsius so that a crack is formed in the boundary of the second semiconductor substrate 200 and the single crystalline epitaxial layer 220. Also, a high pressure waterjet can be injected to the sidewall of the ion-implanted layer 212 to add physical shock to the sidewall of the ion-implanted layer 212 so that a crack can be formed in the boundary of the second semiconductor substrate 200 and the single crystalline epitaxial layer 220.
The first semiconductor substrate 100 on which the second semiconductor substrate 200 is bonded can be rotated while irradiating the laser 500 or injecting the waterjet in order to uniformly adding the stress to the ion-implanted layer 212. The laser 500 and waterjet can be arranged single or multiple numbers around the second semiconductor substrate 200.
When the crack is formed by locally added stress to the ion-implanted layer 212, the crack can be spread out along to the detaching layer 201 where crystal lattice structure is weak, and this results the detaching of the single crystalline epitaxial layer 220 and the second semiconductor substrate 200.
As shown in
In
As a following step, a fourth interlayer dielectric film 240 is formed to cover the transistors on the single crystalline epitaxial layer 220.
Contacts and wirings 255 can be formed in the fourth interlayer dielectric film 120. Also, contact plugs 253, which are electrically connected to the lower region semiconductor devices by penetrating the fourth interlayer dielectric film 120 and the single crystalline epitaxial layer 220, can be formed.
After forming lower region semiconductor devices, a fifth interlayer dielectric film 260 is formed by depositing isolation material.
The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2009-63943 | Jul 2010 | KR | national |
