The present application claims priority to Chinese Patent Application No. 202211242229.7, filed on Oct. 11, 2022, which is hereby incorporated by reference in its entirety.
The present disclosure relates to the technical field of semiconductors, and specifically, to a semiconductor structure and a preparation method thereof.
Gallium nitride (GaN) is a typical third generation wide band gap semiconductor, and of widely popularity. Its superior properties are mainly manifested in its high electron mobility and high two-dimensional electron gas (2 DEG) concentration. In addition, the material of gallium nitride (GaN) has stable chemical properties, high tolerance to high temperatures, high corrosion resistance, and have innate advantage in high frequency, high power and radiation resistance applications.
In a transverse GaN-based HEMT device, in order to obtain higher breakdown voltage, it is necessary to increase the gate-drain spacing, but this will inevitably increase the device size and on-resistance, reduce the effective current density per unit chip area and chip performance, and lead to the chip area increase and add to development cost. In order to solve the above problems, researchers have proposed a GaN-based vertical conductive semiconductor structure.
However, after many years of research, the current GaN-based vertical semiconductor structure still present problems of high on-resistance, low breakdown voltage and its working power still could not meet the requirements for some applications.
The purpose of the present disclosure is to provide a semiconductor structure and a preparation method thereof, to reduce on-resistance, improve breakdown voltage and increase working power.
According to one aspect of the present disclosure, a semiconductor structure is provided, and the semiconductor structure includes: a first nitride semiconductor layer including a first surface and a second surface being opposite to the first surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer, the second nitride semiconductor layer having the same conductivity type as the first nitride semiconductor layer, and the doping concentration of the second nitride semiconductor layer being lower than the doping concentration of the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer, the conductivity type of the third nitride semiconductor layer is opposite to the conductivity type of the second nitride semiconductor layer, the third nitride semiconductor layer including a groove and the groove penetrating through the third nitride semiconductor layer;
As an alternative embodiment, the second nitride semiconductor layer includes an AlGaN insertion layer located inside or on the surface of the second nitride semiconductor layer, and the bottom of the groove exposes the AlGaN insertion layer.
As an alternative embodiment, along an epitaxial growth direction, the Al composition of the AlGaN insertion layer increases from 0 of Al composition at initial growth to the maximum value A of Al composition, and then to 0 of Al composition at the end of growth; or,
As an alternative embodiment, along an epitaxial growth direction, the Al composition of the AlGaN insertion layer changes from the initial growth to the point of a maximum value Al composition in one or a combination of continuous increment, stepped increment or oscillatory increment;
As an alternative embodiment, the semiconductor structure further includes a passivation layer located on the surface of the third nitride semiconductor layer facing away from the second nitride semiconductor layer, the passivation layer is made of AlGaN, and the Al concentration in the AlGaN layer increases with the thickness of AlGaN layer.
As an alternative embodiment, the width of the groove along a direction from a bottom of the groove to a top of the groove is equal, linearly increasing, linearly decreasing, periodically varying, increasing first and decreasing after, stepped increasing or stepped decreasing.
As an alternative embodiment, a buffer layer is provided between the first nitride semiconductor layer and the second nitride semiconductor layer.
As an alternative embodiment, the third nitride semiconductor layer includes a first sub-layer of the third nitride semiconductor layer and a second sub-layer of the third nitride semiconductor layer, the first sub-layer and the second sub-layer are located from a bottom of the third nitride semiconductor layer to a top of the third semiconductor layer, and a doping concentration of the first sub-layer of the third nitride semiconductor layer is lower than the doping concentration of the second sub-layer of the third nitride semiconductor layer.
As an alternative embodiment, the source region includes a first sub-layer and a second sub-layer, the first sub-layer and the second sub-layer are located from the bottom of the source region to the top of the source region, and the doping concentration of the first sub-layer of the source region is lower than the doping concentration of the second sub-layer of the source region, where the height of the top surface of the first sub-layer of the source region does not exceed the height of the groove.
As an alternative embodiment, the third nitride semiconductor layer includes Al element, and the variation curve of the Al composition in the epitaxial growth direction includes one or more combinations of the following variation stages: periodic variation, increasing variation or decreasing variation, where the Al concentration has no jump at the contact interface between the third nitride semiconductor layer and the second nitride semiconductor layer.
As an alternative embodiment, the semiconductor structure further includes a source electrode, a gate electrode and a drain electrode, the source electrode is arranged on the source region, the gate electrode is arranged on the top surface of the third nitride semiconductor layer, and the drain electrode is arranged on the second surface of the first nitride semiconductor layer; or the semiconductor structure further includes:
According to another aspect of the present disclosure, a preparation method of the semiconductor structure is provided, and the preparation method includes:
As an alternative embodiment, the second nitride semiconductor layer includes the AlGaN insertion layer located inside or on the surface of the second nitride semiconductor layer, and the bottom of the groove exposes the AlGaN insertion layer.
As an alternative embodiment, two-step etching the third nitride semiconductor layer to form the groove, where,
As an alternative embodiment, along the epitaxial growth direction, the Al composition of the AlGaN insertion layer increases from 0 of Al composition at initial growth to the maximum value A of Al composition, and then to the 0 of Al composition at the end of growth; or along the epitaxial growth direction, the Al composition of the AlGaN insertion layer increases from 0 of Al composition to the maximum value A of Al composition or increases from 0 of Al composition to the maximum value A of Al composition and then decreases to the intermediate value B of Al composition; along the epitaxial growth direction, the Al composition of the AlGaN insertion layer decreases from the maximum value A of Al composition to 0 of Al composition or increases from the intermediate value B of Al composition to the maximum value A of Al composition and then decreases to 0 of Al composition.
As an alternative embodiment, the semiconductor structure further includes a passivation layer located on the surface of the third nitride semiconductor layer facing away from the second nitride semiconductor layer, the material of the passivation layer is AlGaN, and the Al composition in the AlGaN layer increases with the thickness of AlGaN layer.
As an alternative embodiment, the third nitride semiconductor layer is composed of Al element, and the composition variation curve of the Al composition in the epitaxial growth direction includes one or more combinations of the following variation stages: periodic variation, increasing variation or decreasing variation, where the Al composition has no jump at the contact interface between the third nitride semiconductor layer and the second nitride semiconductor layer.
As an alternative embodiment, the width of the groove along a direction from the bottom of the groove to a top of the groove is equal, linearly increasing, linearly decreasing, periodically varying, increasing first and decreasing after, stepped increasing or stepped decreasing.
As an alternative embodiment, the source region consists of a first sub-layer and a second sub-layer, the first sub-layer and the second sub-layer are located from a bottom of the source region to a top of the source region; the doping concentration of the first sub-layer of the source region is lower than the doping concentration of the second sub-layer of the source region, where the height of the upper surface of the first sub-layer of the source region does not exceed the groove.
Exemplary embodiments will be herein explained in detail, corresponding examples are shown in the accompanying drawings. In the following exemplary descriptions, when it comes to the different drawings, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments covered by the present disclosure. On the contrary, they are only examples of devices consistent with some aspects of the disclosure as detailed in the appended claims.
The terms used in the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those with ordinary skills in the field to which the present disclosure belongs. The words “first”, “second” and the like used in the present specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different compositions.
The semiconductor structure of the present disclosure and the preparation method thereof, the semiconductor structure includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and a third nitride semiconductor layer formed on the second nitride semiconductor layer with grooves penetrating through the third nitride semiconductor layer, those three nitride semiconductor layers are arranged from a bottom of the structure to a top of the device structure; and a source region formed in the groove. The semiconductor structure of the present disclosure fills semiconductor material into the etched groove. By designing the groove structure, the semiconductor structure can obtain different sizes of source region, lower on-resistance, increase on-current, avoid excessive local electric field density, optimize the electric field distribution, and thus improve the breakdown voltage.
The embodiment 1 of the present disclosure provides a semiconductor structure.
Referring to
In this embodiment, the semiconductor structure 100 is a junction field effect transistor (JFET).
The semiconductor structure 100 is described in detail below.
The materials used for the first nitride semiconductor layer 1, the second nitride semiconductor layer 2, the third nitride semiconductor layer 3 and the source region 4 could all be of GaN-based, for example, all of them can be GaN.
In this embodiment, the conductivity type of the first nitride semiconductor layer 1, the second nitride semiconductor layer 2 and the source region 4 are N-type. Where the N-type doping ions can be at least one of the followings: Si-ion, Ge-ion, Sn-ion, Se-ion or Te-ion. The conductivity type of the third nitride semiconductor layer 3 is P-type, where the P-type doping ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions or Ba ions. That being said, the junction field effect transistor (JFET) is N-channel based device. Among them, the N-type dopant concentration in the first nitride semiconductor layer 1 is large, thus the first nitride semiconductor layer is heavily N-doped while the second nitride semiconductor layer is lightly N-doped. The doping ion concentration in the first nitride semiconductor layer 1 can be above the order of 1018/cm3, the doping ion concentration in the second nitride semiconductor layer 2 can be below the order of 1018/cm3. The first nitride semiconductor layer 1, the second nitride semiconductor layer 2 or the third nitride semiconductor layer 3 may have a single layer structure or a laminated multilayer structure, and the material of each layer can be GaN, AlGaN or AlInGaN, or a mixture of at least two of the above materials.
In other embodiments, the conductivity types of the first nitride semiconductor layer 1, the second nitride semiconductor layer 2 and the source region 4 are P-type, and the conductivity type of the third nitride semiconductor layer 3 is N-type. In other words, the junction field effect transistor (JFET) is a P-type channel.
The first surface and the second surface can be two opposite surfaces in the thickness direction of the first nitride semiconductor layer 1.
The materials of the source electrode 5, the gate electrode 6 and the drain electrode 7 can be metals, such as Ti/Al/Ni/Au, Ni/Au, etc. A schottky contact can be formed between the gate electrode 6 and the third nitride semiconductor layer 3, and an ohmic contact can be formed between the source electrode 5 and the source region 4, the drain electrode 7 and the second surface of the first nitride semiconductor layer 1.
In a semiconductor structure of the embodiment 100 of the present disclosure, a groove 30 is etched through the P-type doped third nitride semiconductor layer 3, a selective secondary N-type doped source region 4 is epitaxially extended in the groove 30. Contrary to the P-N interface from the conventional ion implantation method, the P-N interface formed between the third nitride semiconductor layer and the second nitride semiconductor layer is more clear. It also helps control the shape of the grooves, reduces the on-resistance and improving the breakdown voltage of the conductor structure 100.
The preparation method of the semiconductor structure 100 may include steps S110-S170, in which:
The preparation method of the semiconductor structure provided by the embodiment of the present disclosure belongs to the same inventive concept as the semiconductor structure, and the description of relevant details and beneficial effects can be referred to each other, thus specific details will not be repeated here.
Correspondingly, the only difference between the preparation method of the semiconductor structure 200 of embodiment 2 and the preparation method of embodiment 1 lies in that the second nitride semiconductor layer 2 formed in step S120 contains the AlGaN insertion layer 12 located on the surface of the second nitride semiconductor layer 2.
Specifically, step S140 can include: forming a mask layer 8 covering the third nitride semiconductor layer 3, as shown in
The material of this mask layer 8 can be an insulating material, such as SiO2, etc. The mask layer 8 can be prepared by vapor deposition, but the embodiment of the present disclosure is not specifically limited to this.
A window 801 is formed on the mask layer 8, which exposes the third nitride semiconductor layer 3. The window 801 can be formed by etching.
Specifically, step S150 can include:
As shown in
As shown in
Specifically, S160 may include forming a source region 4 filling the groove 30, as shown in
In the disclosure, the third nitride semiconductor layer is being etched by a two-step etch process consisting dry-etch and in-situ etch process, shortly after the in-situ etch process, the source region material is secondarily epitaxially extended; on the one hand, the in-situ etch process provides a secondary etch process for the groove, restores the damage to the groove caused by conventional etching, and ensures the growth quality of GaN material of source region in the subsequent secondary epitaxial extension; on the other hand, the in-situ etch process and the subsequent epitaxial extension process are carried out in the same extension machine, carrying out both process in the same extension machine can greatly shorten the processing time and reduce the contamination sources. Optionally, the time interval between in-situ etching the groove 30 and growing the source region 4 by the subsequent epitaxial extension process is less than 1 h.
The preparation method of the semiconductor structure provided by the embodiment of the present disclosure belongs to the same inventive concept as the semiconductor structure, and the description of relevant details and beneficial effects can be referred to each other, so they will not be repeated here.
As shown in
As shown in
As shown in
As shown in
Alternatively, along the epitaxial extension growth direction, the Al composition of the AlGaN insertion layer increases from 0 of Al composition to the maximum value A of Al composition or increases from 0 of Al composition to the maximum value A of Al composition and then decreases to the intermediate value B of Al composition.
Alternatively, along the epitaxial extension growth direction, the Al composition of the AlGaN insertion layer decreases from the maximum value A of Al composition to 0 of Al composition or increases from the intermediate value B of Al composition to the maximum value A of Al composition and then decreases to 0 of Al composition.
In this embodiment, the concentration with maximum Al composition is around the middle position inside the AlGaN insertion layer 12. In other embodiments of this embodiment, the concentration with maximum Al composition inside AlGaN insertion layer 12 is close to the side of the AlGaN insertion layer 12 away from the second nitride semiconductor layer 2, in other words, close to the upper surface of the AlGaN insertion layer 12.
In the present disclosure, the AlGaN insertion layer 12 with Al composition increasing first and decreasing after, is arranged between the interface of the second nitride semiconductor layer and the third nitride semiconductor layer. The AlGaN insertion layer, on the one hand, serves as an etch stop layer to ensure the etching accuracy for the third nitride semiconductor layer; on the other hand, with the design of the concentration variation pattern of Al composition of the AlGaN intercalation layer, the nitride semiconductor layers (in contact with the upper side, lower side, or both the upper and the lower sides of the AlGaN insertion layer) have no jump change of Al composition, thus a smooth transition in material composition, reduced growth dislocation defects, and the material quality of the nitride semiconductor layer is guaranteed.
Since the AlGaN insertion layer 12 is not easily decomposed at high temperature, in-situ etching will not penetrate through the AlGaN insertion layer 12, thus the depth of the groove 30 can be accurately controlled. Optionally, in other embodiments of the second embodiment of the present disclosure, as shown in
Since the width of the groove is periodically varying, linearly increasing, linearly decreasing, increasing first and decreasing after, and the like, in the groove, the contact interface between the N-type source region and the side of the P-type third nitride semiconductor layer varies periodically or forms an inclined surface. on the one hand, with the controlling of the shape of the contact interface between the P-N junction, the reverse breakdown voltage can be effectively increased; on the other hand, during the on state, due to the periodic curved surface or inclined surface of the contact interface, the electrons flowing from the source region to the drain region can flow downward while dispersing to both side, which increases the moving path of the electrons, and thus further reduces the on-resistance of the semiconductor structure.
The conductivity type of the buffer layer 9 is the same as the conductivity type of the first nitride semiconductor layer 1. For example, the buffer layer 9 is an N-type buffer layer 9. The material of the buffer layer 9 can be GaN, AlGaN or AlInGaN, or other semiconductor materials Ga and N based, or a mixture of at least two of the above materials. A buffer layer groove 901 is formed on the surface of the buffer layer 9 facing away from the first nitride semiconductor layer 1, the buffer layer groove 901 being corresponding to the first groove 101. The buffer layer 9 can be formed by epitaxial growth, but the embodiment of the present disclosure is not particularly limited to this. The buffer layer 9 can form a buffer layer groove 901 in a conformal way during the epitaxial growth.
The conductivity type of the buffer layer 9 is opposite to the conductivity type of the first semiconductor 1. For example, the buffer layer 9 is a P-type buffer layer, which is supplemented by electrons in the first semiconductor 1 and the second semiconductor to form a depletion layer; The buffer layer 9 can be described as an alloy layer or a superlattice structure layer, and serves as a barrier layer for impurities and defects.
It should be noted that the buffer layer 9 may have a single layer structure or a laminated structure.
The semiconductor structure and its preparation method of embodiment 9 of the present disclosure are roughly the same as the semiconductor structure and the preparation method of embodiments 1 to 8 of the present disclosure. The difference is that, the third nitride semiconductor layer contains Al element, and the composition variation curve of the Al composition in the epitaxial growth direction includes one or more combinations of the following variation stages: periodic variation, increasing variation or decreasing variation, where the Al composition has no jump at the contact interface between the third nitride semiconductor layer and the second nitride semiconductor layer. By controlling of the composition variation of the Al composition of the third nitride semiconductor layer, the present disclosure can locally modulate the carrier concentration in the source region. After device optimization, the local modulation of carrier concentration can serve the following functions: during the off condition, the varying carrier concentration of the Al composition of the third nitride semiconductor layer can increase the width of the depletion layer, lower the peak of the electric field, and thus increase the breakdown voltage; during the on condition, the structure has the characteristic of reducing the on resistance, this characteristic of lowering on-resistance enables a small voltage drop during the on state when there is a high current density. As a result, the system's utilization of energy conversion efficiency is largely increased.
The above mentioned are only preferred embodiments of the present disclosure, and do not limit the present disclosure in any way. Although the disclosure has been disclosed in a preferred embodiment, it is not meant to limit the disclosure. Anyone familiar with the art can make some changes or modifications to the equivalent embodiments by using the technical content disclosed above without departing from the scope of the technical scheme of the present disclosure. However, without departing from the content of the technical scheme of the present disclosure, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present disclosure are still within the scope of the technical scheme of the present disclosure.
Number | Date | Country | Kind |
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202211242229.7 | Oct 2022 | CN | national |