Patent Application
20240113013
The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous within many products, particularly as they continue to decrease in cost and size. There is a continued desire to reduce the size of structural features and/or to provide a greater amount of structural features for a given chip size. Miniaturization, in general, allows for increased performance at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field-effect transistors (FETs), and capacitors.
Embodiments of the invention provide techniques for forming semiconductor structures with stacked interconnects.
In one embodiment, a semiconductor structure comprises a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.
In another embodiment, an interconnect structure comprises a stacked interconnect line, the stacked interconnect line comprising a first portion comprising two or more conducting line segments separated by an isolating layer and a second portion vertically stacked over the first portion, and one or more vias connecting the stacked interconnect line with an additional structure.
In another embodiment, an integrated circuit comprises a semiconductor structure comprising a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.
These and other features and advantages of embodiments described herein will become more apparent from the accompanying drawings and the following detailed description.
Illustrative embodiments of the invention may be described herein in the context of illustrative methods for forming semiconductor structures with stacked interconnects, along with illustrative apparatus, systems and devices formed using such methods. However, it is to be understood that embodiments of the invention are not limited to the illustrative methods, apparatus, systems and devices but instead are more broadly applicable to other suitable methods, apparatus, systems and devices.
It is to be understood that the various features shown in the accompanying drawings are schematic illustrations that are not necessarily drawn to scale. Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. Further, the terms “exemplary” and “illustrative” as used herein mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “illustrative” is not to be construed as preferred or advantageous over other embodiments or designs.
In semiconductor fabrication processes, a large number of semiconductor devices and conductive interconnect layers are formed in and on a single wafer or substrate. Such conductive interconnect layers provide a network of pathways that transport signals throughout an integrated circuit (e.g., connecting circuit components of an integrated circuit). Different interconnect layers may be connected to one another via a set of vias formed through the wafer. As feature sizes continue to decrease, the aspect ratio (e.g., a ratio height or depth to width) of features such as vias generally increases. It is difficult to fabricate complex structures with multiple interconnect layers and vias connecting such layers within increasingly smaller wafer footprints.
To fabricate very large scale integrated (VLSI) or ultra large scale integrated (VLSI) circuits, complex interconnect structures are required. Such interconnect structures may include a wiring interconnect network (e.g., of metallic wiring) for coupling different devices and features of devices to one another. The wiring interconnect network may include “line” features that traverse a distance across a level of a semiconductor structure, as well as “via” features that connect line features in different levels. The line features, also referred to as metal lines, may be formed of aluminum (Al), copper (Cu), tungsten (W) or another suitable material that is electrically insulated by interlayer dielectric (ILD) layers. The via features are referred to herein as being in “V” layers or levels of a semiconductor structure, while the line features are referred to as being in “M” layers or levels of the semiconductor structure.
To improve performance, the size of various features of a semiconductor structure (also referred to herein as a semiconductor chip) continue to scale. For example, transistor gate length and chip size overall continue to shrink. As a result, the interconnect structures must also shrink, which causes the aspect ratio of via features to generally increase. To improve manufacturability, lithography fabrication may utilize advanced masks that incorporate phase-shifting and optical proximity correction. As the size scale of interconnect structures decreases, overlay error between features in the interconnect structure can lead to various reliability issues. Overlay errors may result from misalignment during lithography processes, as the masks may become misaligned with the underlying structure. Although overlay errors can be reduced be re-working lithography operations, it is generally not feasible to entirely avoid some level of overlay error.
Various failure modes for interconnects may be a result of electro-migration (EM). EM failure is a result of a void forming in a conductive metal feature through metal diffusion, leading to a short or very high resistance. EM is highly dependent on a current density and cross-section of metal features. If interconnect wiring is constructed such that the intersections between vias and lines are too small, smaller voids formed by EM can lead to failure which shortens the EM lifetime.
EM may be a cause of malfunction of interconnects in integrated circuits. EM includes the physical motion of atoms out of areas where current density is high (e.g., resulting from frictional forces between metal ions and flowing electrons). EM may ultimately result in a break in a via or line. EM may be mitigated at least in part through the selection of the material used for vias and lines. For example, aluminum (Al) vias the and lines may exhibit lower EM than other materials such as copper (Cu). Thus, materials such as Cu are now predominantly used for vias and lines (more generally, for interconnects). Cu interconnects, however, are still subject to EM due to Cu diffusion during current flow. There is thus a need for increasing EM lifetime for back-end-of-line (BEOL) interconnects or other wirings.
EM performance of metal wires can be boosted by a short length effect, where the mass transport is halted by a blocking boundary. The increased stress near the blocking boundary generates a back-flow force, which compensates for the driving force of electron wind and mass transport, therefore prolonging the wire lifetime. When the length of the wire before the blocking boundary is short enough, the driving force is completely compensated by the back-flow stress and enables an immoral EM wiring lifetime independent of stress current and temperature.
Illustrative embodiments provide interconnect structures with vertically stacked metal lines (e.g., at the same line level). Such vertically stacked metal lines by themselves are isolated, but together form a continuous line in a given line level to permit current flow. To reduce the effects of EM, blocking boundaries are formed between different segments of the lines in the given line level. Such interconnect structures may be formed by forming voids in a dielectric layer (e.g., an interlayer dielectric (ILD) layer), the voids defining regions where a via level (e.g., a Vx-1 level) and first portions of a metal line level (e.g., an Mx(B) level) are to be formed. A barrier layer is then formed in the voids, followed by deposition of the interconnect material (e.g., Cu) for the via level (e.g., the Vx-1 level) and the first portions of the metal line level (e.g., the Mx(B) level). After planarization (e.g., of the Vx-/Mx(B) level) using chemical mechanical planarization (CMP) or other suitable processing, additional dielectric material is then formed and patterned over the first portion of the metal line level, and additional voids are formed in the “upper” additional dielectric material. The additional voids define regions were second portions of the metal line level (e.g., an Mx(A) level) are to be formed. A barrier layer is then formed in the additional voids, followed by interconnect material for the second portions of the metal line level (e.g., the Mx(A) level). The structure may then be planarized again (e.g., using CMP or other suitable processing).
Such stacked interconnect structures advantageously provide significantly improved EM characteristics, which enables large life stress current density (Juse) (e.g., using the short-length effect). The stacked interconnect structures also have no resistance penalty, due to the high aspect ratio (AR) and large contact areas. The stacked interconnect structures are also valuable in advanced node structures, enhancing EM characteristics without taking horizontal space, and can be used for subtractive interconnect schemes as well. The stacked interconnect structures may be used for front side and/or back side power distribution networks as well, where high Juse is critical.
The dielectric layer 102 may comprise an interlayer dielectric (ILD), and may be formed of any suitable isolating material, such as silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon oxynitride (SiON), etc. The dielectric layer 102 may have a width (in the X and Y directions) sufficient to cover the underlying structure 101 (e.g., which may include active devices, one or more additional line and via levels of additional interconnect structures, etc.).
The liner layer 108, which may also be referred to as a metal adhesion layer, a barrier layer or a protection layer, may be formed of various materials depending on the materials used for the vias 104 and the line segments 106-1, 106-2 and 106-3. The liner layer 108 may have a uniform thickness in the range of 0.3 nm to 10 nm. In some cases, the liner layer 108 may have a different bottom coverage than sidewall coverage due to the step effect or reverse bias effect. The liner layer 108 serves as a blocking boundary to the mass transport of low-resistance conductive metal inside the line segments 106-1, 106-2 and 106-3. The liner layer 108 may be formed of tantalum (Ta), tantalum nitride (TaN), a tantalum nitride and cobalt (TaN/Co) dual layer, a tantalum nitride and ruthenium (TaN/Ru) dual layer, a tantalum nitride and tantalum dual layer (TaN/Ta), etc.
The vias 104 and line segments 106-1, 106-2 and 106-3 may be formed of a low resistance metal such as copper (Cu), ruthenium (Ru), tungsten (W), cobalt (Co), rhodium (Rh), etc. The vias 104 may have widths (in the X direction) in the range of 5 nm to 10 micrometers (μall), and heights (in the Z direction) in the range of 5 nm to 10 μm. The line segments 106-1, 106-2 and 106-3 may have widths (in the X direction) in the range of 10 nm to 20 μm, and heights (in the Z direction) in the range of 10 nm to 5 μm. The spacing 105 between the line segments 106-1, 106-2 and 106-3 may be in the range of 5 nm to 1 μm.
The line segments 106-4 and 106-5 may be formed of similar materials as the line segments 106-1, 106-2 and 106-3. The line segments 106-4 and 106-5 may have widths (in the X direction) in the range of 50 nm to 20 μm, sufficient to connect adjacent ones of the line segments 106-1, 106-2 and 106-3 as illustrated. For example, the line segment 106-4 extends over portions of and connects the line segments 106-1 and 106-3. The line segment 106-5 extends over portions of and connects the line segments 106-2 and 106-3. Collectively, the line segments 106 enable interconnection from the via 104-1, to the line segment 106-1, to the line segment 106-4, to the line segment 106-3, to the line segment 106-5, to the line segment 106-2, and to the via 104-2, where the vias 104-1 and 104-2 may connect to different portions of the underlying structure 101 (e.g., to additional interconnect levels in the underlying structures, such as an Mx-1 line level and/or Vx-2 via level, to different portions of one or more active devices in the underlying structure 101, etc.). The spacing 107 between the line segments 106-4 and 106-5 may be in the range of 5 nm to 1 μm. Overlapping of the “upper” line segments 106-4 and 160-5 and the “lower” line segments 106-1, 106-2 and 106-3 can be maximized to reduce the overall line resistance.
The lengths of the line segments 106, in some embodiments, are selected so as to be shorter than a critical length (e.g., in the range of a few microns) to minimize EM effects.
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Semiconductor devices and methods for forming the same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
In some embodiments, the above-described techniques are used in connection with semiconductor devices that may require or otherwise utilize, for example, complementary metal-oxide-semiconductors (CMOS s), metal-oxide-semiconductor field-effect transistors (MOSFETs), and/or fin field-effect transistors (FinFETs). By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.
Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
In some embodiments, a semiconductor structure comprises a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.
The third conducting line segment in the second portion of the interconnect line electrically connects the first conducting line segment and the second conducting line segment in the first portion of the interconnect line.
The first portion of the interconnect line and the second portion of the interconnect line are part of a same interconnect level of an interconnect structure.
The interconnect line may provide at least a portion of a front side power distribution network, or at least a portion of a back side power distribution network.
The first conducting line segment may be connected to a first via and the second conducting line segment may be connected to a second via. At least one of the first via and the second via may be coupled to at least one additional interconnect line, or to at least a portion of an active device structure.
The first portion of the interconnect line may further comprise a fourth conducting line segment separated from the second conducting line segment by the isolating layer, and the second portion of the interconnect line may further comprise a fifth conducting line segment vertically stacked over at least a portion of the second conducting line segment and the fourth conducting line segment. The third conducting line segment and the fifth conducting line segment are separated by the isolating layer.
In some embodiments, an interconnect structure comprises a stacked interconnect line, the stacked interconnect line comprising a first portion comprising two or more conducting line segments separated by an isolating layer and a second portion vertically stacked over the first portion, and one or more vias connecting the stacked interconnect line with an additional structure.
The additional structure may comprise an additional interconnect line. The stacked interconnect line may be in a first line level of the interconnect structure and the additional interconnect line may be in a second line level of the interconnect structure.
The additional structure may comprise an active device structure. The active device structure may comprise one or more transistors.
In another embodiment, an integrated circuit comprises a semiconductor structure comprising a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.
The third conducting line segment in the second portion of the interconnect line electrically connects the first conducting line segment and the second conducting line segment in the first portion of the interconnect line.
The first portion of the interconnect line and the second portion of the interconnect line are part of a same interconnect level of an interconnect structure.
The first portion of the interconnect line may further comprise a fourth conducting line segment separated from the second conducting line segment by the isolating layer, and the second portion of the interconnect line may further comprise a fifth conducting line segment vertically stacked over at least a portion of the second conducting line segment and the fourth conducting line segment. The third conducting line segment and the fifth conducting line segment are separated by the isolating layer.
It should be understood that the various layers, structures, and regions shown in the figures are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the figures to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures are not repeated for each of the figures. It is to be understood that the terms “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, temperatures, times and other process parameters, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “approximately” or “substantially” as used herein implies that a small margin of error is present, such as ±5%, preferably less than 2% or 1% or less than the stated amount.
In the description above, various materials, dimensions and processing parameters for different elements are provided. Unless otherwise noted, such materials are given by way of example only and embodiments are not limited solely to the specific examples given. Similarly, unless otherwise noted, all dimensions and process parameters are given by way of example and embodiments are not limited solely to the specific dimensions or ranges given.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
