BRIEF DESCRIPTION OF THE DRAWINGS
The present invention can be described in greater detail with the aid of the following drawings.
FIG. 1 is an exemplary block diagram of a background art implementation of an SRAM array.
FIG. 2 is an exemplary circuit schematic diagram of a background art SRAM cell.
FIG. 3 is an exemplary waveform diagram illustrating the READ operation of the background art SRAM cell of FIG. 2.
FIG. 4 is an exemplary graph illustrating SRAM cell stability margins with technology migration/scaling.
FIG. 5 is an exemplary block diagram of the present invention.
FIG. 6 is an exemplary circuit schematic diagram of the present invention.
FIG. 7A-FIG. 7C are exemplary simulation results demonstrating the performance of the present invention.
FIG. 8 is an exemplary flow diagram of a method of the present invention.
FIG. 9 is an exemplary flow diagram of an alternative to the method of the present invention.
FIG. 10 is an exemplary flow diagram of yet another alternative to the method of the present invention.
FIG. 11 is an exemplary flow diagram of yet another embodiment of the present invention directed toward a method for testing a memory array.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention is an apparatus and method for improving the operating voltage range and stability margin of SRAM arrays. As semiconductor technology scales down to smaller feature sizes, SRAM cells are becoming more sensitive to lower operating voltages. For example, when a cell is read, the data in the SRAM cell can be disturbed or distorted.
FIG. 5 shows an exemplary block diagram of the apparatus of the present invention. In particular, FIG. 5 shows each subarray, bank or macro 506, 508, 510 of the SRAM apparatus has a mask-bit register 507, 511, 515. During functional tests, the subarrays, banks or macros are tested to a low-voltage corner by a BIST/TESTER 501. Subarrays with single-cell failures that go beyond redundancy repair capability have their mask registers set to ground (GND). Single cell failures induced in the field can be easily repaired using this circuitry. Setting the mask registers 507, 511, 515 to GND activates the SAA circuitry of the present invention. The SAA circuitry of the present invention is further discussed below.
In the present invention, distortion or disturbance of SRAM data due to READ-access is decreased by reducing the amount of charge injection from the VDD-pre-charged bit-Line BL to the low node of the cell. The quicker the BL can be discharged, the less likely an unstable cell will lose data when disturbed. Unstable cells are especially vulnerable during the half-selected (i.e., unselected operations with idle columns during WRITE or READ operations).
In contrast to the background art, the SAA feature of the present invention provides full BL amplification to both fully-selected and unselected columns. Full BL amplification improves the discharge rate of the low-node of the cell and provides data recovery by writing back the original data prior to the READ-access disturb.
FIG. 6 shows an exemplary schematic circuit diagram of the present invention and features an SAA circuitry integrated in each subarray column. In particular, with the present invention if bit-Lines BLC0, BLT0 are written to during a write operation, bit-Lines BLC1, BLT1 are concurrently sensed and fully amplified.
In contrast to the background art schematic of FIG. 1, FIG. 6 shows the present invention comprises additional SAA transistors (e.g., TX0A, TX0B, T50, TM0, TB0) in each column of the SRAM array. As shown in FIG. 6, the sense-amplifiers are set on every bit-line on both READ and WRITE cycles. Thus, the present invention provides a means for quickly discharging half-selected bit-lines during READ and WRITE operations.
In the present invention, a cross-coupled NFET SAA is included in every bit-line pair. That is, as shown in FIG. 6, a bitline pair BLT0, BLC0, has NFET SAA circuitry comprising TX0A, TX0B, T50, TM0, TB0.
Further, when a signal/MASK, as shown in FIG. 6, is set to VDD, every bit-line in the subarray has SAA circuitry that is set by a global set signal SETSA. Setting the signal /MASK, as discussed above, is defined as SAA mode.
In addition, both fully-selected bit-lines and half-selected bit-lines experience a full voltage discharge to GND after the sense-amplifiers are set in the SAA mode. In the SAA mode, the apparatus and method of the present invention provides a full WRITE-back of the read data to those cells that are disturbed during the READ operation.
Further, in the present invention, bit-lines that are half-selected during both READ and WRITE cycles realize an improvement in discharge rate. That is, with the apparatus and method of the present invention, bit-lines are quickly discharged by the cell, which in turn, rapidly discharges the internal cell node voltages (e.g., NT or NC) to GND or VSS. Further, NFETs TMO,TM1 of the SAA circuits shown in FIG. 6 provide a GND path to the sense-amplifier for all bit-lines and thus, one bit-line in each pair is fully discharged to GND.
Furthermore, the operation mode is enabled by NFETS TB0, TB1, which are controlled by the selection of the bit switch RBS0, RBS1. During the operation mode, the SAA circuitry is not required on half-selected bit-lines. In addition, the signal /MASK, as shown in FIG. 6 is set to GND or VSS. Moreover, in the operation mode, the sense-amplifier sets only one of those bit-lines that are selected. Thus, in the present invention, the sense-amplifier on half-selected bit-lines does not have a path to GND, when the signal SETSA is enabled. In the operation mode, the small signal swing on the bit-lines is preserved and the power penalty of the background art is reduced.
In another embodiment of the present invention, PFET set devices are included to further improve the power dissipation characteristics of the apparatus. The PFET set devices have a cut-off at a P-Vt above VSS and thus prevent a full bit-line discharge. In addition, the circled PFET devices adjacent to T50, T51 show yet another alternative embodiment of the present invention. That is, NFET devices T50, T51 can be replaced with the indicated PFET devices.
In particular, in this embodiment, the global bit-lines GBLC, GBLT, shown in FIG. 6, are pre-charged to VSS and driven high during read cycles by PFETs TGT, TGC. NFET devices TWC, TWT are used to reinforce the discharge of the data line during a READ operation using the feedback GBLC, GBLT driver devices. PFET device TD prevents leakage to global bit-lines in the unselected subarrays.
Fluctuations that affect cell stability margin are generally random in nature. The present invention further includes a masking function that can be enabled to mitigate the increase in power resulting from generating a full signal swing on all subarray columns. Signal amplification on half-selected Bit-Lines can be inhibited by disabling the MASK signals at the subarray level, as shown in FIG. 5. As shown in FIG. 6, during the masking operation, bit-switch signals RBS0 and RBS1 enable the sense-amplifier activation only on the selected column.
Using the exemplary schematic circuit diagram of FIG. 6 as an example, a 400 mV improvement in operating voltage is seen in simulations using a 5 sigma unbalanced cell. The area overhead of the SAA circuitry is approximately 1.2% (i.e., in a subarray with 128 cells/Bit-line). Since the implementation can be made using a hierarchical bit-line structure, the power penalty of switching bit-lines during READ and WRITE operations is relatively small.
Simulation results of the read assist feature are shown in FIG. 7A-FIG. 7C. FIG. 7A shows the voltage waveforms of write Bit Line BLT and cell nodes NC, NT for the write selected column. FIG. 7B shows data corruption of an unstable cell for the half-selected column during the write operation. FIG. 7C shows the half-selected column with the assist feature invoked. The benefits of the read-assist operation are observed when the SA set signal amplifies BLT. This in turn recovers the data in the cell by writing-back its original state.
Alternatively, in the above embodiments of the present invention, the selection/setting of the SAA circuitry can be optional. In fact, by preventing the selection/setting of the SAA, the flow-through access time of each cell can be determined.
Another embodiment of the invention is shown in the method flow diagram of FIG. 8. In particular, step 801 of FIG. 8 is directed to coupling sense-amplifier assist circuitry to each column of a memory array. Step 803 of FIG. 8 is setting the sense-amplifier assist circuitry on each column during both READ and WRITE cycles. Masking of the sense-amplifier assist circuitry that is coupled to half-selected columns is performed in step 805. Discharging bit-lines to ground on both half-selected and fully-selected columns occurs in Step 806. Step 807 of FIG. 8 is discharging the internal cell nodes of the memory array. Performing a full WRITE-back of READ data to cells of the memory array disturbed during READ cycles.
Alternatively, the above embodiment may further comprise the method shown in the flow diagram of FIG. 9. In particular, step 901 of FIG. 9 is directed to coupling sense-amplifier assist circuitry to each column of a memory array. Step 903 of FIG. 9 is setting the sense-amplifier assist circuitry on each column during both READ and WRITE cycles. Masking of the sense-amplifier assist circuitry that is coupled to half-selected columns is performed in step 905. Discharging bit-lines to ground on both half-selected and fully-selected columns occurs in Step 906. In step 907, the internal cells nodes of the memory array are discharged to ground. Performing a full WRITE-back of READ data to cells of the memory array disturbed during READ cycles occurs in step 909. Step 911 is directed to maintaining READ data timing between half-selected columns and fully-selected columns.
Preferably, the method of the present invention further comprises the method steps of the flow diagram shown in FIG. 10. In particular, as continued from FIG. 9 (i.e., see reference “A” of FIG. 9), step 1001 involves pre-charging global bit-lines to Vss during READ cycles. Reinforcing the discharge of data lines during READ cycles via feedback from global bit-lines occurs in step 1003. In particular, the step of reinforcing is performed at least when device TGT or TBC is turned on to drive global bit-lines GBLT, GBLC to a high voltage level (e.g., but not limited to VDD). This further turns on device TWT or TWC to aid in the discharge of data line DLT or DLC.
Further, Step 1005 of FIG. 10 is preventing leakage to half-selected global bit-lines. This step of preventing is realized for unselected global bit-lines in unselected subarrays, where device TD is active (i.e., SUBSEL is low). This further prevents the discharge of DLC or DLT so that both DLC and DLT are kept at their VDD pre-charge state.
FIG. 11 is yet another embodiment of the present invention. In particular, FIG. 11 discloses a method for testing a memory array as shown in the block diagram of FIG. 5. In particular, step 1101 of FIG. 11 is providing a mask bits for each of a plurality of subarrays of the memory array. Step 1103 involves setting mask bits for sense amplifier assist circuitry coupled to each of the plurality of subarrays that pass a functional test. Disabling sense amplifier assist circuitry coupled to each of the plurality of subarrays failing the functional test occurs in step 1105.
Preferably the above method further comprises functional tests that at least includes testing to a low-voltage corner. Moreover, the above embodiment further comprises disabling sense amplifier circuitry further comprises blowing a fuse for each subarray that does not pass the functional tests.
The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention, but, as mentioned above, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings and/or the skill or knowledge of the relevant art. The embodiments described herein above are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form or application disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.
Patent Application
20070291561
