Setting One or More Delays of One or More Cells in a Memory Block to Improve One or More Characteristics of the Memory Block

Abstract

In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example memory block;

FIG. 2 illustrates an example cell in a memory block;

FIG. 3 illustrates an example memory block with an example decoder; and

FIG. 4 illustrates an example subthreshold and gate tunneling leakage in a cell storing a “0”.

Claims

1. A memory block comprising: one or more bit lines that each comprise two or more cells, each cell in each bit line having a distance from a sense amplifier coupled to the bit line;each of one or more of the cells in each of one or more of the bit lines having a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

2. The memory block of claim 1, wherein the delay comprises a read delay, a write delay, or both.

3. The memory block of claim 1, wherein the setting of the delay of each of one or more of the cells in each of one or more of the bit lines enables reduction of leakage of the cell or dynamic power consumption of the memory block.

4. The memory block of claim 1, wherein the setting of the delay of each of one or more of the cells in each of one or more of the bit lines enables reduction of a static noise margin of the cell.

5. The memory block of claim 1, wherein the setting of the delay of each of one or more of the cells in each of one or more of the bit lines enables increasing read stability of the cell.

6. The memory block of claim 1, wherein the setting of the delay of each of one or more of the cells in each of one or more of the bit lines enables reduction of capacitive load on the bit line.

7. The memory block of claim 1, further comprising one or more word lines each coupled to two or more cells, each of the cells coupled to a word line having a distance from a decoder coupled to the word line, each of one or more of the cells in each of one or more of the word lines having a delay particularly set according to the distance of the cell from the decoder coupled to the word line.

8. The memory block of claim 7, wherein the delay comprises a read delay, a write delay, or both.

9. The memory block of claim 7, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables reduction of leakage of the cell or dynamic power consumption of the memory block.

10. The memory block of claim 7, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables reduction of a static noise margin of the cell.

11. The memory block of claim 7, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables increasing read stability of the cell.

12. The memory block of claim 7, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables reduction of capacitive load on the word line.

13. The system of claim 1, wherein one or more of the word lines are stitched.

14. The memory block of claim 7, wherein each of the cells coupled to a word line also has a distance from a predecoder coupled to the word line, each of one or more of the cells coupled to each word line having a delay particularly set according to the distance of the cell from the decoder coupled to the word line as well as the distance of the cell from the predecoder coupled to the word line.

15. The memory block of claim 14, wherein the delay comprises a read delay, a write delay, or both.

16. The memory block of claim 14, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables reduction of leakage of the cell or dynamic power consumption of the memory block.

17. The memory block of claim 14, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables reduction of a static noise margin of the cell.

18. The memory block of claim 14, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables increasing read stability of the cell.

19. The memory block of claim 14, wherein the setting of the delay of each of one or more of the cells in each of one or more of the word lines enables reduction of capacitative load on the word line.

20. The system of claim 1, wherein the memory block comprises one or more of: static random access memory (SRAM);ferroelectric random access memory (FRAM);read only memory (ROM);programmable read only memory (PROM);erasable programmable read only memory (EPROM);electrically erasable programmable read only memory (EEPROM);flash memory;dynamic random access memory (DRAM);magnetic random access memory (MRAM);phase change random access memory (PRAM);non volatile random access memory (NVRAM);bubble memory;ovonic unified memory (OUM);nanotube memory;molecular memory;programmable logic device (PLD);electrically programmable logic device (EPLD);generic array logic device (GAL);programmable logic array (PLA);programmable array logic (PAL);a three dimensional memory structure;content addressable memory (CAM); ora register file.

21. The system of claim 1, wherein, the delay of a cell is set by one or more of: an increased or decreased threshold voltage of each of one or more transistors in the cell;an increased or decreased length of each of one or more transistors in the cell;a reduced or increased supply voltage of the cell;an increased or decreased ground voltage of the cell;an increased or decreased back bias voltage of each of one or more transistors in the cell;a decreased or increased width of each of one or more transistors in the cell; oran increased or decreased thickness of a gate oxide in one or more transistor in the cell.

22. The system of claim 1, wherein the memory block comprises a hierarchical bit-line architecture.

23. The system of claim 1, wherein the memory block is a multiple-port memory.

24. The system of claim 1, wherein the cells each comprise six transistors.