Patent Application
20140227858
1. Technical Field
This invention relates generally to the field of semiconductors and, more particularly, to shallow trench isolation (STI) integration methods/schemes for improved wet etch removal rates and etch stopping.
2. Related Art
In current fin-based field effect transistor (FinFET) integration schemes, enhanced High Aspect Ratio Process (eHARP) is often utilized for shallow trench isolation (STI) gap fill. However, due to poor eHARP film density, severe STI-oxide recess was discovered in downstream processes. Such phenomena resulted in fin damage and poor device performance.
In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FinFET device through the use of multiple protective liners between bi-layers of refill. In a typical embodiment, a set of trenches will be etched in a substrate (e.g., silicon (Si). A shallow trench isolation (STI) layer will then be formed. The STI layer will include a first liner layer (e.g., an in-situ steam generation (ISSG)-based layer) and a second liner layer (e.g., silicon nitride (SiN) or poly-silicon). The set of trenches will then be filled (e.g., over the second liner layer) via an enhanced high aspect ratio process (eHARP) material, which will then be polished and etched back. The second liner layer will then be removed (e.g., via a hot phosphorous process or a direct thermal treatment process depending on the material used in the second liner layer), and the set of trenches will be (re)filled with a high density plasma (HDP) material that is subsequently polished and etched back. In one embodiment, a silicon layer may be deposited after the second liner layer has been removed (but before the HDP fill) for additional protection during downstream wet/dry clean processes).
A first aspect of the present invention provides a method for forming a semiconductor device, comprising: etching a set of trenches in a substrate; forming a first liner layer over the set of trenches; forming a second liner layer over the first liner layer; filling the set of trenches over the second liner layer with a first fill material; polishing and etching back the first fill material; removing the second liner layer; and refilling the set of trenches with a second fill material.
A second aspect of the present invention provides a method for forming a semiconductor device, comprising: etching a set of trenches in a substrate; forming a first liner layer over the set of trenches; forming a second liner layer over the first liner layer; filling the set of trenches over the second liner layer via an enhanced high aspect ratio process (eHARP); polishing and etching the semiconductor device after the filling; removing the second liner layer; and filling the set of trenches with a high density plasma (HDP).
A third aspect of the present invention provides a method for forming a semiconductor device, comprising: etching a set of trenches in a substrate; forming a shallow trench isolation (STI) layer, the STI layer comprising a first liner layer and a second liner layer; filling the set of trenches over the second liner layer via an enhanced high aspect ratio process (eHARP); polishing and etching the semiconductor device after the filling; removing the second liner layer; filling the set of trenches with a high density plasma (HDP); polishing the HDP; and etching back the HDP.
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements.
Illustrative embodiments will now be described more fully herein with reference to the accompanying drawings, in which embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “set” is intended to mean a quantity of at least one. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure (e.g., a first layer) is present on a second element, such as a second structure (e.g. a second layer) wherein intervening elements, such as an interface structure (e.g. interface layer) may be present between the first element and the second element.
As indicated above, aspects of the present invention relate to approaches for forming a semiconductor device such as a FinFET device through the use of multiple protective liners between bi-layers of refill. In a typical embodiment, a set of trenches will be etched in a substrate (e.g., silicon (Si). A shallow trench isolation (STI) layer will then be formed. The STI layer will include a first liner layer (e.g., an in-situ steam generation (ISSG)-based layer) and a second liner layer (e.g., silicon nitride (SiN) or poly-silicon). The set of trenches will then be filled (e.g., over the second liner layer) via an enhanced high aspect ratio process (eHARP) material, which will then be polished and etched back. The second liner layer will then be removed (e.g., via a hot phosphorous process, or a direct thermal treatment process depending on the material used in the second liner layer), and the set of trenches will be (re)filled with a high density plasma (HDP) material that is subsequently polished and etched back. In one embodiment, a silicon layer may be deposited after the second liner layer has been removed (but before the HDP fill) for additional protection during downstream wet/dry clean processes).
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In various embodiments, design tools can be provided and configured to create the data sets used to pattern the semiconductor layers as described herein. For example, data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also include hardware, software, or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules, or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance on which software runs or in which hardware is implemented. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, application-specific integrated circuits (ASIC), programmable logic arrays (PLA)s, logical components, software routines, or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.
While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.
