Patent Application
20190027370
The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of forming a field effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate structure configured to apply a control voltage that switches carrier flow in a channel formed in the body region. When a control voltage that is greater than a designated threshold voltage is applied, carrier flow occurs in the channel between the source and drain to produce a device output current.
Epitaxial semiconductor films may be used to modify the performance of field-effect transistors. For example, an epitaxial semiconductor film can be used to increase the carrier mobility through the channel of a field-effect transistor by inducing stresses in the channel. In a p-channel field-effect transistor, hole mobility can be enhanced by applying a compressive stress to the channel. One way in which the compressive stress can be applied is by embedding an epitaxial semiconductor material, such as silicon-germanium, at the ends of the channel. Similarly, electron mobility can be enhanced in an n-channel field-effect transistor by applying a tensile longitudinal stress to the channel. One way in which the tensile stress can be applied is by embedding an embedding an epitaxial semiconductor material, such as silicon doped with carbon, at the ends of the channel. The embedded stressors may operate as portions of source and drain regions of the field effect transistor, and as a dopant supply for other portions of the source and drain regions.
When embedded source and drain regions are in closer proximity to the channel region, transistor performance generally improves because of increased strain. However, with a short gate length, there is a point at which closer-embedded source and drain proximity to the channel results in transistor performance degradation due to increased off-state leakage. Moving forward to smaller transistor technologies, it may be desirable to shrink to shorter gate lengths, while maintaining strain from embedded source and drain regions without suffering increases in off-state leakage.
Accordingly, improved methods of forming a field effect transistor are needed.
In an embodiment of the invention, a method is provided for forming a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a cavity extending through the semiconductor fin and into a substrate fin underlying the semiconductor fin. After the cavity is formed, the semiconductor fin is etched selective to the substrate fin with a second etching process to widen a portion of the cavity.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
With reference to
Gate structures 14 of a multi-gate field effect transistor are arranged on a top surface 13 of the semiconductor fin 12 and overlap with the semiconductor fin 12 at spaced apart locations. The gate structures 14 may also be located on trench isolation (not shown) in the substrate fin 10 adjacent to the semiconductor fin 12. Each gate structure 14 includes a gate electrode 15 and a gate dielectric 17 interposed between the gate electrode and the substrate fin 10. The gate electrode 15 may be composed of polycrystalline silicon (i.e., polysilicon), or may include one or more conformal barrier metal layers and/or work function metal layers composed of conductors, such as metals (e.g., tungsten (W)) and/or metal nitrides or carbides (e.g., titanium nitride (TiN) and titanium aluminum carbide (TiAlC)). The gate dielectric 17 may be composed of a dielectric material, such as silicon dioxide (SiO2) or a high-k dielectric material like hafnium oxide (HfO2). The gate structures 14 may be functional gate structures or, in the alternative, sacrificial gate structures that are removed and replaced in a replacement metal gate process. The term “sacrificial gate structure” as used herein refers to a placeholder structure for a functional gate structure to be subsequently formed. The term “functional gate structure” as used herein refers to a permanent gate structure used to control output current (i.e., flow of carriers in the channel) of a semiconductor device.
Sidewall spacers 18 are positioned on the top surface of the semiconductor fin 12 at locations adjacent to the vertical sidewalls of each gate structure 14. The sidewall spacers 18 may be composed of a dielectric material, such as a low-k dielectric material like silicon oxycarbonitride (SiOCN), deposited as a conformal layer by atomic layer deposition (ALD) and etched with a directional etching process, such as reactive ion etching (ME). A gate cap 20 is arranged on the top surface of the gate electrode of each gate structure 14 and in a space laterally between the sidewall spacers 18. The gate caps 20 may be composed of a dielectric material, such as silicon nitride (Si3N4), deposited by chemical vapor deposition (CVD), and are present to prevent epitaxial grown on the gate structures 14 during subsequent source and drain formation.
With reference to
The cavity 22 divides the semiconductor fin 12 into distinct channel regions 12a, 12b. One of the channel regions 12a is associated with one of the gate structures 14, and the other of the channel regions 12b is associated with the adjacent gate structure 14. During operation with a control voltage applied to the gate electrodes of the gate structures 14, carrier flow occurs in the channel regions 12a, 12b.
A bottom surface 24 of the portion of the cavity 22 in the substrate fin 10 and below the interface 11 may have a u-shaped curvature. Above the interface 11, the channel regions 12a, 12b are accessible at their side surfaces 26 through the cavity 22. The side surfaces 26 the channel regions 12a, 12b in the portion of the cavity 22 extending through the semiconductor fin 12 are contained in planes spaced apart from each other by the width, w, of the cavity 22, and the planes containing the side surfaces 26 may have a vertical orientation and may be oriented parallel to each other.
With reference to
The etching process may be a wet chemical etching process that relies on an etch chemistry such as a mixture of peroxide with a base, such as a mixture of water (H2O), hydrogen peroxide (H2O2), and ammonium hydroxide (NH4OH) (i.e., a hot SC1 clean), of buffered or dilute hydrochloride acid. Alternatively, the etching process may be a selective dry etch-back process. The lateral recessing of the semiconductor fin 12 decreases the gate length and increases the proximity of subsequently-formed source/drain regions to the channel regions 12a, 12b.
With reference to
An epitaxial growth process may be used to deposit semiconductor material, such as silicon germanium (SiGe) or carbon-doped silicon (Si:C), to form the embedded source/drain region 30, and may include in situ doping during growth to impart a given conductivity type to the grown semiconductor material. In an embodiment, the embedded source/drain region 30 may be formed by a selective epitaxial growth process in which semiconductor material nucleates for epitaxial growth on semiconductor surfaces, but does not nucleate for epitaxial growth from insulator surfaces. As used herein, the term “source/drain region” means a doped region of semiconductor material that can function as either a source or a drain of a field-effect transistor. For a p-type field-effect transistor, the semiconductor material of the embedded source/drain region 30 may be doped with a p-type dopant selected from Group III of the Periodic Table (e.g., boron (B)) that is effective to impart p-type conductivity. For an n-type field-effect transistor, the semiconductor material of the embedded source/drain region 30 may be doped with an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P) or arsenic (As)) that is effective to impart n-type conductivity.
The embedded source/drain region 30 may be strained and incorporate internal stress through control over the conditions and parameters characterizing the epitaxial growth process. The embedded source/drain region 30 may operate as stressors that transfer stress to the channel regions 12a, 12b of the semiconductor fin 12 such that the channel regions 12a, 12b are placed under stain, which may increase carrier mobility in channels formed during device operation. If the embedded source/drain region 30 is composed of Si:C, tensile strain may be produced in the channel regions 12a, 12b, which may be appropriate for an n-type field-effect transistor. If the embedded source/drain region 30 is composed of SiGe, compressive strain may be produced in the channel regions 12a, 12b, which may be appropriate for a p-type field-effect transistor.
The formation of the cavity 22 with two distinct etching processes of different characteristics, isotropy and anisotropy, decouples the depth of the cavity 22 from the proximity of the cavity to the channel region 12a or channel region 12b of the field-effect transistor. The widening of the cavity 22 by the isotropic etching process defines the proximity of the source and drain junctions, and also places the stress from the epitaxial semiconductor material of the embedded source/drain region 30 in the widened portion of the cavity 22 closer to the channel region 12a or channel region 12b. The depth of the cavity 22 may be increased to further scale volume/strain without impacting electrostatics (e.g., without introducing a drain-induced barrier lowering (DIBL) penalty or an off-state leakage current (Ioff) penalty).
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
