The present invention relates to shared contacts that are provided between a gate of one MOSFET transistor and a source or drain region of another MOSFET transistor, for example, within SRAM devices.
MOSFET devices are widely used in electronic products. One common example of a MOSFET device is a static random access memory (SRAM) device, which holds binary information. SRAMs are frequently used in the electronics industry, due to their combination of speed, low power, and lack of requirement for refresh.
Standard SRAM cells commonly use cross-coupled inverters, having two N-channel and two P-channel transistors each, accessed by two pass transistors. Such cells are sometimes referred to as “6T” cells, since (with the two pass transistors) they have six transistors per cell, although other configurations are possible (e.g., four pass transistors are used to access the SRAM cell in 2-port memory devices, etc.).
An equivalent circuit for a conventional SRAM circuit is shown in
In circuits that utilize MOSFET devices, including SRAMs, a gate electrode of one transistor may be directly connected with a neighboring source or drain region of another transistor. If the gate electrode and the source/drain region are closely arranged, a shared contact may be formed for electrical connection, instead of separate contacts. Shared contacts are advantageous, for example, in that a reduction in cell size is generally achieved as the number of contacts decreases.
For example,
A specific conventional example of a shared contact region of an SRAM cell is shown in schematic cross-section in
The conventional structure shown in
An alternative approach is shown in
The above and other drawbacks of devices having shared contacts are addressed by the present invention, in which electronic devices are provided that comprise a doped semiconductor shared contact between a gate conductor region of at least one transistor and a diffusion region of at least one transistor.
One specific example of such a shared contact, among many others, is a doped SiGe shared contact between (a) a gate conductor region shared by an N-channel MOSFET and a P-channel MOSFET and (b) a drain diffusion region of an N-channel MOSFET or of a P-channel MOSFET. Numerous other examples are discussed in the Detailed Description below.
An advantage of the present invention is that problems associated with alignment, etch stops and metal filling that are experienced with other shared contact designs are avoided.
These and other aspects, embodiments and advantages of the present invention will become immediately apparent to those of ordinary skill in the art upon review of the Detailed Description and Claims to follow.
A more complete understanding of the present invention is available by reference to the following detailed description of various aspects and embodiments of the invention. The detailed description of the invention which follows is intended to illustrate but not limit the invention. The scope of the invention is defined by the claims.
In general, electronic devices benefiting from the present invention are MOSFET devices for which it is desired to provide a shared contact between a gate conductor region of at least one transistor and a diffusion region of at least one other transistor (e.g., between a gate conductor region positioned over a semiconductor substrate and a diffusion region within the substrate, such as a source or drain diffusion region). In the present invention, the shared contact is a doped semiconductor shared contact.
In the partial cross-sectional view of
Between the isolation regions 20a and 20b is provided a P well 12p, which is typically doped with a P-type dopant such as boron, among others, to a doping concentration ranging from 1×10̂15 to 1×10̂17 cm−3 and to a maximum depth ranging from 50 nm to 200 nm. Between the isolation regions 20b and 20c is provided an N well 12p, which is typically doped with a N-type dopant such as arsenic or phosphorous, among others, to a doping concentration ranging from 1×10̂15 to 1×10̂17 cm−3and to a maximum depth ranging from 50 nm to 200 nm.
Proximate the surface of the P well 12p are N-type diffusion regions 14na and 14nb, which typically have a maximum doping concentration ranging from 1×10̂13 to 1×10̂15 cm−3 and a maximum depth ranging from 400 nm to 800 nm. Proximate the surface of the N well 12n are P-type diffusion regions 14pa and 14pb, which typically have a maximum doping concentration ranging from 1×10̂13 to 1×10̂15 cm−3 and a maximum depth ranging from 400 nm to 800 nm.
Over the P and N wells 12p, 12n are provided gate regions 34a and 34b, each of which includes a gate conductor (e.g., doped polysilicon having a conductivity ranging from 0.01 ohm-cm to 1 ohm-cm) separated from the substrate 10 by a gate dielectric (e.g., silicon oxide having a thickness ranging from 8 to 20 Angstroms). The gate regions 34a, 34b are flanked by dielectric spacers, formed from a material such as silicon oxide or silicon nitride, among others.
A doped semiconductor shared contact such as a doped SiGe shared contact 36 is provided over, and in electrical contact with, a portion of gate region 34a and a portion of N-type diffusion 14n. It is note that in the present example, the left and right diffusion regions 14na and 14nb are connected, however, in other applications, the diffusion regions are separate. In the embodiment illustrated, embedded SiGe regions 36a, 36b are also provided at the surface of the P-type diffusion regions 14pa and 14pb. The doped SiGe regions are typically about 25 nm to 100 nm in thickness and having a maximum doping concentration ranging from 1×10̂15 to 1×1̂17 cm−3. Typical dopants are N-type dopants such as phosphorus. The molar ratio of silicon to germanium in the alloy typically ranges from 2:1 to 1:2.
Contacts 32a, 32b, 32c, typically metallic contacts such as tungsten, are provided within a dielectric layer 30 such as silicon dioxide or silicon nitride. Over the dielectric layer 30 are disposed conductive interconnects 42a, 42b, typically metallic interconnects such as tungsten. Interconnect 42a is in electrical contact with contacts 32a, 32b, whereas interconnect 42 is in electrical contact with contact 32c.
In the particular embodiment shown in
One of ordinary skill in the art will recognize, however, that innumerable other schemes are possible.
An exemplary scheme for making the device
A semiconductor substrate 10, for example, a silicon substrate, is provided, whereupon dielectric isolation regions 20 are formed in the substrate using a process such as an STI (shallow trench isolation) or a LOCOS (local oxidation of silicon) process. N and P wells 12p, 12n are then formed, followed, if desired, by VT adjust implants. A gate oxide layer (not separately illustrated), a doped polysilicon layer and a dielectric layer (e.g., SiN) are then formed over the substrate 10 and patterned, creating the gate structures 34a, 34b for the device which have dielectric caps 37a, 37b. Tip/halo implants may also be performed, if desired, followed by deposition of a spacer dielectric layer 35, such as silicon oxide or silicon nitride. After masking the P well (N channel) regions of the device, spacers 35b are etched in the N well (P channel regions), for example, by performing a dry etching step. This is followed the formation of recesses 12r in the N well 12n, for example, using a dry etching step. The mask is then removed from the P-well regions, resulting in the structure shown in
A further mask is then provided, and a hole is then patterned in the dielectric layers 35, 37a through an aperture in the further mask, for example, via an additional etch step. The further mask is removed, and an SiGe epitaxial layer is then grown over the device surface, for example, by a silicon epitaxial growth process, thereby forming SiGe shared contact 36c, and well as recessed SiGe regions 36a and 36b. The resulting structure is shown in
The spacer dielectric layer 35 is then etched in the P well region (with or without a mask over the N well region), thereby forming spacer 35a on left side of the gate 34a. N impurity ions are then implanted/diffused in the P well region, forming diffusion regions 14na and 14nb. Similarly, P impurity ions are implanted/diffused in the N well region, forming diffusion regions 14pa and 14pb. The resulting structure is illustrated in
A dielectric layer 30, such as a layer of silicon dioxide, is then deposited over the structure of
An additional conductive layer is then deposited, masked and etched to form interconnects 42a, 42b, as illustrated in
Although various embodiments are specifically illustrated and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and are within the purview of the appended claims without departing from the spirit and intended scope of the invention.
Number | Date | Country | |
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Parent | 11064586 | Feb 2005 | US |
Child | 14120399 | US |