Patent Application
20240006297
Embodiments of the present disclosure generally relate to the field of package assemblies, and in particular package assemblies that include substrates with copper traces.
Continued reduction in end product size of mobile electronic devices such as smart phones and ultrabooks is a driving force for the development of reduced size system in package components. As speed requirements between dies on a package, for example between a compute die and a memory die, continues to increase, density of traces in a package substrate will continue to increase, and the increased signal frequency and speed of transmission on these traces will become increasingly important.
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to increasing the speed and density of input/output (I/O) on substrates by using unroughened surfaces on the pads or traces to achieve higher signal frequency and higher speeds, and reduce insertion loss, through transmission lines that go through the surfaces. In embodiments, a silicide layer, which may be referred to as a silicide interlayer, and a silicon nitride layer may be placed between a copper trace and a dielectric on the copper trace to reduce the delamination risk of the dielectric from the copper trace. In embodiments, this allows a strong bond between the copper trace and the dielectric without having to roughen a surface of the copper trace prior to applying the dielectric. Embodiments may result in unroughened copper trace surfaces and a higher life of the substrate and packages to which the substrate is included. Embodiments may be referred to as sequential interlayers between a dielectric and copper.
In embodiments described herein, a silicide interlayer may be formed between a copper trace, or other copper feature on or in a substrate, and a silicon nitride layer around the copper trace to enhance the adhesion of the silicon nitride to the copper trace. In conjunction with the silicon nitride layer, these embodiments may provide a strong adhesion of the copper traces to a dielectric that at least partially surrounds the copper traces, without requiring roughening a surface of the copper traces. In legacy implementations, when a surface of the copper feature, including a trace, is roughened, there is a loss of the copper, which decreases the plated dimensions of the copper feature.
In embodiments, the silicide interlayer and the silicon nitride layer may be applied using a single-tool during the manufacturing process, for example a chemical vapor deposition (CVD) process that involves a physical vapor deposition (PVD) process that involves plasma assisted deposition. In embodiments, the silicide interlayer may be a copper silicide interlayer. This may be referred to as a chemical-based adhesion process.
Substrates for next generation chip-to-chip interconnect technologies require higher speed and higher density input/output (IO) routing through interconnects and substrates. For example, higher speed I/O data transfer is important in order to enable support for next generation Serializer/Deserializer (SerDes) interconnects that operate at speeds of 28 GHz or greater, that operate at high frequencies will having low signal losses.
At high frequencies, a significant majority of the signal transfer is close to the surface of the conductor, for example copper traces, an effect known as the “skin effect.” At 1 MHz signal transfer, this skin effect depth is about 66 μm while at 28 GHz it reduces to about 400 nm, and reduces to about 200 nm at 100 GHz. Hence, trace roughness and the surface of the conductor starts playing a significant role in reducing signal losses at higher frequencies.
Also, the density of I/O for an interconnect is based on a variety of factors that include via size, line/space pitch, bump pitch, via-to-pad alignment, pad-to-via alignment, and material properties that include organic-based dielectric materials. For example, legacy processes to produce an interconnect with a 110 μm bump pitch results in less than 20 IO/mm/layer, for example 49 μm diameter vias, 9/12 μm L/S, and 14 μm alignment. Very high I/O density interconnects, for example densities greater than 100 IO/mm/layer, calls for advanced patterning, alignment and via formation.
Reducing the routing pitch will facilitate I/O density scaling. For example, scaling the routing pitch down to 2/2 μm. However, 2/2 μm fine line space (FLS) fabrication using a traditional semi-additive process tool and material set is a challenge, particularity with respect to limits in high resolution exposure, reduced loss of copper from copper traces due to roughening of the copper trace surfaces used for trace-to-dielectric adhesion, seed etch and thin dielectric for improved electrical performance. For example, embodiments described herein may facilitate 2/2 μm LS fabrication by transitioning away from mechanical adhesion by roughening copper trace surfaces, and moving toward chemical adhesion in order to minimize the loss of copper trace due to roughening.
Embodiments described herein are directed to improving the adhesion of the dielectric material, which may include an organic polymer/inorganic filler composite, to an unroughened copper surface. The copper layer may be pre-treated in the form of oxide removal or an inductively coupled plasma treatment for delivering a pristine copper surface.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent.
As used herein, the term “module” may refer to, be part of, or include an ASIC, an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
Various Figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.
The intermediate layer 102b may include copper features 106 that are on the bottom layer 102a. The copper features 106 in implementations may be traces. A second dielectric 108 may be on the copper features 106. Copper traces 110 may be on the second dielectric 108 and in the upper layer 102c. In implementations, the copper traces 110 may be pads onto which copper vias (not shown) or some other copper connections may be placed onto a roughened surface 110a of the copper traces 110. In implementations, a third dielectric 112 may be placed on the copper traces 110. Vias 114 may be created, for example, by drilling through the third dielectric 112 to expose the roughened surface 110a of the copper traces 110.
In implementations, to prevent delamination of the third dielectric 112 from the surfaces of the copper traces 110, the surfaces of the copper traces may be roughened, as shown in the blowup of area 100 shown in diagram 100. This may be referred to as part of a mechanical adhesion process. In implementations, the roughened surface 110a may be roughened using a wet chemical-based process for roughening the copper traces 110 before the third dielectric 112 is applied. As a result, the roughened surface 110a provides a mechanical anchor, as well as additional surface area, for the third dielectric 112 to bond with the copper trace 110.
Although in these legacy implementations the third dielectric 112 is securely anchored to the traces 110, the legacy roughening technique creates challenges. First, a distance between copper traces 110 may increase due to the impact of the etch-based roughening process. Second, the roughened surface 110a creates insertion losses for AC signal transduction, especially in high speed applications. These effects combined together result in significant performance limitations of electronic packaging substrates.
The intermediate layer 252b may include copper features 256 that are on the bottom layer 252a. The copper features 256 in embodiments may be traces. A second dielectric 258 may be on the copper features 256. Copper traces 260 may be on the second dielectric 258 and in the upper layer 252c. In implementations, the copper traces 260 may be pads onto which copper (not shown) or other electrically conductive material may be placed onto a surface 260a of the copper traces 260 that form a portion of a signal transmission line. In implementations, a third dielectric 262 may be placed on the copper traces 260. Vias 264 may be created, for example by drilling, through the third dielectric 262 to expose the surface 260a of the copper traces 260. In embodiments, the first dielectric 254, the second dielectric 258, and the third dielectric 262 may include the same materials, or may include different materials.
In embodiments, a silicide layer 270 may be placed on the surface of the second dielectric 258 after the copper traces 260 are placed on the dielectric 258. In embodiments, the silicide layer 270 may be a copper silicide, cobalt silicide, ruthenium silicide, or tungsten silicide layer. In embodiments, the silicide layer 270 may have a thickness of 2 μm or less. In embodiments, a thickness of the silicide layer 270 may be variable. In embodiments, as described further below, the silicide layer 270 may be deposited using a CVD plasma process.
In embodiments, a silicon nitride (SiNx) layer 272 may be deposited on the silicide layer 270, with the third dielectric 262 placed on the silicon nitride layer 272. In embodiments, the silicide layer 270 may form a chemical bond with the silicon nitride layer 272. This, in conjunction with the tight chemical bond that is formed between the silicon nitride layer 272 and the third dielectric 262, the third dielectric 262 as a result may be tightly chemically adhered to the copper trace 260. In some embodiments, the silicide layer 270 may be omitted, and only a silicon nitride layer 272 may be placed between the third dielectric 262 and the copper trace 260.
In embodiments, the surface 260a of the copper trace 260 may be unroughened, as shown in the blowup of the area 250. In embodiments, the surface 260a may be less than a 100 nm arithmetic mean roughness (Ra) in roughness, while roughened layers typically are greater than 100 nm Ra in roughness. In embodiments, the surface 260a of the copper trace 260 does not require roughening.
In embodiments, copper traces 356 may be placed on the first layer 352a. In embodiments, the copper traces 356 may be electrical routing features, or may be some other copper feature. In embodiments, the copper traces 360 may be copper pads. A second dielectric 358 may be placed on the first layer 352a and surround the copper traces 356. In embodiments, the second dielectric 358 may be similar to the first dielectric 354. In embodiments, copper traces 360 may be placed on the second dielectric 358 of layer 352b. The copper traces 360 may be formed using standard techniques, for example electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
Subsequent to the placement of the third dielectric 362, vias 364 may be formed through the third dielectric 362 to expose a surface 360a of copper trace 360. In embodiments, the vias 364 may be formed using a mechanical or laser drill and reach the surface 360a of the copper trace 360. In embodiments, the surface 360a may be ablated or abraded in preparation for forming a direct copper-to-copper interconnect when copper is placed into the via 364. Note that in the embodiments the surface 360a has not been roughened. Area 350 is shown as a blow up in
In embodiments, copper traces 456 may be placed on the first layer 452a. In embodiments, the copper traces 456 may be electrical routing features, or may be some other copper feature. A second dielectric 458 may be placed on the first layer 452a and surround the copper traces 456. In embodiments, the second dielectric 458 may be the same or may be different than the first dielectric 454. In embodiments, copper traces 460 may be placed on the second dielectric 458 of layer 452b. In embodiments, the copper traces 460 may be copper pads. The copper traces 460 may be formed using standard techniques.
At block 602, the process may include providing a first dielectric layer. In embodiments, the first dielectric layer may be similar to second dielectric 258 within intermediate layer 252b of
At block 604, the process may further include placing a trace on the first dielectric layer. In embodiments, the trace may be similar to copper trace 260 of
At block 606, the process may further include placing a layer of silicide on the trace and on the first dielectric layer. In embodiments, the layer of silicide may be similar to the silicide layer 270 of
At block 608, the process may further include placing a layer of silicon nitride on the layer of silicide. In embodiments, the layer of silicon nitride may be similar to silicon nitride layer 272 of
At block 610, the process may further include placing a second dielectric layer on the layer of silicon nitride. In embodiments, the second dielectric layer may be similar to third dielectric 362 within layer 352c of
In an embodiment, the electronic system 700 is a computer system that includes a system bus 720 to electrically couple the various components of the electronic system 700. The system bus 720 is a single bus or any combination of busses according to various embodiments. The electronic system 700 includes a voltage source 730 that provides power to the integrated circuit 710. In some embodiments, the voltage source 730 supplies current to the integrated circuit 710 through the system bus 720.
The integrated circuit 710 is electrically coupled to the system bus 720 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 710 includes a processor 712 that can be of any type. As used herein, the processor 712 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 712 includes, or is coupled with, silicide and silicon nitride layers between a dielectric and copper, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 710 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 714 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 710 includes on-die memory 716 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 710 includes embedded on-die memory 716 such as embedded dynamic random-access memory (eDRAM).
In an embodiment, the integrated circuit 710 is complemented with a subsequent integrated circuit 711. Useful embodiments include a dual processor 713 and a dual communications circuit 715 and dual on-die memory 717 such as SRAM. In an embodiment, the dual integrated circuit 710 includes embedded on-die memory 717 such as eDRAM.
In an embodiment, the electronic system 700 also includes an external memory 740 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 742 in the form of RAM, one or more hard drives 744, and/or one or more drives that handle removable media 746, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 740 may also be embedded memory 748 such as the first die in a die stack, according to an embodiment.
In an embodiment, the electronic system 700 also includes a display device 750, an audio output 760. In an embodiment, the electronic system 700 includes an input device such as a controller 770 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 700. In an embodiment, an input device 770 is a camera. In an embodiment, an input device 770 is a digital sound recorder. In an embodiment, an input device 770 is a camera and a digital sound recorder.
As shown herein, the integrated circuit 710 can be implemented in a number of different embodiments, including a package substrate having silicide and silicon nitride layers between a dielectric and copper, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate having silicide and silicon nitride layers between a dielectric and copper, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates having silicide and silicon nitride layers between a dielectric and copper embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line of
The following paragraphs describe examples of various embodiments.
Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the “and” may be “and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.
These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
