Patent Application
20230261042
The present disclosure relates to a silicon carbide semiconductor device. The present application claims a priority based on Japanese Patent Application No. 2020-118899 filed on Jul. 10, 2020, the entire contents of which are incorporated herein by reference.
WO 2017/179377 (PTL 1) describes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a super junction structure Each of Japanese National Patent Publication No. 2019-520703 (PTL 2) and Japanese Patent Laying-Open No. 2015-216182 (PTL 3) describes a super junction structure of a silicon carbide semiconductor formed by ion implantation employing a channeling phenomenon.
A silicon carbide semiconductor device according to the present disclosure includes a substrate, a super junction layer, an element layer, a first electrode, and a second electrode. The substrate is composed of a silicon carbide semiconductor having a first conductivity type. The super junction layer is provided above a first main surface of the substrate and alternately has a first region having the first conductivity type and a second region having a second conductivity type. The element layer is provided above the super junction layer. A first electrode is provided on the element layer. The second electrode is provided on a second main surface of the substrate opposite to the first main surface. The first region has a first portion and a second portion located between the first portion and the first main surface. The second region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the first main surface. In a cross section perpendicular to the second main surface and parallel to a direction from the first region toward the second region, a width of the second portion is larger than a width of the first portion, a width of the fourth portion is smaller than a width of the third portion, a total value of the width of the first portion and the width of the third portion is 0.5 µm or more and 4 µm or less, and a height of each of the first region and the second region is 2 µm or more.
It is an object of the present disclosure to provide a silicon carbide semiconductor device to improve breakdown voltage while reducing on-resistance.
According to the present disclosure, there can be provided a silicon carbide semiconductor device to improve breakdown voltage while reducing on-resistance.
First, embodiments of the present disclosure are listed and described. Regarding crystallographic indications in the present specification, an individual orientation is represented by [], a group orientation is represented by <>, and an individual plane is represented by (), and a group plane is represented by {}. A crystallographically negative index is normally expressed by putting “-” (bar) above a numeral; however, in the present specification, the crystallographically negative index is expressed by putting a negative sign before the numeral.
(1) A silicon carbide semiconductor device 100 according to the present disclosure includes a substrate 11, a super junction layer 10, an element layer 40, a first electrode 61, and a second electrode 62. Substrate 11 is composed of a silicon carbide semiconductor having a first conductivity type. Super junction layer 10 is provided above first main surface 1 of substrate 11, and alternately has a first region 41 having the first conductivity type and a second region 42 having a second conductivity type. Element layer 40 is provided above super junction layer 10. First electrode 61 is provided on element layer 40. Second electrode 62 is provided on a second main surface 2 of substrate 11 opposite to first main surface 1. First region 41 has a first portion 71 and a second portion 72 located between first portion 71 and first main surface 1. Second region 42 has a third portion 73 in contact with first portion 71 and a fourth portion 74 in contact with second portion 72 and located between third portion 73 and first main surface 1. In a cross section perpendicular to second main surface 2 and parallel to a direction from first region 41 toward second region 42, a width of second portion 72 is larger than a width of first portion 71, a width of fourth portion 74 is smaller than a width of third portion 73, a total value of the width of first portion 71 and the width of third portion 73 is 0.5 µm or more and 4 µm or less, and a height of each of first region 41 and second region 42 is 2 µm or more.
(2) In silicon carbide semiconductor device 100 according to (1), in the cross section perpendicular to second main surface 2 and parallel to the direction from first region 41 toward second region 42, the width of first portion 71 may be smaller than a height of first portion 71, and the width of third portion 73 may be smaller than a height of third portion 73.
(3) In silicon carbide semiconductor device 100 according to (1) or (2), an impurity concentration in third portion 73 may be higher than an impurity concentration in fourth portion 74.
(4) In silicon carbide semiconductor device 100 according to any one of (1) to (3), an impurity concentration of each of first portion 71 and third portion 73 may be 3×1016 cm.-3 or more and 5×1017 cm.-3 or less.
(5) In silicon carbide semiconductor device 100 according to any one of (1) to (4), a buffer layer 12 having the first conductivity type may be provided between super junction layer 10 and substrate 11.
(6) In silicon carbide semiconductor device 100 according to any one of (1) to (5), element layer 40 may include a first impurity region 15 having the first conductivity type, a second impurity region 23 in contact with first impurity region 15 and having the second conductivity type, and a third impurity region 30 separated from first impurity region 15 by second impurity region 23 and having the first conductivity type. Element layer 40 may be provided with a trench 5 that has a side surface 8 constituted of each of first impurity region 15, second impurity region 23, and third impurity region 30, and that has a bottom portion 9 contiguous to side surface 8 and constituted of first impurity region 15. First electrode 61 may be a source electrode, and second electrode 62 may be a drain electrode. A gate electrode may be provided inside trench 5.
(7) In silicon carbide semiconductor device 100 according to any one of (1) to (6), first main surface 1 may correspond to a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane.
Hereinafter, embodiments of the present disclosure will be described in detail. In the description below, the same or corresponding elements are denoted by the same reference characters, and will not be described repeatedly
First, a configuration of a silicon carbide semiconductor device 100 according to a first embodiment will be described.
As shown in
Substrate 11 is composed of, for example, hexagonal silicon carbide having polytype 4H. First main surface 1 may correspond to, for example, a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. Specifically, first main surface 1 may correspond to a (0001) plane or a plane inclined at an angle of 8° or less with respect to the (0001) plane. First main surface 1 may correspond to a (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane.
Buffer layer 12 is located between super junction layer 10 and substrate 11. Buffer layer 12 has, for example, the n type conductivity (first conductivity type). Buffer layer 12 includes an n type impurity that can provide the n type conductivity, such as N (nitrogen).
Super junction layer 10 is provided above first main surface 1 of substrate 11 Super junction layer 10 is in contact with buffer layer 12. Super junction layer 10 alternately has first regions 41 and second regions 42. For example, first regions 41 and second regions 42 are alternately arranged along a direction (first direction 101) parallel to first main surface 1. From another viewpoint, for example, it can be said that first regions 41 and second regions 42 are alternately arranged along a direction intersecting a thickness direction of substrate 11.
First region 41 has the n type conductivity (first conductivity type). First region 41 includes an n type impurity that can provide the n type conductivity, such as N (nitrogen). Second region 42 has a p type conductivity (second conductivity type). Second region 42 includes a p type impurity that can provide the p type conductivity, such as Al (aluminum).
Each of first direction 101 and second direction 102 is parallel to first main surface 1. First direction 101 is a direction perpendicular to second direction 102. First direction 101 is, for example, a <11-20> direction. Second direction 102 is, for example, a <1-100> direction. First direction 101 may be, for example, a direction obtained by projecting the <11-20> direction onto first main surface 1. Second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto first main surface 1.
As shown in
First region 41 has a first portion 71 and a second portion 72. Second portion 72 is located between first portion 71 and first main surface 1. First portion 71 and second portion 72 are adjacent to each other in third direction 103. Second portion 72 may be in contact with buffer layer 12 or may be in contact with first main surface 1.
Second region 42 has a third portion 73 and a fourth portion 74. Fourth portion 74 is located between third portion 73 and first main surface 1. Third portion 73 and fourth portion 74 are adjacent to each other in third direction 103. Fourth portion 74 may be in contact with buffer layer 12 or may be in contact with first main surface 1.
Third portion 73 is in contact with first portion 71 Third portion 73 and first portion 71 are adjacent to each other in first direction 101. Third portions 73 and first portions 71 are alternately arranged in first direction 101. Fourth portion 74 is in contact with second portion 72. Fourth portion 74 and second portion 72 are adjacent to each other in first direction 101. Fourth portions 74 and second portions 72 are alternately arranged in first direction 101.
As shown in
As shown in
As shown in
As shown in
As shown in
A total of the height (first height T1) of first portion 71 and the height (second height T2) of second portion 72 is a height (third height T3) of first region 41. Similarly, a total of the height (first height T1) of third portion 73 and the height (second height T2) of fourth portion 74 is a height (third height T3) of second region 42.
The height (third height T3) of each of first region 41 and second region 42 is 2 µm or more. The lower limit of the height of each of first region 41 and second region 42 is not particularly limited, but may be, for example, 2.5 µm or more, or 3 µm or more. The upper limit of the height of each of first region 41 and second region 42 is not particularly limited, but may be, for example, 5 µm or less or 4 µm or less.
An impurity concentration in third portion 73 may be higher than an impurity concentration in fourth portion 74. An impurity concentration in first portion 71 is substantially the same as an impurity concentration in second portion 72. The impurity concentration in first portion 71 is substantially the same as the impurity concentration in third portion 73 The impurity concentration in fourth portion 74 may be lower than the impurity concentration in second portion 72.
The impurity concentration of each of first portion 71 and third portion 73 may be, for example, 3×1016 cm-3 or more and 5×1017 cm-3 or less. The lower limit of the impurity concentration of each of first portion 71 and third portion 73 is not particularly limited, but may be, for example, 4×1016 cm-3 or more, or 5×1016 cm-3 or more. The upper limit of the impurity concentration of each of first portion 71 and third portion 73 is not particularly limited, but may be, for example, 3×1017 cm-3 or less, or 2×1017 cm-3 or less.
Element layer 40 is provided above super junction layer 10. Element layer 40 is, for example, a switching element. Element layer 40 has, for example, a first impurity region 15, a second impurity region 23, a third impurity region 30, a fourth impurity region 24, and a fifth impurity region 20. First impurity region 15 is, for example, a drift region.
First impurity region 15 has the n type conductivity (first conductivity type). First impurity region 15 includes an n type impurity that can provide the n type conductivity, such as N (nitrogen). First impurity region 15 is in contact with first region 41. First impurity region 15 has a first drift layer 14 and a second drift layer 13. First drift layer 14 is in contact with gate insulating film 6. Second drift layer 13 is contiguous to first drift layer 14. Second drift layer 13 is located between first drift layer 14 and first region 41. The width of second drift layer 13 at its center is smaller than each of the widths of the upper and lower portions of second drift layer 13.
Second impurity region 23 is, for example, a body region. Second impurity region 23 is in contact with first impurity region 15. Second impurity region 23 has the p type conductivity (second conductivity type). Second impurity region 23 includes a p type impurity that can provide the p type conductivity, such as Al (aluminum). Second impurity region 23 is electrically connected to second region 42. The concentration of the p type impurity in second impurity region 23 may be higher than the concentration of the n type impurity in first impurity region 15.
Third impurity region 30 is, for example, a source region . Third impurity region 30 is separated from first impurity region 15 by second impurity region 23. Third impurity region 30 has the n type conductivity (first conductivity type). Third impurity region 30 includes an n type impurity that can provide the n type conductivity, such as P (phosphorus). The concentration of the n type impurity in third impurity region 30 may be higher than the concentration of the p type impurity in second impurity region 23.
Fourth impurity region 24 is, for example, a contact region. Fourth impurity region 24 is in contact with second impurity region 23 and third impurity region 30. Fourth impurity region 24 has the p type conductivity (second conductivity type). Fourth impurity region 24 includes a p type impurity that can provide the p type conductivity, such as Al (aluminum). The concentration of the p type impurity in fourth impurity region 24 may be higher than the concentration of the p type impurity in second impurity region 23.
Fifth impurity region 20 connects second impurity region 23 and second region 42 to each other. Fifth impurity region 20 is in contact with each of first impurity region 15, second impurity region 23, and second region 42. Fifth impurity region 20 has the p type conductivity (second conductivity type). Fifth impurity region 20 includes a p type impurity that can provide the p type conductivity, such as Al (aluminum).
Fifth impurity region 20 has a first connection region 21 and a second connection region 22. First connection region 21 is in contact with each of second impurity region 23 and first drift layer 14. Second connection region 22 is in contact with each of first connection region 21 and second region 42. Second connection region 22 is located between first connection region 21 and second region 42 in third direction 103.
Gate insulating film 6 is provided on element layer 40. Gate insulating film 6 is composed of silicon dioxide, for example. Gate insulating film 6 is in contact with, for example, each of first impurity region 15, second impurity region 23, and third impurity region 30. A channel can be formed in second impurity region 23 that is in contact with gate insulating film 6.
Gate electrode 52 is provided on gate insulating film 6. Gate electrode 52 is in contact with gate insulating film 6. Gate electrode 52 is composed of a conductor such as polysilicon doped with an impurity, for example.
Trench 5 is provided in element layer 40. Trench 5 is defined by a side surface 8 and a bottom portion 9. Side surface 8 is constituted of each of first impurity region 15, second impurity region 23, and third impurity region 30. Bottom portion 9 is contiguous to side surface 8. Bottom portion 9 is constituted of first impurity region 15
At least a portion of gate insulating film 6 is provided inside trench 5, for example. Gate insulating film 6 is in contact with each of first impurity region 15, second impurity region 23, and third impurity region 30 at side surface 8. Gate insulating film 6 is in contact with the first impurity region at bottom portion 9. At least a portion of the gate electrode is provided inside trench 5, for example.
Second electrode 62 is, for example, a source electrode. Second electrode 62 is provided on element layer 40. Second electrode 62 is in contact with third impurity region 30 and fourth impurity region 24. Second electrode 62 may cover a separation insulating film 64. First electrode 61 is, for example, a drain electrode. First electrode 61 is provided on second main surface 2 of substrate 11.
Separation insulating film 64 is provided to cover gate electrode 52. Separation insulating film 64 is in contact with each of gate electrode 52 and gate insulating film 6. Separation insulating film 64 is constituted of, for example, a NSG (None-doped Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, or the like. Separation insulating film 64 electrically insulates gate electrode 52 and second electrode 62 from each other
Next, a method of forming super junction layer 10 will be described.
First, buffer layer 12 is formed on substrate 11. Buffer layer 12 is formed by epitaxial growth, for example. Next, first region 41 is formed on buffer layer 12. First region 41 is formed by, for example, epitaxial growth. Each of buffer layer 12 and first region 41 has the n type conductivity (first conductivity type). Next, a mask layer (not shown) is formed on first region 41.
Next, a channeling ion implantation step is performed. Specifically, in the state in which the mask layer is disposed on first region 41, impurity ions that can provide the p type conductivity (second conductivity type) such as aluminum are implanted into first region 41. An implantation energy is, for example, 960 keV. An implantation temperature is, for example, a room temperature. Thus, second regions 42 are formed in portions of first region 41. Second regions 42 are provided to be separated from each other in first direction 101. Thus, super junction layer 10 in which first regions 41 and second regions 42 are alternately arranged is formed (see
In the channeling ion implantation step, the impurity ions are implanted in a direction substantially parallel to the <0001> direction, which corresponds to a crystal axis of silicon carbide. The impurity ion implantation direction may be inclined by an angle of 0.5° or less with respect to the <0001> direction, for example. Specifically, the impurity ion implantation direction may be a direction obtained by inclining third direction 103 in an off direction. The off direction may be, for example, first direction 101 or second direction 102. Thus, scattering of the impurity ions and the silicon carbide can be reduced, with the result that the impurity ions can be implanted deeply. As a result, second region 42 having a thickness of 2 µm or more is formed (see
As shown in conditions B and C in
Table 1 shows a width of extension of the impurity region in the lateral direction and a width of extension of the impurity region in the depth direction. As shown in Table 1, in each of conditions A and B, the width of extension of the impurity region in the lateral direction is substantially the same as the width of extension of the impurity region in the depth direction. In comparison between conditions B and C, it is understood that when the implantation energy is the same, the width of extension of the impurity region in the lateral direction in the case of the random implantation is substantially the same as the width of extension of the impurity region in the lateral direction in the case of the channeling implantation.
When the implantation energy is made high, the width of extension of the impurity region in the lateral direction becomes large. The width of extension of the impurity region in the lateral direction as formed by the box profile of condition A depends on the extension when the implantation energy is the highest. In comparison between conditions A and C, it is understood that when the implantation depths are substantially the same, the width of extension of the impurity region in the lateral direction in the case of the random implantation is larger than the width of extension of the impurity region in the lateral direction in the case of the channeling implantation.
In view of the above discussion, by using the channeling implantation, an impurity region (super junction layer 10) can be formed to have a large width of extension in the depth direction and a small width of extension in the lateral direction. It should be noted that in Table 1, the implanted impurity ions are aluminum ions. A target of the implantation is silicon carbide The values shown in Table 1 are varied by about ±20% depending on the implanted impurity ions and the target of the implantation.
Next, a configuration of a silicon carbide semiconductor device 100 according to a second embodiment will be described. The configuration of silicon carbide semiconductor device 100 according to the second embodiment is different from the configuration of silicon carbide semiconductor device 100 according to the first embodiment mainly in that first regions 41 are stacked together and second regions 42 are stacked together in super junction layer 10, and is the same as the configuration of silicon carbide semiconductor device 100 according to the first embodiment in terms of the other points. The following mainly describes the configuration different from the configuration of silicon carbide semiconductor device 100 according to the first embodiment.
Each of the lower limit of the number of stacked first regions 41 and the lower limit of the number of stacked second regions 42 is not particularly limited, but may be, for example, 2 or more or 3 or more. Each of the upper limit of the number of stacked first regions 41 and the upper limit of the number of stacked second regions 42 is not particularly limited, but may be, for example, 10 or less or 6 or less.
Stacked first regions 41 and stacked second regions 42 can be formed by alternately repeating the epitaxial growth step and the channeling ion implantation step. For example, a first region 41 in a lower layer is formed in a first epitaxial growth step. A first region 41 in an upper layer is formed in a second epitaxial growth step. Strictly speaking, a growth condition in the first epitaxial growth step is different from a growth condition in the second epitaxial growth step. Therefore, the impurity concentration of first region 41 in the lower layer may be different from the impurity concentration of first region 41 in the upper layer. From another viewpoint, it can be said that when the impurity concentration profile of first region 41 in the upper layer and the impurity concentration profile of first region 41 in the lower layer are measured by SIMS (Secondary Ion Mass Spectrometry) along third direction 103, an impurity concentration profile of first region 41 in the upper layer may be discontinuous from an impurity concentration profile of first region 41 in the lower layer.
The height of each of first region 41 and second region 42 in one layer is, for example, 2 µm or more and 4 µm or less. By stacking first regions 41 together and stacking second regions 42 together, each of the total thickness of first regions 41 and the total thickness of second regions 42 can be large. The lower limit of each of the total thickness of first regions 41 and the total thickness of second regions 42 is not particularly limited, but may be, for example, 4 µm or more or 6 µm or more. The upper limit of each of the total thickness of first regions 41 and the total thickness of second regions 42 is not particularly limited, but may be, for example, 30 µm or less or 20 µm or less.
Next, a configuration of a silicon carbide semiconductor device 100 according to a third embodiment will be described. The configuration of silicon carbide semiconductor device 100 according to the third embodiment is mainly different from the configuration of silicon carbide semiconductor device 100 according to each of the first and second embodiments in that silicon carbide semiconductor device 100 is a planar type MOSFET, and is the same as the configuration of silicon carbide semiconductor device 100 according to each of the first and second embodiments in terms of the other points. The following mainly describes the configuration different from the configuration of silicon carbide semiconductor device 100 according to each of the first and second embodiments.
As shown in
Next, a configuration of a silicon carbide semiconductor device 100 according to a fourth embodiment will be described. The configuration of silicon carbide semiconductor device 100 according to the fifth embodiment is mainly different from the configuration of silicon carbide semiconductor device 100 according to each of the first and second embodiments in that silicon carbide semiconductor device 100 is a PN diode, and is the same as the configuration of silicon carbide semiconductor device 100 according to each of the first and second embodiments in terms of the other points. The following mainly describes the configuration different from the configuration of silicon carbide semiconductor device 100 according to each of the first and second embodiments.
It should be noted that although the fourth embodiment shows the example of the PN diode, it can be modified to a Schottky diode. That is, in
Next, the following describes a method of measuring the concentration of the p type impurity and the concentration of the n type impurity in the respective impurity regions.
Each of the concentration of the p type impurity and the concentration of the n type impurity in the respective impurity regions can be measured using SIMS. A measuring device is, for example, a secondary ion mass spectrometer provided by Cameca. A measurement pitch is, for example, 0.01 µm. When the n type impurity to be detected is nitrogen, a primary ion beam is cesium (Cs). A primary ion energy is 14.5 keV. A secondary ion polarity is negative. When the p type impurity to be detected is aluminum or boron, the primary ion beam is oxygen (O2). The primary ion energy is 8 keV. The secondary ion polarity is positive.
Next, the following describes a method of distinguishing the p type region and the n type region from each other
In the method of distinguishing the p type region and the n type region from each other, SCM (Scanning Capacitance Microscope) is used. A measuring device is, for example, NanoScope IV provided by Bruker AXS. The SCM is a method of visualizing a carrier concentration distribution in a semiconductor. Specifically, a metal-coated silicon probe is used to scan a surface of a sample. On this occasion, a high-frequency voltage is applied to the sample. Majority carriers are excited, thereby applying modulation to a capacitance of the system. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V.
Although it has been illustrated that the first conductivity type is the n type conductivity and the second conductivity type is the p type conductivity in the above description, the first conductivity type may be the p type conductivity and the second conductivity type may be the n type conductivity. The impurity concentration of the impurity region having the n type conductivity is the concentration of the n type impurity. The impurity concentration of the impurity region having the p type conductivity is the concentration of the p type impurity.
Next, functions and effects of silicon carbide semiconductor device 100 according to each of the embodiments will be described.
In the super junction structure, as the impurity concentration of each of first region 41 and second region 42 is higher and the pitch (the total of the width of first region 41 and the width of second region 42) is smaller, on-resistance can be reduced more. Further, as the thickness of each of first region 41 and second region 42 is larger, breakdown voltage is higher. Therefore, in order to reduce the on-resistance and attain high breakdown voltage, it is desirable that each of the thicknesses of first region 41 and second region 42 is large and the pitch (the total of the width of first region 41 and the width of second region 42) is small.
Normally, when impurity ions are implanted into the silicon carbide layer with high acceleration energy, scattering becomes large in the silicon carbide layer. Therefore, the width of the implantation region becomes larger than the opening width of the mask pattern. As a result, it is difficult to form a super junction structure having a large thickness and a small pitch. Further, the thickness of the mask pattern needs to be large in order to implant impurity ions deeply. However, as the thickness of the mask pattern is larger, stress becomes large, thus resulting in occurrence of a problem such as large warpage of a wafer.
On the other hand, an implantation depth that can be attained with a low acceleration energy of about 1 MeV or less is about 1 µm. For example, in order to obtain super junction layer 10 having a breakdown voltage of about 1.2 kV, it is necessary to repeat the epitaxial growth and the ion implantation about five or six times.
Super junction layer 10 of silicon carbide semiconductor device 100 according to the present embodiment is formed by using the channeling implantation technique. Therefore, super junction layer 10 having a large thickness and a small pitch can be formed with a low acceleration energy of about 1 MeV or less. Specifically, the total value of the width of first portion 71 and the width of third portion 73 is 0.5 µm or more and 4 µm or less, and the height of each of first region 41 and second region 42 is 2 µm or more. Thus, the breakdown voltage can be improved while reducing the on-resistance.
Further, according to silicon carbide semiconductor device 100 of the present embodiment, the number of times of performing each of the epitaxial growth and the ion implantation can be reduced. Therefore, a polycrystalline silicon carbide particle can be suppressed from being sandwiched between the epitaxial layers. This results in improved yield of silicon carbide semiconductor device 100.
Further, when the p type regions are formed by repeating the epitaxial growth and the ion implantation, a portion of a p type region formed in a lower epitaxial layer needs to be overlapped with a portion of a p type region formed in an upper epitaxial layer so as to connect the upper and lower p type regions to each other. The impurity concentration of each of the overlapping portions of the p type regions is higher than the impurity concentration of each of the non-overlapping portions of the p type regions. By reducing the number of times of performing each of the epitaxial growth and the ion implantation, the number of the overlapping portions of the p type regions can be reduced. Therefore, a charge balance in super junction layer 10 can be suppressed from being lost.
The embodiments disclosed herein are illustrative and non-restrictive in any respect. The scope of the present invention is defined by the terms of the claims, rather than the embodiments described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
1: first main surface; 2: second main surface; 5: trench; 6: gate insulating film; 8: side surface; 9: bottom portion; 10: super junction layer, 11: substrate; 12: buffer layer; 13: second drift layer, 14: first drift layer; 15: first impurity region; 20: fifth impurity region; 21: first connection region; 22: second connection region; 23: second impurity region; 24: fourth impurity region; 30: third impurity region; 40: element layer; 41: first region; 42: second region; 52: gate electrode; 61: first electrode; 62: second electrode; 63: third electrode; 64: separation insulating film; 71: first portion; 72: second portion; 73: third portion; 74: fourth portion; 100: silicon carbide semiconductor device; 101: first direction; 102: second direction; 103: third direction; P: pitch; T1: first height; T2: second height; T3: third height; W1: first width; W2: second width; W3: third width; W4: fourth width.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-118899 | Jul 2020 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/019996 | 5/26/2021 | WO |
