Patent Application
20220059977
This disclosure relates to a smart connector, and the method of manufacturing thereof. More specifically, this disclosure relates to a smart connector and the method of manufacturing thereof, which partially uses an Application Specific Electronics Packaging (“ASEP”) manufacturing process to form the smart connector.
Application Specific Electronic Packaging (“ASEP”) devices and manufacturing process have been developed by the Applicant and are useful for the creation of electronics modules that integrate the function of printed circuit boards, heat sinks, connectors, high current conductors, and thermal management features into a single electronics module. An advantage of the ASEP manufacturing process is that it allows a manufacturer to integrate connector functions into the electronics module that would be much larger and more expensive if the connector functions were discrete components. Furthermore, metal contacts integrated into ASEP devices are highly conductive so the metal contacts provide an optimal path for carrying high current, as well as removing heat very efficiently.
The ASEP manufacturing process utilizes many of the same manufacturing steps used to produce connectors, but adds significantly more functionality with minimal addition of cost. ASEP manufacturing processes have previously been described and illustrated in International Application No. PCT/US2016/039860, filed on Jun. 28, 2016 and published as International Publication No. WO 2017/004064 on Jan. 5, 2017, and in International Application No. PCT/US201.7/040736, filed on Jul. 5, 2017 and published as international Publication No. WO 2018/009554 on Jan. 11. 2018, the disclosures of which are incorporated herein by reference.
One of the industries that ASEP devices and ASEP manufacturing processes has been found to be able to provide significant value for is that of power electronics. Due to the increasing demand for electrification and higher power levels in a variety of industries, the need for better ways to produce high power electronics is exponentially growing.
Today, power electronics are still assembled onto “thick Cu PCBs” that may have 3 to 5-ounce Cu traces (110 to 185 microns thick). But not only, are these types of PCBs expensive, they are not actually very good at carrying the very high currents (100 to 500 Amps) that are required by the industry. Techniques such as using heat pipes are being considered m order to help remove the heat being, generated, but these approaches are often bulky and expensive to implement.
ASEP manufacturing; processes for forming power electronics enable designers with an approach to dramatically reduce the electrical resistance in the system, thereby reducing the amount of heat generated. Furthermore, by directly attaching the power devices that generate some of the heat to a highly thermally conductive metal, ASEP devices enable the removal of the heat that is still generated in a much more efficient way.
While ASEP manufacturing devices and processes provide some significant advantage in the design and manufacture of power electronics where currents of several hundred amps would be possible, one of the challenges associated with changing the features and or performance requirements of an ASEP device is that different applications may require entirely new stamping dies and or molds. This could result in difficulty justifying the cost associated with the new stamping dies and or molds and the time associated with manufacturing and qualifying the stamping dies and or molds.
Thus, there is a need for an improved ASEP device and an improved process of manufacturing same.
In an embodiment, a smart connector includes an Application Specific Electronics Packaging CASEP) device formed by an ASEP manufacturing process, and a separate printed circuit board electrically connected to electrical components of the ASEP device. The ASEP manufacturing process includes forming a continuous carrier web having a plurality of lead frames, overmolding a substrate onto the fingers of each lead frame, each substrate having a plurality of openings which exposes a portion of the fingers, electroplating the traces, and electrically attaching at least one electrical component to the traces to form a plurality of ASEP devices. In some embodiments, the printed circuit board has electrical components configured to control the functionality of the electrical components. in some embodiments, the printed circuit board has electrical components configured to modify properties of the smart connector.
In an embodiment, a method of forming a smart connector includes: forming a continuous carrier web having, a plurality of lead frames, each lead frame defining an opening and having a plurality of lingers which extend into the opening; overmolding a substrate onto the fingers of each lead frame, each substrate having a plurality of openings provided therethrough which exposes a portion of the lingers to form exposed. portions; electrically connecting an electrical component to the exposed portion of some of the fingers of each lead frame to form a plurality of devices, each device having at least one electrical component; and electrically attaching a printed circuit board to the exposed portion of some of the lingers of one of the devices, the printed circuit board having electrical components configured to control the functionality of the at least one electrical component of the one device.
The present application is illustrated by way of example and not limited in the accompanying figures in which like reference numerals indicate similar elements and in which:
The detailed description that follows describes exemplary embodiments and the features disclosed are not intended to be limited to the expressly disclosed combination(s). Therefore, unless otherwise noted, features disclosed herein may be combined together to form additional combinations that were not otherwise shown for purposes of brevity. The terms “forward” and “rearward” are used for description purposes only and do not denote a required orientation during use.
The present disclosure is directed to improvements in the design and manufacture of a smart connector 360 which is partially formed using an Application Specific Electronics Packaging (“ASEP”) manufacturing process 320. In some embodiments, the smart connector 360 includes an Application Specific Electronics Packaging (“ASEP”) device 310 which is formed using the ASEP manufacturing process 320 and a separate printed circuit board 200 which is attached to the ASEP device 310 to control the operation of the ASEP device 310 in different manners. In some embodiments, the smart connector 360 includes an Application Specific Electronics Packaging (“ASEP”) device 310 which is formed using the ASEP manufacturing, process 320 and a separate printed circuit board 200 which is attached to the ASEP device 310 to modify properties of the resulting smart connector 360 in different manners. In an embodiment, the ASEP device 310 and the printed circuit board 200 are assembled/connected into a housing 375 to form the, smart connector 360. In some embodiments, multiple ASEP deices 310 arc connected to the printed circuit board 200 and the printed circuit board 200 interacts with all of the ASEP devices 310, as shown schematically in
The ASEP device 310 includes base electrical components 386 which are commonly used in a variety of applications to meet customer's needs. The base electrical components 386 may include, but are not limited to, microprocessor unit (MPU)/micro controller unit (MCU), field-programmable gate array (FPGA), field-effect transistor (FET) which may have an associated gate driver, insulated-gate bipolar transistor (IGBT), motor driver, electronic components for implementing communication frontend (such as a RJ45 connector), sensors (such as current sensors), diodes, capacitors, and resistors. The current sensor may be used to monitor the FET. ASEP manufacturing processes 320 provides several significant advantages for the design and manufacture of high-power electronics—an industry that will be growing exponentially over the next decade due to the electrification of the transportation and other industries. Because of the benefits provided by the ASEP device 310 manufactured by the ASEP manufacturing process 320. the FET may be a 40-amp or more field effect transistor.
The separate printed circuit board 200 includes electrical components 202 which characteristics/parameters can be varied and which interact with the base electrical components 386 on the ASEP device 310. The electrical components 202 on the separate printed circuit board 200 may include, but are not limited to, microprocessor unit (MPU)/micro controller unit (MCU)/central processing unit (CPU), electronic components for implementing communication protocols, memory, field-programmable gate array (FPGA). Examples of communication protocols include Controller Area Network (CAN), Local Interconnect Network (LIN), FlexRay, ControlNet, DirectNet, Modbus, Profibus, any two wire or radio frequency (RF) communication protocol. Previously, these electrical components 202 which are provided on the separate printed circuit board 200 were integrated in the ASEP device.
With the present disclosure, since certain features previously provided on prior art ASEP devices are now provided on the separate printed circuit board 200, and not on the ASEP device 310, many of the electronics and components for the smart connector 360 can be easily changed or upgraded by replacing the separate printed circuit board 200 by the manufacturer without having to retool for manufacturing the more costly ASEP device 310. This allows the same ASEP device 310 to be used with multiple printed circuit boards 200, thereby allowing the manufacturer to cost effectively accommodate the same customer's requirements or multiple customers' requirements using the same base ASEP device 310 and only changing the printed circuit board 200. The printed circuit board 200 is not optimal for use in routing high current and does not have good thermal management properties, however, the printed circuit board 200 provides the smart connector 360 with the advantages of high-density circuitry, multi-layering, and can be very quickly and cost effectively manufactured. As a result, the capital required to produce the base ASEP device 310 can be left unchanged and minimal capital is only required to manufacture new printed circuit boards 200 for use with the same ASEP device 310. This also solves the thermal challenges associated with applications because the ASEP device 310 solves thermal challenges (which the printed circuit board 200 does not), while allowing for the application to be customized for each customer by changing the printed circuit board 200, thereby dramatically reducing the required capital to tool and manufacture high power applications.
Some examples of applications using these electrical components 202, 386 include the following. 1) A solid-state switch in which the printed circuit board 200 is a master. In the solid-state switch application, the printed circuit board 200 includes the MCU and the communication protocols (for example CAN, LIN), and the ASEP device 310 includes the FET. 2) A compute module in which the printed circuit board 200 is a slave. In the compute module application, the printed circuit board 200 includes memory, and the ASEP device 310 includes the CPU. 3) A communication module in which the printed circuit board 200 is a master. In the communication module application, printed circuit board 200 includes the MCU and the communication protocol, and the ASEP device 310 includes the communication frontend (RJ45 connector). 4) A motor module in which the printed circuit board 200 is a master. In the motor module application, printed circuit board 200 includes the MCU and the communication protocol, and the ASEP device 310 includes the motor driver.
As an example of how the printed circuit board 200 controls the operation of the ASEP device 310, if the printed circuit board 200 includes the MCU and the communication protocol, and the ASEP device 310 includes the FET, the MCU on the printed circuit board 200 instructs the FET on the ASEP device 310 to turn on or off, as required. As an example, depending upon communication protocol provided on the printed circuit board 200, the operation of the ASEP device 310 is controlled differently while using the same FET on the ASEP device 310.
As an example of how the printed circuit board 200 modifies the properties of the resulting smart connector 360, if the printed circuit board 200 includes memory, and the ASEP device 310 includes the CPU, depending upon the code stored in the memory is provided on the printed circuit board 200 alters the properties of the resulting smart connector 360.
The smart connector 360 is partially formed using the ASEP manufacturing process 320 as is known in the prior art, but the ASEP manufacturing process 320 has been modified to form the smart connector 360 by accommodating electrical connection to the, printed. circuit board 200. Attention is directed to
As illustrated in
As illustrated in
End portions of the contact pins 342 do not have the substrate 338 overmolded thereto. The overmolding of Step B can be performed with single or two shot processes, or any other conventional molding process.
The ASEP manufacturing process 320 continues with Step C. in Step C, patterning is performed on the substrate 338. The patterning provides for one or more patterns 344 (which may be circuit patterns) to he formed on the surface(s) of the substrate 338. The patterns 344 can be formed by any number of suitable processes, including a laser process, a plasma process (Which can be a vacuum or atmospheric process), a UV process and/or a fluorination process. Depending on the process used (e.g., plasma, UV and/or fluorination), the patterning may comprise patterning (i.e., a surface treatment of) most, if not all, of the surface of the substrate 338. Thus, the patterns 344 may be formed on all or nearly all of the surface of the substrate 338.
The ASEP manufacturing process 320 continues with Step D. hi Step D, a metal layer (commonly referred to as a seed layer) is deposited on all or part of the patterns 344 (typically all when the patterns 344 are formed by a laser process, and typically a part of when the patterns 344 are formed by plasma, U V and/or fluorination processes) and connected to the substrate 338, which metal layer provides a conductive pattern or traces 346. The traces 346 also are provided along the walls of the openings 340, thus electrically connecting the traces 346 to the fingers 334, and thus to the :remainder of the lead frame 328 as well. The deposition. of the metal layer may he performed by any suitable process, including an electroless plating process, an ink jet process, a screening process, or an aerosol process. Depending on the process used, the metal to be deposited may be in any suitable form, including ink or paste. The metal to be deposited preferably has high conductivity and low binder content so as to increase its conductivity. The metal to be deposited further preferably has high chemical stability in plating baths and a viscosity that is compatible with the desired deposition process. While not illustrated, it is to be understood that portions of the fingers 334 can act as internal buss(es) which are electrically connected to the traces 346 on the surface of the substrate 338.
The ASEP manufacturing process 320 continues with Step E. In Step E, the traces 346 are made conductive (sintered), thereby forming conductive traces 348. The sintering process can be performed by a laser or by flash heat, or any other desirable process that provides sufficient thermal energy, for instance to fuse the particles (e.g., nano or micron in size) in an ink or paste. Sintering helps ensure that the deposited metal forming the traces 346 adheres to the substrate 338 and also ensures that the deposited metal is conductive (as it often is the case that the deposited metal as applied is not sufficiently conductive to allow for a voltage potential to be applied to the traces 346). As can be appreciated, if Step D is performed with an electroless plating process, then Step E does not need to be performed, as there is no need to sinter the electroless plating.
It should further be noted that, if both. Step C and Step E are performed using lasers, that a preferred process would have multiple lasers integrated into a single station/position, thereby saving space in the ASEP manufacturing process 320 and helping to ensure that laser is properly registered. In addition, the integration of multiple lasers in a single station/position enables faster processing of the material.
As illustrated in
The connection of the traces 346 to the internal buss(es) enables electroplating of all metals, including copper, nickel, gold, silver, tin, lead, palladium, and other materials. The process of forming traces 346 which are connected to the internal bass(es) and then electroplating enables faster deposition of metals than known electroless plating processes. In addition, the plating process is smoother and lower cost when implemented using reel-to reel technology as compared with more conventional batch processes.
In another embodiment, techniques such as those included in Mesoscribe technology may be used to deposit a full thickness of copper (or other conductive material) on a surface. A picosecond laser may then be used to isolate desired conductive patterns in the conductive material. Such an approach could he used in place of Step F, as described herein, or in addition to Step F, where one or more plated materials are desired.
Steps C, D, E, and F may be used on a Syndiotactic Polystyrene (SPS) provided by XAREC and provide good retention of the electronic circuit traces 350 to the surface of the substrate 338.
The ASEP manufacturing process 320 continues with Steps G and H after Step F, but
As illustrated in
The ASEP manufacturing process 320 continues with Step J, but
As illustrated in
It is to be appreciated that in certain applications not all of Steps A-K will be needed. It is to be further appreciated that in certain applications the order of Steps A-K may be modified as appropriate. It should also be appreciated that while the drawings only show the ASEP manufacturing process 320 being applied to the substrate 338, that the ASEP manufacturing process 320 may be equally applied to internal layers.
In an embodiment, the printed circuit board 200 is conventionally formed and includes an insulating substrate 204 having circuits 206 formed thereon by a thin layer of conducting material deposited, or “printed” on the surface of the substrate 204. Individual electronic components 202 are placed on the surface of the substrate 204 and are soldered to the circuits 206. In an embodiment, the printed circuit board 200 has a plurality of contact pins 208 extending from the substrate which provide connectors to the ASEP device(s) 310. Some of the contact pins 208 are labeled shown in
Prior to, or after, the ASFP device 310 is singulated, the printed circuit board 200 is mated with the ASEP device(s) 310. The contact pins 208 are electrically connected to the high current contacts 341 and the contact pins 342 as necessary to complete the mating of the printed circuit board 200 with the ASEP device(s) 310. In some embodiments, the contact pins 208 extend through the openings 343 and through the apertures 336 for connection to the high current contacts 341 and the contact pins 342 in a press-Ft manner. In some embodiments, the contact pins 208 are surface mounted to the high current contacts 341 and the contact pins 342 via the openings 343, for example by soldering. Thereafter, the mated printed circuit board 200 and ASEP device(s) 310 are assembled/connected into the housing 375 to form the smart connector 360. In an embodiment, multiple housings may be provided with the primed circuit board 200 in one housing, and each ASEP device 310 in its own housing. In an embodiment, multiple housings may be provided with the printed circuit board 200 and one or more of the ASEP devices 310 in one housing, and other ASEP devices 310 in their own housings.
The substrate 338 has a forward edge 390, a rearward edge 392, and first and second side edges 394, 396. The housing 375 may include a first inner portion (not shown) into which the mated printed circuit board 200 and ASEP device(s) 310 is inserted and housed. The side edges 394, 396 of the ASEP device 310 may be inserted into track portions (not shown) defined by the housing 375 until the forward edge 390 of the ASEP device(s) 310 abuts against an internal wail (not shown) of the housing 375. The internal wall separates the housing 375 into a first inner portion (not shown) and a second inner portion 398 and has a plurality- of apertures (not shown) extending therethrough which allow the electroplated high current contacts 357 and the electroplated. contact pins 358 to extend into the second inner portion 398. A cover 400 can be secured to the housing 375 via known means to dose of the first inner portion and, in essence, encapsulate the A SEP device(s) 310/printed circuit hoard. 200 therein. The cover 400, as well as the internal wall, may be configured to have track portions to receive the side edges 394, 396 of the ASEP device(s) 310 to stabilize the ASEP device(s) 310/printed circuit board 200 M position within the housing 375. A gasket 402 may be provided between the cover 400 and the housing 375 to seal off the ASEP device(s) 310/printed circuit board 200 from outside elements.
With the smart connector 360 formed, it can be connected to a mating connector 500, see
This forms a small and light weight smart connector 360.
The printed circuit board 200 may be directly mated to the side of the substrate 338 which does not have the electrical components 386 thereon. The side of the substrate 338 which does not have the electrical components 386 thereon may be planar and ideally suited for connection to the printed circuit board 200. The printed circuit board 200 may have outer edges which define a perimeter which is smaller than the perimeter defined by edges 390, 392, 394, 396 of the substrate 338, such that the printed circuit board 200 does not extend beyond edges 390, 392, 394, 396. This provides a compact assembly. Other orientations are possible. For example, the printed circuit board 200 may he mounted on the same surface as the electrical components 386 and extend outwardly from one or more of the edges 390, 392, 394, 396, or for example, the printed circuit hoard 200 may he above the electrical components 386 and electrically connected to the ASEP device(s) 310.
The ASEP device 310 and mated printed circuit board 200 can be used to form a smart battery switch which can be either used to carry 400 Amps or provide a secondary redundant protection due to primary switch malfunction. The ASEP device 310 and mated printed circuit board 200 can be used to form a smart battery switch that is capable of switching 200 Amps. Each battery switch may have reverse-battery protection.
All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
The use of the terms “a” and “an” and “the” and “at least one” and similar referents in the context of describing the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” followed by a list of one or more items (for example, “at least one of A and B”) is to be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.
Preferred embodiments of this invention are described herein, including the best mode known to the inventors for carrying out the invention. Variations of those preferred embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the invention to be practiced otherwise than as specifically described herein. Accordingly, this invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the invention unless otherwise indicated herein or otherwise clearly contradicted by context. As can be appreciated from the various embodiments depicted herein, different features of different embodiments depicted herein can be combined together to form additional combinations. As a result, the embodiments depicted herein are particularly suitable to provide a wide range of configurations that were not all depicted individually so as to avoid repetitiveness and unnecessary duplication.
The disclosure provided herein describes features in terms of preferred and exemplary embodiments thereof. Numerous other embodiments, modifications and variations within the scope and spirit of the appended claims will occur to persons of ordinary skill in the art from a review of this disclosure.
This application claims priority to U.S. Provisional Application No. 62/795,299, filed Jan. 22, 2019, the contents of which are incorporated herein in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2020/014494 | 1/22/2020 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62795299 | Jan 2019 | US |
