The present application claims priority to Singapore Patent Application No. 10201706699P, titled “Spin Orbit Materials for Efficient Spin Current Generation,” filed by Applicant National University of Singapore on Aug. 16, 2017, the contents of which are incorporated by reference herein in their entirety.
The present disclosure relates generally to spin torque devices and more specifically to a spin-orbit torque (SOT) based magnetic devices (“SOT devices”) and materials that may enable efficient spin current generation therein.
Spin torque devices, such as spin torque magnetic random access memory (MRAMs), magnetic logic devices, racetrack memories, etc., manipulate magnetization directions to store information or for other purposes. Magnetization direction may be manipulated using current-induced STT. STT techniques have advanced over a number of years, and STT MRAMs is becoming commercially available. Magnetization manipulation may also be achieved via current-induced SOT. A typical SOT device is structured as a device stack having a number of layers all arranged substantially parallel to a plane. For instance, a SOT device stack may include a magnetic layer (e.g., a ferromagnet (FM) layer) adjacent a non-magnetic layer (NM) layer. When an in-plane input current is applied to the SOT device, a spin current from the NM layer diffuses into the magnetic layer (e.g. FM layer) and influences the magnetization direction. While not yet at the point of commercial viability, SOT MRAM may represent the future of MRAM.
A basic requirement for manipulating the magnetization direction of a magnetic layer, such as a FM layer, is efficiently generating the spin current. In one technique, spin orbit coupling (SOC) effects in the NM are utilized to generate the spin currents electrically. One such effect is the spin Hall effect (SHE), which exploits SOC in the bulk of a NM, resulting in asymmetric scattering of opposite spins, and thus converting an unpolarized charge current into a pure spin current and vice-versa.
Since the origins of the SHE lie in SOC, and the strength of SOC is larger for heavier elements, heavy metals (HMs) such as platinum (Pt), tantalum (Ta), hafnium (Hf) and tungsten (W) typically have been utilized as the NM layer of the device stack in SOT devices. As such, the NM layer has often been referred to as a HM layer. The SHE in HMs arises from an intrinsic SHE mechanism, which results from the effects of SOC on the electronic band structure. However, common complementary metal oxide semiconductor (CMOS) technology does not use HMs such as Pt, Ta, Hf and W. Instead, the commonly used metals are copper (Cu) and aluminum (Al), which intrinsically have a very small θSH. As such, it has proved problematic to integrate SOT devices with CMOS technology.
Further, current density (JC) desired for SOT induced magnetization switching using HMs (such as Pt, Ta etc.) is high, e.g., in the order of approximately 107-108 A/cm2, which hinders SOT based applications. The high value of JC causes high power consumption and necessitates a large current driving transistor. Accordingly, there is a need for a way to mitigate the issue of high JC.
In general, there is a need for a new spin current source to excite magnetization dynamics in SOT devices, to replace bulk spin current sources such as heavy metals.
An improved SOT device (e.g., a SOT-based MRAM, logic device, racetrack memory, etc.) is provided that replaces a traditional NM layer adjacent to a magnetic layer with a NM layer that includes one of three classes of materials, namely an CMOS-compatible composite (e.g., copper platinum (CuPt)) alloy, a topological insulator (TI) (e.g., bismuth selenide (Bi2Se3), bismuth selenium (BixSe1-x) alloy, bismuth antimony (Bi1-xSbx) alloy, etc.) or a TI/non-magnetic metal interface (e.g., a Bi2Se3/silver (Ag), BixSe1-x/Ag, Bi1-xSbx/Ag, etc.) interface, that provide efficient current generation.
In a first embodiment, a SOT device replaces a traditional NM layer adjacent to a magnetic layer with a CMOS-compatible alloy NM layer, made by adding nonmagnetic impurities with strong SOC (e.g., Pt) to a light metal host (e.g., Cu) that is compatible with CMOS technology. The resulting alloy, due to its impurities with strong SOC (e.g., Pt), may provide a large SHA comparable to that of a pure heavy metal (e.g., pure Pt), and by selecting a light metal host that is a widely utilized metallization element in CMOS technology (e.g., Cu) may be readily integrated into CMOS processes. The alloy may provide extrinsic SHE mechanisms that rely upon election scattering on the impurity centers, namely skew scattering and side-jump scattering. Such extrinsic SHE mechanisms may allow θSH to advantageously be tuned by changing relative concentrations of the light metal host and strong SOC impurities. Further, the alloy may advantageously sustain high CMOS backend annealing temperatures.
In a second embodiment, a SOT device stack replaces a traditional NM layer adjacent to a magnetic layer with a topological insulator (TI) (e.g., Bi2Se3, BixSe1-x, Bi1-xSbx, etc.) NM layer. TIs are an emerging state of quantum matter with strong spin-orbit coupling and excellent charge-to-spin conversion. A large SOT can be generated using a TI (e.g., Bi2Se3) by exploiting topological protected spin-momentum-locked surface states (TSS). Such large SOT may efficiently manipulate the adjacent magnetic layer and provide magnetization switching at extremely low JC in the absence of an assistive magnetic field. Low JC can enable SOT devices that have very low power consumption, allowing for small current driving transistors, and addressing other outstanding scalability issues. The absence of an assistive magnetic field further may allow for integration into well-established technologies for magnetic devices.
In a third embodiment, a SOT device stack replaces a traditional NM layer adjacent to a magnetic layer with a TI/non-magnetic metal interface (e.g., a Bi2Se3/Ag, BixSe1-x/Ag, Bi1-xSbx/Ag, etc. interface) NM layer. This 2D interface may serve as a spin current source to excite magnetization dynamics and/or drive magnetization switching, replacing bulk spin current sources such as heavy metals.
It should be understood that a variety of additional features and alternative embodiments may be implemented other than those discussed in this Summary. This Summary is intended simply as a brief introduction to the reader, and does not indicate or imply that the examples mentioned herein cover all aspects of the disclosure, or are necessary or essential aspects of the disclosure.
The description below refers to the accompanying drawings of example embodiments, of which:
Similarly, the other layers of the SOT device 200 may be made from various materials. The magnetic layer 210 may be a FM layer made from ferromagnetic materials such as iron (Fe), cobalt (Co), nickel (Ni) and their alloys (e.g., nickel iron (NiFe) alloy, cobalt iron boron (CoFeB) alloy, etc.); ferrimagnetic materials such as cobalt palladium (CoPd) alloy, cobalt terbium (CoTb), and cobalt gadolinium (CoGd) alloy, or multilayers such as [Co/Tb]n, [Co/Pd]n and [Co/Gd]n; or ferromagnetic or ferromagnetic insulators, such as yttrium iron garnet (YIG). A barrier layer (not shown) may be made from materials such as magnesium oxide (MgO), hafnium oxide (HfO) or other insulating materials or nonmagnetic metals. Likewise, the capping layer may be made from silicon oxide (SiO2), aluminum oxide (Al2O3), etc.
A. Overview
In a first embodiment, a SOT device replaces a traditional NM layer with a CMOS-compatible composite alloy (e.g., a Cu-based alloy such as CuPt alloy) NM layer that provides an extrinsic SHE mechanism. For example, in this embodiment, a SOT device may be structured as a stack that includes a substrate made of silicon (Si), a FM layer of permalloy (Py) (Ni8iFe19) (e.g., having a thickness of 5 nanometers (nm)), a CMOS compatible composite alloy NM layer made of Cu1-xPtx (e.g., having a thickness of 6 nm) where x (0-100%) is the atomic ratio of Pt in Cu1-xPtx alloy, a barrier layer of MgO (e.g., having a thickness of 1 nm), and a capping layer of SiO2 (e.g., having a thickness of 3 nm). The entire film stack may be deposited onto a thermally oxidized Si substrate at room temperature using magnetron sputtering. The composite alloy of Cu1-xPtx may be deposited by co-sputtering Cu and Pt targets. In order to tune the Pt concentration (x) in the Cu1-xPtx alloy, the sputtering power of Cu may be fixed and the sputtering power of Pt may be varied for x less than a threshold amount and the sputtering power of Pt may be fixed and the sputtering power of Cu may be varied for x greater than the threshold amount. The deposited films may be patterned using optical photolithography and argon (Ar) ion milling, among other processes.
B. An Example Test Device
In a specific test device for which experimental results are presented herein, the stack is deposited at room temperature using magnetron sputtering with a base pressure of <2×10−9 Torr. To tune the Pt concentration (x) in the Cu1-xPtx alloy, the sputtering power of Cu is fixed at 120 W and the sputtering power of Pt is varied from 0 to 150 W for x less than 75%, and the sputtering power of Pt is fixed at 60 W and the sputtering power of Cu is varied between 0 and 60 W for x greater than 75%. The deposited films are patterned into rectangular microstrips having a length of 130 μm and a width of 20 μm using optical photolithography and Ar ion milling. A coplanar waveguide (CPW) is fabricated using optical photolithography and sputter deposition to make electrical contacts with the microstrips. A gap (G) between ground and signal electrodes of the CPW is varied in the range 35-90 μm among the different devices in order to tune the device impedance close to ˜50Ω.
For the ST-FMR measurements, a microwave current of a fixed frequency (f=7, 8, or 9 GHz) is applied to Py/Cu1-xPtx bilayer. Simultaneously, an external magnetic field Hext is applied at an angle θH=35° with respect to the current channel, as shown in
C. Extraction of Spin Hall Angle and Damping
The ST-FMR spectra of
Vmix=VSFS(Hext)+VAFA(Hext),
where FS (Hext) is a symmetric Lorentzian function of amplitude VS and FA(Hext) is an antisymmetric Lorentzian function of amplitude VA. The Oersted field induced torque from the charge current in Cu1-xPtx layer is in out-of-phase with the magnetization precession and thus generates an antisymmetric Lorentzian spectrum about the resonance field, while the spin Hall torque from the generated spin current is in-phase with the magnetization precession and hence produces a symmetric Lorentzian spectrum about the resonance field.
θSH is the ratio of spin current density generated in the NM for a given charge current density. Therefore, θSH can be expressed to be proportional to the ratio VS/VA according to the equation:
θSH(VS/VA)(eμ0MStd/h)[1+(4πMeff/Hext)]1/2,
where MS and Meff are the saturation and effective magnetization of the Py layer, respectively, and t and d are the thicknesses of the Py layer and the Cu1-xPtx alloy layer, respectively.
The VS/VA ratio method utilized to determine θSH values assumes that the interfacial effects such as the Rashba effect at a FM/NM interface (here the Py/Cu1-xPtx interface) is not significant. However, if the Rashba effect is significant, it can generate an effective field-like torque term of the same symmetry as Oersted field induced torque and thus can contribute to VA. As a result, the value of θSH may not be accurately estimated from ST-FMR spectra. In order to eliminate such an issue, θSH can be determined by considering only the symmetric component VS of the ST-FMR spectrum using the equation
where Δ is the linewidth of the Lorentzian ST-FMR spectrum, E and Irf are the microwave electric field and current through the device, respectively, dR/dθH is angular dependent magnetoresistance of the device at θH=35°, and αSHE and σ are the spin Hall and longitudinal charge conductivities of the Cu1-xPtx alloy, respectively.
Apart from large θSH and smaller damping enhancement, the Cu1-xPtx alloy exists as a single-phase solid solution for temperatures up to approximately 1000° C. due to high solubility of Pt in Cu. Therefore, the Cu1-xPtx alloy can sustain high CMOS backend processing temperatures (e.g., 400° C.).
D. Contributions of Skew Scattering and Side-Jump
In order to identify the contributions from skew scattering and side-jump to the extrinsic SHE, spin Hall resistivity induced by the Pt (ρSHimp) is compared with the longitudinal resistivity induced by Pt (ρimp) for different Pt concentrations. Here, ρimp is determined using the equation ρimp=ρCuPt−ρCu, where ρCuPt and ρCu are values of the longitudinal resistivity for Cu1-xPtx alloy and pure Cu, respectively, of thicknesses 6 nm. The longitudinal resistivity for 6 nm thick pure Cu and pure Pt are measured as 20.5 μΩcm and 32 μΩcm, respectively.
To determine ρSHimp for different x, the following equation may be used:
−ρSH=σSHintρCuPt2−ρSHimp,
where ρSH is the spin Hall resistivity of Cu1-xPtx alloy determined from relation θSH=(−ρSH/ρCuPt) and σSHint is the intrinsic contributions of Cu to the spin Hall resistivity. In the equation the contributions of phonons for the spin Hall resistivity are not considered as they are negligible. However, contributions of σSHint is considered due to a non-zero θSH in Cu, even though it is one order of magnitude smaller than that in Cu1-xPtx alloy. To determine σSHint, consider the case x=0%, for which ρSHimp=0 and ρCuPt=ρCu, since ρimp=0. Hence, σSHint can be written as σSHint=−ρSH/ρCu2=θSh,Cu/ρCu, where θSH,Cu is the θSH of Cu (x=0%). Substituting the expressions for σSHint and ρSH into the above equation one obtains the equation:
−ρSHimp=ρCuPtθSH−(θSH,Cu/ρCu)ρCuPt2.
E. Thickness Dependence and Spin Diffusion Length
F. Summary of CMOS Compatible Composite Alloy Techniques
To summarize, a SOT device may be constructed that replaces a traditional NM layer with a CMOS-compatible composite alloy (e.g., a Cu-based alloy such as CuPt alloy) NM layer. The CMOS-compatible alloy (e.g., CuPt alloy) may be highly efficient (e.g., as efficient as pure Pt) in terms of spin current generation efficiency, but with a smaller damping enhancement. The CMOS-compatible composite alloy may manipulate magnetization using SOTs. Further, the CMOS-compatible composite alloy may have properties that allow it to be readily integrated into CMOS processes. For example, in the case of a CuPt alloy, the alloy may withstand high annealing temperatures, and since Cu is a widely used metallization element in CMOS technology it may be readily integrated into CMOS processes.
A. Overview
In a second embodiment, a SOT device stack replaces a traditional NM layer with a topological insulator (TI) (e.g., Bi2Se3, BixSe1-x, Bi1-xSbx, etc.) NM layer. A large SOT may be generated using a TI (e.g., Bi2Se3, BixSe1-x, Bi1-xSbx, etc.) that may efficiently switch the magnetization of an adjacent FM layer with an extremely low JC. For example, in this embodiment, a SOT device may be structured as a stack that includes, a substrate (e.g., Al2O3), a TI NM layer (e.g., having a thickness of 5-20 QL, where 1 QL is approximately equal to 1 nm), a FM layer (e.g., CoFeB or NiFe, having a thickness of 7 nm), a barrier layer of MgO (e.g., having a thickness of 2 nm), and a capping layer of Al2O3 (e.g., having a thickness of 3 nm). The TI layer may be grown on the substrate using molecular beam epitaxy (MBE) or sputtering. The CoFeB layer and insulating capping layer may be sputtered onto the TI layer. The deposited films may be patterned using optical photolithography and Ar ion milling, among other processes.
B. An Example Test Device
In a specific test device for which experimental results are presented herein, after the TI layer are grown on the substrate the CoFeB layer and insulating capping layer are sputtered onto the TI layer at room temperature, the stack is subsequently patterned into rectangular microstrips having a length of 130 μm and a width of 20 μm using optical photolithography and Ar ion milling. A CPW is fabricated using optical photolithography and sputter deposition to make electrical contacts with the microstrips. A gap (G) between ground and signal electrodes of the CPW is varied in the range 10-20 μm in order to tune the device impedance close to ˜50Ω. ST-FMR measurement are conducted as discussed above in relation to the CMOS compatible composite alloy.
C. Extraction of Spin-Orbit Torque Efficiency and the Contribution from Interfaces
As shown in
where IRF is the RF current flowing through the device, γ is the gyromagnetic ratio, dR/dθH is the angular dependent magnetoresistance at θH=35°, Δ is the linewidth of ST-FMR signal, FS (H) is a symmetric Lorentzian, H is in-plane external magnetic field, τDL is the damping-like spin-orbit torque on unit CoFeB moment at θH=0°, MS is the saturation magnetization of CoFeB, t is the thickness of CoFeB, JS is the measured spin current density with in-plane spin polarizations at the Bi2Se3/CoFeB interface, which is correlated with the measured symmetric component VS as shown in
Since the thickness of a TSS (tTSS) and two dimensional electron gas (2DEG) (t2DEG) in Bi2Se3 are reported to be approximately 1 nm and approximately 4 nm, respectively, negligible bulk states (BS) are expected when the Bi2Se3 thickness is less than 8 QL. In region I (tBiSe>10 QL), there are considerable BS and 2DEG contributions to the transport, which could dilute the TSS, resulting in a small θTI. In region II (˜10 QL), BS start to shrink, leading to a slight increase of θTI. In region III (tBiSe≤8 QL), the BS disappear and the contribution from the 2DEG decreases. On the other hand, due to the lack of inversion symmetry, Rashba splitting states in the 2DEG subbands can give rise to S∥. However, the accumulated spins due to the Rashba states are expected to have an opposite helicity (i.e. negative θTI) compared to the TSS. Since θTI always shows positive values, it may be concluded that the TSS dominated SOT is the main contribution to the large enhancement of θTI in region III.
The θTI versus tBiSe from ST-FMR measurements is obtained by using a uniform charge current density JC (A cm−2) in the entire Bi2Se3 layer as
where JS is the spin currents. The interface SOT efficiency from only TSS, λTSS (nm−1), can be obtained by the interface charge current density JC-TSS (A cm−1) in the TSS as
Therefore, one may evaluate λTSS by
where n2D and nTSS are the sheet carrier concentration in the entire Bi2Se3 film and TSS, respectively.
where JS-TSS/JC-TSS is the intrinsic interface SOT efficiency from TSS (λintTss) which is inversely proportional to VF and almost remain constant at different tBiSe, and JS-2DEG is the spin current density from Rashba splitting in 2DEG. This yields the equation:
where λ2DEG is the interface SOT efficiency from Rashba splitting in the 2DEG, JC-2DEG=n2DEG μeE and JC-TSS=nTSS μeE. One may assume that the difference of surface band bending between 7 and 8-QL Bi2Se3 films is small, which results in an almost constant λ2DEG By using the difference of λTSS between 7 and 8 QL film, the λ2DEG is determined and it shows negative value and is ˜−0.4 nm−1. Moreover, the values for λintriTSS are also estimated for tBiSe≤10 QL with negligible BS. Interestingly, such that λintriTSS shows a constant value of ˜0.8 nm−1 for 7, 8 and 10 QL Bi2Se3 films. This amended interface SOT efficiency is in the similar range of the value of λTSS (˜0.82 nm−1) at tBiSe=5 QL. This further indicates that TSS dominates SOT in thinner films and that there is high SOT efficiency from TSS.
D. SOT Driven Magnetization Switching in Bi2Se3/NiFe at Room Temperature
The SOT device also may be structured as a film stack that includes, for example, a TI NM layer (e.g., having a thickness of 8 QL where 1 QL is approximately equal to 1 nm) a FM layer of Nickel Iron (NiFe) Py (e.g., having a thickness of 6 nm), a barrier layer of MgO (e.g., having a thickness of 1 nm), and a capping layer of SiO2 (e.g., having a thickness of 4 nm). The Py/MgO/SiO2 layers may be sputtered onto the Bi2Se3 layer with an in-situ magnetic field along the y-axis (i.e. perpendicular to current channel). For testing purpose five 2-μm wide grooves may be etched on the Py layer and backfilled with nonmagnetic metal Cu, which divide the continuous Py layer into five rectangles and make them magnetically isolated. The magnetic easy axis of Py rectangles is along the ±y directions due to the shape anisotropy. This allows one to capture the magnetization switching after pulsed DC current is off, where there is no current induced spurious effects. The magnetization direction of Py is collinear with the incoming spin directions and thus the spins can directly switch the magnetization direction of Py without any external assisted magnetic field.
MOKE imaging measurements may be carried out on such an example device to observe SOT induced magnetization switching.
More specifically, the initially Py magnetization is saturated along the +y-axis by applying an in-plane external magnetic field (H). Then in the testing H is removed and I is applied along the +x-axis to the device. When the current density in Bi2Se3 is zero, the MOKE image as shown in
Moreover, based on the antidamping spin torque driven magnetization switching model with consideration of thermal fluctuation and reverse domain nucleation, the SOT efficiency of Bi2Se3 from SOT induced magnetization switching is determined. For antidamping spin torque driven magnetization switching, the critical switching current density fC0 for the switching scheme of our Bi2Se3/Py device can be described by:
where JC0 is the critical switching current density without thermal fluctuation, Ms, t, α, Hc and Meff are the saturated magnetization, thickness, damping constant, coercive field and effective magnetization of Py layer, respectively, and θTI is the SOT efficiency. This equation is based on the macrospin model in the absence of thermal fluctuation. The magnetization switching process can be described by the localized nucleation of reverse domains with an activation volume VN first, followed by domain wall propagation. Magnetization exhibits coherent reversal inside the activation volume VN. Therefore, the equation can be applied by introducing VN instead of the whole volume of Py layer. In testing, the switching current density JC for the magnetization switching is ˜6.2×105 A m−2 at room temperature. Then the JC0 can be obtained by
with thermal fluctuation considerations, where tp is the current pulse width of approximately 500 μs, t0 is the attempt time of approximately 1 ns, the anisotropy energy density KPy is estimated by HcMs/2 with measured Hc approximately 6.9 Oe and Ms=6.84±0.03×105 A m−1. The domain wall width δm of Py layer is assumed to be approximately 220 nm, and t is 6 nm, then we can estimate VN≈δm2t. Consequently, JC0 may be approximately 5.26×JC. The Meff and α may be ˜0.57 T and ˜0.01543, respectively based on experimental measurements. Further, based on experimental testing SOT efficiency θTI for Bi2Se3/Py may be approximately 1.71. This value is consistent with the value obtained from ST-FMR measurements (θTI˜1). This agreement further indicates the excellent efficiency of TIs in spin generation and SOT driven magnetization switching.
F. Summary of Topological Insulator Techniques
To summarize, a SOT device may be constructed that replaces a traditional NM layer with a TI (e.g., Bi2Se3, BixSe1-x, Bi1-xSbx, etc.) NM layer. Such TI NM layer may be a highly efficient spin current generator. In the case of a device that uses a Bi2Se3 TI NM layer (as discussed above), the Bi2Se3 layer may, for example, exhibit a SOT efficiency up to approximately 1.75 at room temperature, which corresponds to an interface SOT efficiency of λTSS=0.8 nm−1. The SOT induced magnetization switching may be successfully achieved at room temperature without any external magnetic field. The current density required for the magnetization switching in a SOT device employing a TI NM layer may be extremely low. For example, in the case of an example device that uses a Bi2Se3 TI NM layer (as discussed above), current density may be approximate 6×105 A/cm2 which is almost two orders of magnitude smaller than that in heavy metals. Utilizing a TI NM layer, a device may achieve very low power consumption, addressing scalability issues in modern magnetic devices. Furthermore, as an assistive magnetic field may not be required, a TI NM layer may be readily integrated into existing technologies for magnetic devices.
A. Overview
In a third embodiment, a SOT device stack replaces a traditional NM layer with a TI/non-magnetic metal interface (e.g., a Bi2Se3/Ag, BixSe1-x/Ag, Bi1-xSbx/Ag, etc. interface) layer adjacent to the FM layer. A TI/non-magnetic metal interface (e.g., Bi2Se3/Ag interface) Rashba effect can induce efficient charge-spin conversion. This Rashba interface may serve as a spin current source to achieve TI-based room temperature spin devices with high scalability and efficiency. For example, in one embodiment, a SOT device may be structured as a film stack that includes a substrate made of Al2O3, a Bi2Se3/Ag interface layer (e.g., having a Bi2Se3 thickness of 10 QL where 1 QL is approximately equal to 1 nm, and an Ag thickness (tAg) up to 5 nm), a FM layer of Co40Fe40B20 (e.g., having a thickness of 7 nm), a barrier layer of MgO (e.g., having a thickness of 2 nm), and a capping layer of SiO2 (e.g., having a thickness of 4 nm).
B. An Example Test Device and In-Plane Torque/Out-of-Plane Torque Ratio
In a specific test device for which experimental results are presented herein, samples are prepared as discussed above with tAg=0, 1, 2, 3, 5 nm.
C. Extraction of the Charge-Spin Conversion Efficiency
Using techniques as discussed above in reference to the second embodiment, one may extract the charge-to-spin conversion efficiency in both Bi2Se3/Ag/CoFeB devices and Ag/CoFeB devices. To evaluate the spin orbit torque ratio (θ∥), one may assume that the charge conductivity of the Bi2Se3/Ag is no more than the conductivity for the Bi2Se3 single layer capped with 2 nm of MgO and 4 nm of SiO2, which is ˜6.99×104 Ω−1m−1 from probe measurements. This value is comparable with the value obtained in Bi2Se3 with a Al2O3 cap. With this assumption, one may obtain a lower bound of θ∥ in Bi2Se3/Ag/CoFeB.
D. Rashba Effect Driven Magnetization Switching in Bi2Se3/Ag/NiFe at Room Temperature
The interfacial Rashba effect driven magnetization switching at room temperature in an example Bi2Se3 (10 QL)/Ag (2 nm)/NiFe (6 nm) sample is demonstrated by MOKE microscopy.
E. Summary of TI/Non-Magnetic Metal Interface Techniques
To summarize, a SOT device may be constructed that replaces a traditional NM with a TI/non-magnetic metal interface (e.g., a Bi2Se3/Ag, BixSe1-x/Ag, Bi1-xSbx/Ag, etc. interface) layer adjacent to the FM layer. This interface may exhibit efficient charge-to-spin current conversion process originating from the interface Rashba effect. Such a process may be dependent on the thickness of the non-magnetic metal. In the case of a Bi2Se3/Ag interface the Rashba induced charge-to-spin conversion may be Ag-thickness dependence, in a specific example (as discussed above) saturating at tAg approximately equals 2 nm. High charge-spin conversion efficiency may be achieved. In the case of an example Bi2Se3/Ag/CoFeB device (as discussed above) a value of spin orbit torque ratio of approximately 0.5 may be achieved at room temperature. This charge-spin conversion efficiency may be further increased by improving the interface quality. The Rashba effect induced magnetization switching may be successfully achieved at room temperature without any external magnetic field. The current density required for the magnetization switching in a SOT device employing a TI/nonmagnetic metal interface (e.g., Bi2Se3/Ag) may be extremely low.
It should be understood that various adaptations and modifications may be made to the above-discussed techniques. For example, while it is discussed above that the various metal and oxide layers (such as the CMOS-compatible composite alloy layer) may be deposited using magnetron sputtering, it should be understood that a variety of other metal and oxide growth techniques may be utilized. Likewise, while it is discussed above that MBE may be used to grow a TI layer, it should be understood that a variety of other TI growth techniques may be utilized. In addition, while a number of example layers of device stack are discussed, it should be understood that additional or different layers, interfaces or junctions may be employed. For instance, in embodiments utilizing a TI or TI/non-magnetic metal interface, a magnetic functional part on top of the TI or TI/non-magnetic metal interface can also be magnetic tunnel junctions (MTJ) composed of any of a variety of materials. The MTJ may have a traditional sandwiched structure. The MTJ can also have a synthetic antiferromagnetic (SAF) or single antiferromagnetic exchange biased free magnetic layer and a SAF or single antiferromagnetic pinned reference magnetic layer.
In general, it should be appreciated that details included in the various example embodiments are merely provided for purposes of illustration, and are not intended to limit the scope, applicability, or configuration of the invention. For example, it should be understood that the various elements described above may be made from differing materials, implemented in different combinations or otherwise formed or used differently without departing from the intended scope of the invention. What is claimed is:
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