Patent Application
20190304524
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely on innovative devices such as spin orbit torque (SOT) memory devices including a spin orbit torque electrode coupled with a compatible MTJ device to overcome the requirements imposed by scaling.
Non-volatile embedded memory with SOT memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a material layer stack to form functional SOT memory devices present formidable roadblocks to commercialization of this technology today. Specifically, increasing thermal stability in SOT memory devices are some important areas of device development.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified “ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
Spin orbit torque (SOT) memory devices with enhanced stability and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present disclosure may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.
As used throughout this description, and in the claims, a list of items joined by the term “at least one of' or “one or more of' can mean any combination of the listed terms. For example, the phrase
A SOT memory device may include a magnetic tunnel junction (MTJ) device formed on a spin orbit torque electrode. The MTJ device functions as a memory device where the resistance of the MTJ device switches between a high resistance state and a low resistance state. The resistance state of an MTJ device is defined by the relative orientation of magnetization between a free magnet and a fixed magnet that are separated by a tunnel barrier. When the magnetization of the free magnet and a fixed magnet have orientations that are in the same direction, the MTJ device is said to be in a low resistance state. Conversely, when the magnetization of the free magnet and a fixed magnet each have orientations that are in opposite direction to each other, the MTJ device is said to be in a high resistance state.
In an embodiment, in an absence of a spin orbit torque electrode, resistance switching in an MTJ device is brought about by passing a critical amount of spin polarized current through the MTJ device so as to influence the orientation of the magnetization of the free magnet to align with the magnetization of the fixed magnet. The act of influencing the magnetization is brought about by a phenomenon known as spin torque transfer, where the torque from the spin polarized current is imparted to the magnetization of the free magnet. By changing the direction of the current, the direction of magnetization in the free magnet may be reversed relative to the direction of magnetization in the fixed magnet. Since the free magnet does not need a constant source of spin polarized current to maintain a magnetization direction, the resistance state of the MTJ device is retained even when there is no current flowing through the MTJ device. For this reason, the MTJ device belongs to a class of memory known as non-volatile memory.
As an MTJ device is scaled down in size, the amount of critical spin polarized current density required to switch the device increases. By implementing an MTJ device on a SOT electrode, the magnetization in the free magnet may undergo torque assisted switching from a Spin Hall current, induced by passing an electrical current through the SOT electrode in a direction transverse to a thickness of the MTJ device material stack. The Spin Hall current arises from spin dependent scattering of electrons due to a phenomenon known as spin orbit interaction. Electrons of one spin polarity are directed towards an upper portion of the spin orbit torque electrode and electrons with an opposite spin polarity are directed toward a bottom portion of the spin orbit torque electrode. Electrons of a particular spin polarity are directed toward the MTJ device and impart a spin orbit torque on the magnetization of the free magnet. The spin hall current may also help the MTJ device switch faster. It is to be appreciated that, in an embodiment, the spin hall current can fully switch a free magnet having a magnetization that is oriented in an in-plane direction. An in-plane direction is defined as a direction that is parallel to an uppermost surface of the spin orbit torque electrode. An external field may be utilized to exert a torque to completely switch the perpendicular free magnet from an in plane direction.
Integrating a non-volatile memory device such as an SOT memory device onto access transistors enables the formation of embedded memory for system on chip (SOC) applications. However, approaches to integrate an SOT memory device onto access transistors presents challenges that have become far more formidable with scaling. One such challenge is the need to improve stability of the SOT memory device against thermal fluctuations during the lifetime of a device. Thermal fluctuations can cause unwanted reversal of magnetization of the free magnet, the fixed magnet or both, leading to loss of information stored in an SOT memory device. As the MTJ memory device in the SOT memory device typically includes a multilayer stack of magnetic and non-magnetic materials, the stack is engineered for thermal stability. The thermal stability of the multilayer stack depends on the strength of the magnetic anisotropy and on the thickness of the free magnet in the MTJ memory device.
In some embodiments, the free magnet further includes two magnetic layers separated by a coupling layer to increase thermal stability. A first magnetic layer is adjacent to the tunnel barrier and a second magnetic layer is in contact with the spin orbit torque electrode. The thermal stability of the free magnet may be increased due to an increase in magnetism called interfacial magnetic anisotropy arising from interfaces between each of the first and second magnetic layers and the adjacent non-magnetic coupling layer. While thermal stability may be increased, switching current may be impacted when there are multiple magnets that are required to undergo magnetization switching. Switching current may be minimized, however, when the magnetic layer that is proximal to (e.g., in physical contact with) the spin orbit torque electrode is able to favorably utilize the polarized Spin Hall current to initiate the magnetization switching and influence the second of the magnetic layers proximal to the tunnel barrier to switch magnetization orientation. Such a phenomenon may be realized when the magnetic layer that is proximal to the spin orbit torque electrode has a magnetic anisotropy that is greater than the magnetic anisotropy of the magnetic layer proximal to the tunnel barrier.
When the two magnetic layers of a free magnet are ferromagnetically coupled, thermal stability may also be increased. Ferromagnetic coupling takes place through a phenomenon known as magnetic dipole coupling through a second coupling layer between the first and the second magnetic layers in a free magnet, and may be enhanced by tuning the second coupling layer composition and thickness. Depending on embodiments, the second coupling layer may include a highly conductive material such as a metal, or a partially conductive material such as a dielectric layer that permits electron tunneling.
As MTJ devices (formed on spin orbit torque electrode) are scaled, the need for smaller memory cell size has driven the industry in the direction of perpendicular MTJs. Perpendicular MTJs are memory devices where the fixed magnet and the free magnet have magnetic anisotropy that is perpendicular with respect to a plane defining an uppermost surface of the spin orbit torque electrode. Relative to an in-plane device, a perpendicular MTJ with a ferromagnetically coupled free magnet having at least two magnetic layers on a spin orbit torque electrode has several advantages, such as increased thermal stability.
In accordance with embodiments of the present disclosure, a spin orbit torque (SOT) memory device includes a first electrode including a spin orbit torque material and a magnetic tunnel junction (MTJ) device coupled with the first electrode. In an embodiment, the first electrode has uppermost surface area that is 10 to 20 times larger than a lowermost surface area of the MTJ device. In an embodiment, the MTJ device includes a free magnet structure that includes a magnetic enhancement layer to improve stability (herein referred to as a magnetic stability enhancement layer), a free magnet, and a spacer between magnetic stability enhancement layer and the free magnet. The magnetic stability enhancement layer may be a magnetic material. The free magnet is coupled with the magnetic stability enhancement layer. The spacer enables ferromagnetic coupling between the magnetic stability enhancement layer and the free magnet. The free magnet structure collectively undergoes magnetization switching. In an exemplary embodiment, the magnetic stability enhancement layer undergoes magnetization switching first and then the free magnet switches in response to magnetization switching of the magnetic stability enhancement layer. The MTJ device further includes a fixed magnet having a magnetization that does not change orientation during operation of the SOT memory device, a tunnel barrier between the free magnet and the fixed magnet, and a second electrode coupled with the fixed magnet.
Referring again to
The electrode 101 includes a metal with high degree of spin orbit coupling. A metal with a high degree of spin-orbit coupling has an ability to inject a large spin polarized current in to the free magnet structure 106. A large spin polarized current can exert a large amount of torque and influence the magnetization of the free magnet structure 106 for faster switching. In an embodiment, the electrode 101 includes a metal such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, electrode 101 includes a beta phase tantalum or beta phase tungsten. An electrode 101 including a beta phase tantalum or beta phase tungsten has a high spin hall efficiency. With a high spin hall efficiency, the electrode 101 can generate a large spin hall current for a given charge current that is passed through the electrode 101. In an embodiment, the electrode 101 has thickness of between 2 nm and 20 nm.
In an embodiment, the magnetic stability enhancement layer 108 includes an alloy of a magnetic material and a non-magnetic material. In some embodiments, the non-magnetic material includes a metal such as platinum, palladium and iridium, and the magnetic material includes a metal such as cobalt or iron. In another embodiment, the magnetic stability enhancement layer 108 is a ferrimagnet alloy including manganese and at least one other element, such as germanium, aluminum or gallium. The magnetic stability enhancement layer 108 may have a thickness between 4 nm and 10 nm for perpendicular MTJ devices.
In some embodiments, the magnetic stability enhancement layer 108 includes a multilayer stack of alternating layers of magnetic layer 108A and a non-magnetic layer 108B on the magnetic layer 108A, as is illustrated in
In other embodiments, the magnetic stability enhancement layer 108 includes a multilayer stack of alternating layers of non-magnetic layer 108B and a magnetic layer 108A on the non-magnetic layer 108B, as illustrated in
Referring again to
In an embodiment, the free magnet 112 includes a magnetic material such as Co, Ni, Fe or alloys of these materials. In an embodiment, the free magnet 112 includes a magnetic material such as CoB, FeB, CoFe or CoFeB. In some embodiments, the free magnet 112 includes a Co100-x-yFexBy, where X and Y each represent atomic percent, further where X is between 50 and 80 and Y is between 10 and 40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnet 112 is FeB, where the concentration of boron is between 10 and 40 atomic percent of the total composition of the FeB alloy. In an embodiment, the free magnet 112 has a thickness between 0.9 nm and 2.0 nm for pMTJ devices.
In an embodiment, tunnel barrier 114 is composed of a material suitable for allowing electron current having a majority spin to pass through tunnel barrier 114, while impeding, at least to some extent, electron current having a minority spin from passing through tunnel barrier 114. Thus, tunnel barrier 114 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In an embodiment, tunnel barrier 114 includes a material such as, but not limited to, oxygen and at least one of magnesium (e.g., a magnesium oxide, or MgO), or aluminum (e.g., an aluminum oxide such as Al2O3). In an embodiment, tunnel barrier 114 including MgO has a crystal orientation that is (001) and is lattice matched to free magnet 112 below tunnel barrier 114 and fixed magnet 116 above tunnel barrier 114. In an embodiment, tunnel barrier 114 is MgO and has a thickness in the range of 1 nm to 2 nm. In an embodiment, a free magnet 112 including a Co100-x-yFexBy, is highly lattice matched to the tunnel barrier 114 including an MgO. Lattice matching a crystal structure of the free magnet 112 with the tunnel barrier 114 enables a higher tunneling magnetoresistance (TMR) ratio in the pMTJ device 104.
In some embodiments, the fixed magnet 116 includes a material and has a thickness sufficient for maintaining a fixed magnetization. In an embodiment, the fixed magnet 116 of the pMTJ device 104 includes an alloy such as CoFe or CoFeB. In an embodiment, the fixed magnet 116 comprises a Co100-x-yFexBy, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10 and 40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 116 is FeB, where the concentration of boron is between 10 and 40 atomic percent of the total composition of the FeB alloy. In an embodiment the fixed magnet 116 has a thickness that is between 1 nm-3 nm.
Conversely,
In an embodiment, the free magnet structure 106 and the fixed magnet 116 can have approximately similar thicknesses and an injected spin polarized current which changes the direction of the magnetization 154 in the free magnet structure 106 can also affect the magnetization 156 of the fixed magnet 116. In an embodiment, to make the fixed magnet 116 more resistant to accidental flipping the fixed magnet 116 has a higher magnetic anisotropy than the free magnet structure 106. In another embodiment, a synthetic antiferromagnetic (SAF) structure 118 can be disposed between the electrode 120 and the fixed magnet 116 in order to prevent accidental flipping of the magnetization 156 in the fixed magnet 116 as illustrated in
It is to be appreciated that an additional layer of non-magnetic spacer layer may exist between the fixed magnet 116 and the A structure 118 (not illustrated in
Referring again to
In an embodiment, the substrate 122 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 122 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 122. Logic devices such as access transistors may be integrated with memory devices such as SOT memory devices to form embedded memory. Embedded memory including SOT memory devices and logic MOSFET transistors can be combined to form functional integrated circuit such as a system on chip.
Referring once again to the plan view illustration of
In an embodiment, the pMTJ device 104 has a center, CAM and the electrode 101 has a center, CSOT. In an embodiment, CMTJ is aligned to CSOT in X and Y directions, as illustrated in
The magnetic stability enhancement layer 108 provides stability and the spacer 110 couples the magnetic stability enhancement layer 108 to composite free magnet 212 via dipole coupling. The dipole coupling is proportional to the saturation magnetization and the thickness of the magnetic stability enhancement layer 108 and the composite free magnet 212. In an embodiment, the free layer 214 includes a magnetic material such as Co, Ni, Fe or alloys of these materials. In an embodiment, the free layer 214 includes a magnetic material such as CoB, FeB, CoFe or CoFeB. In some embodiments, the free layer 214 includes a Co100-x-yFexBy, where X and Y each represent atomic percent, further where X is between 50 and 80 and Y is between 10 and 40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free layer 218 includes a magnetic material such as Co, Ni, Fe or alloys of these materials. In an embodiment, the free layer 218 includes a magnetic material such as CoB, FeB, CoFe or CoFeB. In some embodiments, the free layer 218 includes a Co100-x-yFexBy, where X and Y each represent atomic percent, further where X is between 50 and 80 and Y is between 10 and 40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In some embodiments, the free layer 214 includes a material that is the same or substantially the same as the material of the free magnet 112. In some embodiments, the free layer 218 includes a material that is the same or substantially the same as the material of the free magnet 112.
The conductive layer 216 may include a metal such as tungsten, molybdenum or tantalum. Depending on embodiments, the conductive layer 216 has a thickness between 0.2 nm and 0.5 nm. In some embodiments, a conductive layer 216 having a thickness between 0.2 nm and 0.5 nm may be discontinuous. In some such embodiments portions of the free layer 214 may be in direct contact with the free layer 218.
In one exemplary embodiment, when a pSOT memory device 200 includes a composite free magnet 212, the spacer 110 comprises a material including oxygen and magnesium. A spacer 110 including oxygen and magnesium may enable a higher TMR in the pSOT memory device 200.
In other embodiments, the magnetic stability enhancement layer 108 may include one or more structures having one or more properties of the magnetic stability enhancement layer 108 described above in association with
In an embodiment, a charge current 160 is passed through the electrode 101 in the negative y-direction. In response to the charge current 160, an electron current 162 flows in the positive y-direction. The electron current 162 includes electrons with two opposing spin orientations, a type I electron 166, having a spin oriented in the negative x-direction and a type II electron 164 having a spin oriented in the positive X-direction. In an embodiment, electrons in the electron current 162 experience a spin dependent scattering phenomenon in the electrode 101. The spin dependent scattering phenomenon is brought about by a spin-orbit interaction between the nucleus of the atoms in the electrode 101 and the electrons in the electron current 162. The spin dependent scattering phenomenon causes type I electrons 166, whose spins are oriented in the negative x-direction (into the page of
In an exemplary embodiment, the free magnet structure 106 includes the magnetic stability enhancement layer 108 and the free magnet 112 separated by spacer 110. In such an embodiment, the magnetic stability enhancement layer 108 experiences Spin Hall torque and undergoes magnetization switching. The free magnet 112 which is dipole coupled with the magnetic stability enhancement layer 108 and has a magnetic anisotropy that is weaker than a magnetic anisotropy of the magnetic stability enhancement layer 108, subsequently undergoes magnetization switching.
A read operation to determine a state of the MTJ device 104 may be performed by voltage biasing a third terminal C, connected to the fixed magnet 116 with respect to the either terminal and A and B, where the terminals A or B are grounded (not illustrated).
In an embodiment, the dielectric layer 403 includes an electrically insulating material such as, but not limited to, silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide.
In some embodiments, the deposition process is carried without an air break and the individual layers are blanket deposited using a variety of deposition processes in a cluster tool. Some layers may be deposited using a physical vapor deposition (PVD) process, for example. Other examples of deposition processes may include a co-sputter or a reactive sputtering process to deposit various layers of the composite free magnet 409.
In an embodiment, the magnetic stability enhancement layer 411 is deposited by a physical vapor deposition (PVD) process. In an embodiment, the magnetic stability enhancement layer 411 includes an alloy of a magnetic material and a non-magnetic material. In some embodiments, the non-magnetic material includes a metal such as platinum, palladium and iridium and the magnetic material includes a metal such as cobalt or iron. In an embodiment, the magnetic stability enhancement layer 411is a ferrimagnet alloy including manganese and an element such as germanium, aluminum or gallium. In some embodiments, the magnetic stability enhancement layer 411 includes a material that is the same or substantially the same as the material of the magnetic stability enhancement layer 108. In other embodiments, the magnetic stability enhancement layer 411 includes a multilayer stack of alternating layers of magnetic layer and a non-magnetic layer on the magnetic layer. In some such embodiments, the non-magnetic layer and the magnetic layer each include materials that are respectively the same or substantially the same as the material of the non-magnetic layer 108B and the material of the magnetic layer 108A. In one embodiment, the non-magnetic layer 108B may include a metal such as platinum, palladium or iridium and magnetic layer 108A may include a magnetic material such as cobalt.
The spacer layer 413 is deposited on the magnetic stability enhancement layer 411 to enable ferromagnetic coupling between the magnetic stability enhancement layer 411 and a subsequent free magnet that will be formed. In an embodiment, the spacer layer 413 is deposited using a PVD process. In an embodiment, the spacer layer 413 includes a material that is the same or substantially the same as the material of the spacer 110. In various embodiments, the spacer layer 413 is deposited to a thickness that depends on the choice of material utilized. The thickness of the spacer layer 413 advantageously provides ferromagnetic coupling between the magnetic stability enhancement layer 411 and the free magnetic layer 415 and ranges between 3 nm and 5 nm.
Referring again to
In another embodiment, forming the composite free magnet 409 includes depositing a first free magnet on the spacer layer 413, wherein the spacer layer 413 includes magnesium and oxygen, depositing a conductive layer on the first free magnet and depositing a second free magnet on the conductive layer. In some embodiments, the first magnetic layer includes a material that is substantially the same as the material of the free layer 218 and the second magnetic layer includes a material that is substantially the same as the material of the free layer 214 described in association with
In some embodiments, a tunnel barrier layer 417 is blanket deposited on the free magnetic layer 415. In an embodiment, the tunnel barrier layer 417 includes a material such as MgO or Al2O3. In an exemplary embodiment, the tunnel barrier layer 417 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the tunnel barrier layer 417 is deposited to a thickness between 0.8 nm to 1 nm. In an embodiment, the deposition process is carried out in a manner that yields a tunnel barrier layer 417 having an amorphous structure. In some examples, the amorphous tunnel barrier layer 417 becomes crystalline after a high temperature anneal process to be described further below. In other embodiments, the tunnel barrier layer 417 is crystalline as deposited.
In an embodiment, the fixed magnetic layer 419 is blanket deposited on an uppermost surface of the tunnel barrier layer 417. In an embodiment, the deposition process includes a physical vapor deposition (PVD) or a plasma enhanced chemical vapor deposition process. In an embodiment, the PVD deposition process includes an RF or a DC sputtering process. In an exemplary embodiment, the fixed magnetic layer 419 is Co100 -x-yFexBy, where X and Y each represent atomic percent, further where X is between 50 and 80 and Y is between 10 and 40, and further where the sum of X and Y is less than 100. In some embodiments, the fixed magnetic layer 419 includes a material that is the same or substantially the same as the material of the fixed magnet 116 described above. In some examples, the fixed magnetic layer 419 may be deposited to a thickness between 2.0 nm and 3.0 nm.
The process is continued with deposition of layers utilized to form a SAF layer 421. In some embodiments, the layers utilized to form SAF layer 421 are blanket deposited on the fixed magnetic layer 421 using a PVD process. The layers utilized to form SAF layer 421 are the same or substantially the same as the layers in the SAF structure 118 described above.
In an embodiment, the deposition process concludes with a blanket deposition of an electrode layer 421 on an uppermost surface of the SAF layer 421. In an embodiment, the electrode layer 423 includes a material that is suitable to act as a hardmask during a subsequent etching of the pMTJ material layer stack 450 to form a pMTJ device on the electrode 101. In an embodiment, the electrode layer 423 includes a material such as TiN, Ta or TaN. In an embodiment, the thickness of the top electrode layer ranges from 5 nm to 70 nm. The thickness of the electrode layer 423 is chosen to accommodate patterning of the pMTJ material layer stack 450 to form a pMTJ device.
In an embodiment, after all the layers in the pMTJ material layer stack 450 are deposited, an anneal is performed. In an embodiment, the anneal process enables formation of a crystalline MgO—tunnel barrier layer 417 to be formed. In an embodiment, the anneal is performed immediately post deposition but before patterning of the pMTJ material layer stack 450. A post-deposition anneal of the pMTJ material layer stack 450 is carried out in a furnace at a temperature between 300 to 350 degrees Celsius in a forming gas environment. In an embodiment, the forming gas includes a mixture of H2 and N2 gas. In an embodiment, the annealing process promotes solid phase epitaxy of the free magnetic layer 415 to follow a crystalline template of the tunnel barrier layer 417 (e.g., MgO) that is directly above the free magnetic layer 415. In an embodiment, the anneal also promotes solid phase epitaxy of the fixed magnetic layer 419 to follow a crystalline template of the tunnel barrier layer 417 (e.g., MgO) that is directly below the fixed magnetic layer 419. <001>Lattice matching between the tunnel barrier layer 417 and the free magnetic layer 415 and <001>lattice matching between the tunnel barrier layer 417 and the fixed magnetic layer 419 enables a TMR ratio between 90% and 110% to be obtained in the pMTJ material layer stack 450.
In an embodiment, when the free magnetic layer 415 includes boron, the annealing process enables boron to diffuse away from an interface 430 between the free magnetic layer 415 and the tunnel barrier layer 417. The process of diffusing boron away from the interface 430 enables lattice matching between the free magnetic layer 415 and the tunnel barrier layer 417. In an embodiment, when the fixed magnetic layer 419 includes boron, the annealing process enables boron to diffuse away from an interface 432 between the fixed magnetic layer 419 and the tunnel barrier layer 417.
In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets a direction of magnetization of the fixed magnetic layer 419, the free magnetic layer 415 and the magnetic stability enhancement layer 411. In an embodiment, during the annealing process, an applied magnetic field that is directed perpendicular to a plane of pMTJ material layer stack 450 enables a perpendicular anisotropy to be set in the fixed magnetic layer 419, in the free magnetic layer 415 and in the magnetic stability enhancement layer 411. In an embodiment, the annealing process initially aligns the magnetization of the fixed magnetic layer 419, magnetization of the free magnetic layer 415 and the magnetization of the magnetic stability enhancement layer 411 to be parallel to each other and perpendicular to the plane of the pMTJ material layer stack 450.
While one pMTJ material layer stack 450 has been described in this embodiment, a material layer stack for forming the pMTJ device 204 illustrated in
In an embodiment, the plasma etch process is then continued to pattern the remaining layers of the pMTJ material layer stack 450 to form a pMTJ device 104. The plasma etch process etches the various layers in the pMTJ material layer stack 450 to form a SAF structure 118, a fixed magnet 116, a tunnel barrier 114, a free magnet 112, a spacer layer 110, and a magnetic stability enhancement layer 108. The plasma etch process also exposes the electrode 101 and portions of the underlying dielectric layer 102. In some embodiments, depending on the etch parameters, the pMTJ device 104 may have sidewalls that are tapered as indicated by the dashed lines 425. The pMTJ device 104 formed over the electrode 101, constitutes a perpendicular spin orbit torque memory device 100.
In an embodiment, the transistor 500 has a source region 504, a drain region 506 and a gate 502. The transistor 500 further includes a gate contact 514 above and electrically coupled to the gate 502, a source contact 516 above and electrically coupled to the source region 504, and a drain contact 518 above and electrically coupled to the drain region 506 as is illustrated in
In an illustrative embodiment, one portion of electrode 101 is in electrical contact with the drain contact 518 of transistor 500. A pMTJ contact 528 is on and electrically coupled with the electrode 120 of the pMTJ device 104. An interconnect metallization structure 540 is on and electrically coupled with the electrode 101, and the pMTJ device 104 is between the drain contact 538 and the interconnect metallization structure 540. In the illustrative embodiment, the pMTJ device 104 is laterally between the drain contact 538 and interconnect metallization structure 540. In some embodiments, the pMTJ device 104 is laterally closer to the drain contact 538 than to interconnect metallization structure 540. In other embodiments, the pMTJ device 104 is laterally closer to the interconnect metallization structure 540 than to the drain contact 538. In some embodiments, the pMTJ device 104 is approximately mid-way, laterally, between the interconnect metallization structure 540 and the drain contact 538. In an embodiment, the electrode 101 is also above and adjacent to a dielectric layer 550. In an embodiment, the dielectric layer 550 includes an electrically insulating material such as, but not limited to, silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide.
In an embodiment, the underlying substrate 501 represents a surface used to manufacture integrated circuits. Suitable substrate 501 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as substrates formed of other semiconductor materials. The substrate 501 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.
In an embodiment, the access transistor 500 associated with substrate 501 are metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 501. In various implementations of the invention, the access transistor 500 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
In an embodiment, the access transistor 500 of substrate 501 includes a gate 502 including at least two layers, a gate dielectric layer 502A and a gate electrode 502B. The gate dielectric layer 502A may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 502A to improve its quality when a high-k material is used.
The gate electrode 502B of the access transistor 500 of substrate 501 is formed on the gate dielectric layer 502A and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode 502B may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.
For a PMOS transistor, metals that may be used for the gate electrode 502B include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode 502B may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode 502B may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some implementations of the invention, a pair of sidewall spacers 51A may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 51A may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers may include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. Source region 504 and drain region 506 may be formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 504 and drain region 506 are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 504 and drain region 506. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate 501 may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 504 and drain region 506. In some implementations, the source region 504 and drain region 506 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 504 and drain region 506 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 504 and drain region 506. In the illustrative embodiment, an isolation 508 is adjacent to the source region 504, drain region 506 and portions of the substrate 501.
In an embodiment, a source contact 516 and a drain contact 518 are formed in a dielectric layer 511 and in the dielectric layer 512 above the gate electrode 502B. In the illustrative embodiment, a source metallization structure 524 is coupled with the source contact 516 and a gate metallization structure 526 is coupled with the gate contact 514. In the illustrated embodiment, a dielectric layer is adjacent to the gate contact 514, drain contact 518, source contact 516.
In an embodiment, the source contact 516, the drain contact 518 and gate contact 518 each include a multi-layer stack. In an embodiment, the multi-layer stack includes two or more distinct layers of metal such as a layer of Ti, Ru or Al and a conductive cap on the layer of metal. The conductive cap may include a material such as W or Cu. In some embodiments, a dielectric spacer 526 may be adjacent to the MTJ device 104, where the dielectric layer includes a material that is the same or substantially the same as the material of the dielectric spacer 426.
The isolation 508, and dielectric layer 520 may include any material that has sufficient dielectric strength to provide electrical isolation such as, but not, limited silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.
In an embodiment, when the transistor 500 is energized in a manner that causes charge current to flow through the electrode 101, a Spin Hall current is generated in the electrode 101. In one such embodiment, the interconnect metallization structure 540 is voltage biased with respect to the source contact 516 (with a bias applied to gate contact 514 to enable a channel under the gate 502 to enable charge current to flow through the SOT electrode 101. The Spin Hall current will exert a torque on the magnetization of the magnetic stability enhancement layer 108 of the pMTJ device 104, enabling a change in a direction of magnetization in the magnetic stability enhancement layer 108. In the illustrative embodiment, the magnetization in the free magnet 112, which is dipole coupled with the magnetic stability enhancement layer 108 will change direction in response to a change in direction of magnetization in the magnetic stability enhancement layer 108. The mechanism for generation of Spin Hall current in a SOT electrode such as SOT electrode 101 is described above in association with
A read operation of the pMTJ device 104 may be enabled, for example, by applying a bias voltage between 0.1V and 0.2V between on the MTJ contact 528 and the interconnect metallization structure 540.
Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset 606, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
Communication chip 605 enables wireless communications for the transfer of data to and from computing device 600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 605 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.6 family), WiMAX (IEEE 802.6 family), IEEE 802.10, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 600 may include a plurality of communication chips 604 and 605. For instance, a first communication chip 605 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 604 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
Processor 601 of the computing device 600 includes an integrated circuit die packaged within processor 601. In some embodiments, the integrated circuit die of processor 601 includes one or more memory devices, such as a spin orbit torque memory device 100, including a pMTJ device 104, and spin orbit torque memory device 100, including a pMTJ device 204 in accordance with embodiments of the present disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
Communication chip 605 also includes an integrated circuit die packaged within communication chip 606. In another embodiment, the integrated circuit die of communication chips 604, 605 include a memory array with memory cells including at least one pSOT memory device such as a pSOT memory device 200 including a MTJ device 204 on a SOT electrode 101.
In various examples, one or more communication chips 604, 605 may also be physically and/or electrically coupled to the motherboard 602. In further implementations, communication chips 604 may be part of processor 601. Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM) 607, 608, non-volatile memory (e.g., ROM) 610, a graphics CPU 612, flash memory, global positioning system (GPS) device 613, compass 614, a chipset 606, an antenna 616, a power amplifier 609, a touchscreen controller 66, a touchscreen display 617, a speaker 615, a camera 603, and a battery 618, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In further embodiments, any component housed within computing device 600 and discussed above may contain a stand-alone integrated circuit memory die that includes one or more arrays of memory cells including one or more memory devices, such as a spin orbit torque memory device 100, including a pMTJ device 104, and spin orbit torque memory device 100, including a pMTJ device 204 built in accordance with embodiments of the present disclosure.
In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.
The integrated circuit (IC) structure 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The integrated circuit (IC) structure may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 710. The integrated circuit (IC) structure 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, device structure including transistors, such as transistors 500 and 520 coupled with a with one at least one pMTJ memory device such as a pMTJ device 104, or pMTJ device 204 where the pMTJ devices 104 includes a free magnet structure having a free magnet that is dipole coupled to a magnetic stability enhancement layer and where the pMTJ devices 204 includes a free magnet structure having a composite free magnet that is dipole coupled to a magnetic stability enhancement layer, (such as described above) for example. The integrated circuit (IC) structure 700 may further include embedded devices 714 such as one or more resistive random-access devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 700. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 700.
Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a perpendicular spin orbit torque memory device such as the perpendicular spin orbit torque memory device 100 or a perpendicular spin orbit torque memory device 200. The perpendicular spin orbit torque memory devices 100, 200 may be used in an embedded non-volatile memory application
Thus, embodiments of the present disclosure include spin orbit torque memory devices with enhanced stability and methods to form the same.
Specific embodiments are described herein with respect to perpendicular spin orbit torque devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices such as in-plane STTM or perpendicular STTM devices.
