This present disclosure relates in general to the semiconductor power devices, and more particularly to split-gate trench MOSFETs and methods of manufacturing such devices.
Power metal oxide semiconductor field effect transistors (MOSFETs) are commonly used power devices due to their low gate drive power, fast switching speed and superior paralleling capability. Most power MOSFETs feature a vertical structure with source and drain regions on opposite sides of a gate trench filled with polysilicon as gate electrodes. In such structures, the MOS channels are formed along the vertical walls of the trenches. One configuration of a trench MOSFET device includes a gate trench lined with thicker oxide in the lower part of the trench and thinner oxide in its upper part. Thus, the oxide has a stepped structure, there being a step in its thickness. The stepped gate structure with a thicker oxide at the bottom portion of the trench increases the breakdown voltage of the device.
In recent years, split-gate trench structures are developed and preferred for certain applications over conventional trench MOSFETs. A split-gate trench power MOSFET comprises two electrodes in a gate trench. A first electrode serves as the gate electrode to control the channel formation of the MOSFET, and a second electrode serves as shield electrode to decrease the capacitance Cgd between drain electrode and gate electrode. Generally, the gate electrode and the shield electrode are formed in a self-aligned process that uses a single mask to form a set of trenches that are used for both the gate electrode and the shield electrode. Since the shield electrode is at source potential, it usually extends to surface and is further coupled to a pick-up structure at a terminal region which is located at sides of the MOSFET. This increases the source electrode resistance. Furthermore, extra masks are needed to create such connection and thereby increasing the cost of manufacturing.
It is within this context that embodiments of the present invention arise.
Objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Trenches 106 are formed in the substrate through the body region. The trenches 106 are lined with an insulating material 108, e.g., an oxide. The oxide 108 in the bottom portion of the trench is usually thicker than the oxide 108 in the top portion. A bottom electrode 110 is formed in a lower portion of each trench 106. A top electrode 112 is formed in an upper portion. The bottom electrode 110 is insulated from the top electrode 112 by the oxide 108. Another insulating material 114 electrically insulates the top electrode 112 from the source metal 103.
It is noted that, in certain applications, there is a need to connect the top and bottom electrodes 110 and 112 together while keeping dual layers of oxides with two thicknesses for the top and bottom electrodes. Conventional approaches to connect these electrodes may include a straight contact structure 113 filled with conductive materials that connects all the way through to a bottom electrode 110 in a trench with no top electrode as shown in
Embodiments of the present invention provide a through-poly-contact (TPC) structure in split-gate transistor devices for electrically connecting the top electrode to the bottom electrode. Specifically, a TPC structure can be formed in the same contact etch step by etching all the way through the top electrode, the inter-polysilicon oxide and the bottom electrode and filling conductive materials to form a single deep conductive plug. For embodiments where an electrical connection between the top and bottom electrodes is not desired, one additional mask is required after formation of the top electrode to form an insulating structure filled with insulating materials in the top electrode to break the electrical connection with the bottom electrode.
One or more split-gate trenches 210 are formed in the semiconductor substrate 201. One or more bottom electrodes 212 are formed in the bottom of the trench 210. The bottom electrodes 212 are electrically insulated from the semiconductor substrate, e.g., by an insulator material 215, such as an oxide or nitride, which may coat the walls of a set of the split-gate trenches 210 in which the bottom electrodes are formed. One or more top electrodes 214 are formed in the top portion of the split-gate trenches 210 between the bottom electrodes and a surface of the substrate. The top electrodes 214 are separated from the semiconductor substrate 201 by an insulating material 217 such as oxide or nitride and separated from the one or more bottom electrodes 212 by an inter-poly dielectric layer (or poly oxide) 219. In some embodiments, the insulating material 217 has a thickness less than that of the insulating material 215. As shown in
Aspects of the present disclosure include methods for fabricating a split-gate trench transistor device of the types described above. By way of example, and not by way of limitation, a split-gate trench transistor device like the device of
In the following discussion, an N-type device is described for purposes of illustration. P-type devices may be fabricated using a similar process but with opposite conductivity types. In
A hard mask layer can be formed on top of the substrate 502, for example, by forming a thin oxide layer 504 on the substrate 502 by deposition or thermal oxidation, followed by a nitride layer 506 on top of the thin oxide layer 504. In some embodiments, the thickness of the silicon oxide layer ranges from about 100 Å to 500 Å and is preferably about 200 Å. In some embodiments, the thickness of the nitride layer ranges from 1500 Å to 4000 Å and is preferably about 3500 Å. Another oxide layer 508 may be disposed on top of the nitride layer 506 to form the hard mask with an oxide/nitride/oxide stack. In some embodiments, the thickness of the oxide layer 508 ranges from 1000 Å to 3000 Å and is preferably about 2000 Å. A photo resist layer (not shown) is then applied on top of the oxide/nitride/oxide stack and patterned using a trench mask. A hard mask etch is then performed to etch away exposed portions of the nitride layer 506 and oxide layers 504 and 508 as shown in
In
Next, conductive material 512, such as polysilicon, is deposited into the trenches and over the semiconductor substrate followed by a chemical mechanical polishing (CMP) to remove polysilicon over the oxide layer 508 leaving the conductive material only in the trench 510 as shown in
The conductive material layer 512 is then etched back in the upper portions of the trenches. In one example, the conductive material layer 512 is etched to a target depth using a timed etch-back process. In some embodiments, the conductive material layer 512 is etched to a depth about 0.55 μm below the surface of the semiconductor substrate 502. Then the liner oxide 515 along the etched upper portion of the trenches is stripped, e.g., using a wet etch. A thin insulating layer 518 (e.g., gate oxide) is formed to cover the upper portion of trench wall and another thin insulating layer 517 (e.g., poly oxide) is formed atop the bottom portion of the conductive material layer 512 as shown in 5F forming the bottom electrode. The insulating layer 518 is about 150 to 500 Angstroms (Å) in thickness and the insulating layer 517 is about 250 to 800 Å in thickness.
A second layer of conductive material 514, such as polysilicon, is deposited into upper portion of the trenches and over the substrate followed by a CMP to remove polysilicon over the oxide layer 508. In the particular case of polysilicon, this layer of conductive material is sometimes referred to as gate poly or Poly 2. The second conductive layer 514 is then etched back preferably about 500 Å above the top surface of the substrate 502. Another oxidation step is performed in the trenches forming the oxide later 519 followed by a CMP to remove oxides 519 and oxide layer 508 above the nitride layer 506 as shown in
In
Next, a low temperature oxide (LTO) layer and a borophosphosilicate glass (BPSG) layer 556 are deposited as shown in
A first contact mask 560 is applied and an etch process is performed to form ESD contact openings 558 through the BPSG layer and the LTO layer as shown in
Another contact mask 562 is applied and another etch process is performed to open the arrays of source and body contact openings 563 between the trenches in the active cell region as shown in
In the embodiments where the connection between the top electrode and bottom electrode is not desired, one additional mask is required after formation of the top electrode to etch the top conductive layer 514 and fill oxides to form an insulating structure near the contact structure 520 thereby removing connection between the top and bottom electrodes.
While the above is a complete description of the preferred embodiments of the present invention, it is possible to use various alternatives, modifications, and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A” or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for”. Any element in a claim that does not explicitly state “means for” performing a specified function, is not to be interpreted as a “means” or “step” clause as specified in 35 USC §112, ¶6.
This application is a division of U.S. patent application Ser. No. 14/260,215, filed Apr. 23, 2014, the entire contents of which are incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
7504676 | Bhalla et al. | Mar 2009 | B2 |
7585705 | Pan et al. | Sep 2009 | B2 |
7859047 | Kraft et al. | Dec 2010 | B2 |
8053298 | Bhalla et al. | Nov 2011 | B2 |
8394702 | Tai et al. | Mar 2013 | B2 |
8507978 | Bhalla et al. | Aug 2013 | B2 |
8618601 | Chen | Dec 2013 | B2 |
20060209887 | Bhalla et al. | Sep 2006 | A1 |
20070155104 | Marchant | Jul 2007 | A1 |
20070158701 | Chang et al. | Jul 2007 | A1 |
20070194374 | Bhalla et al. | Aug 2007 | A1 |
20090072301 | Bhalla et al. | Mar 2009 | A1 |
20090148995 | Chang et al. | Jun 2009 | A1 |
20100044792 | Hebert | Feb 2010 | A1 |
20110037120 | Chen et al. | Feb 2011 | A1 |
20110039383 | Chen et al. | Feb 2011 | A1 |
20110068386 | Tai et al. | Mar 2011 | A1 |
20110133258 | Chen | Jun 2011 | A1 |
20110204440 | Bhalla et al. | Aug 2011 | A1 |
20110220990 | Chang et al. | Sep 2011 | A1 |
20120098059 | Tai et al. | Apr 2012 | A1 |
20120187472 | Chang | Jul 2012 | A1 |
20120205737 | Chen et al. | Aug 2012 | A1 |
20130105886 | Lui et al. | May 2013 | A1 |
20130328122 | Li | Dec 2013 | A1 |
20140134813 | Chen | May 2014 | A1 |
20150311295 | Lee et al. | Oct 2015 | A1 |
Number | Date | Country |
---|---|---|
103346166 | Oct 2013 | CN |
Entry |
---|
Non-Final Office Action for U.S. Appl. No. 14/260,215, dated Oct. 6, 2015. |
Notice of Publication for U.S. Appl. No. 14/260,215, dated Mar. 21, 2016. |
Office Action for CN Application No. 201510155606.7, dated Jul. 4, 2017. |
Number | Date | Country | |
---|---|---|---|
20160329426 A1 | Nov 2016 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14260215 | Apr 2014 | US |
Child | 15214335 | US |