Stacked chip packaging structure

Abstract

A stacked chip packaging structure (10) includes a substrate (20), a first chip (40), a second chip (70), and a cover (80). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires (50a). The second chip is mounted above the first chip and above the wires connected with the first chip and is electrically connected with the substrate via a second plurality of wires (50b). The cover is mounted above the second chip and the wires connected with the second chip. The mounting of the second chip and the cover in such a manner is facilitated through the use of an adhesive/glue (60a, 60b) that is able to function both as an adherent and as a spacer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present stacked chip packaging structure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the stacked chip packaging structure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a schematic, cross-sectional view of a stacked chip packaging structure, according to a first preferred embodiment;

FIG. 2 is a schematic, cross-sectional view of a stacked chip packaging structure, according to a second preferred embodiment;

FIG. 3 is a schematic, cross-sectional view of a stacked chip packaging structure, according to a third preferred embodiment;

FIG. 4 is a schematic, cross-sectional view of a stacked chip packaging structure, according to a fourth preferred embodiment;

FIG. 5 is a schematic, cross-sectional view of a stacked chip packaging structure, according to a fifth preferred embodiment; and

FIG. 6 is a cross-sectional view of a typical stacked chip package.

Claims

1. A stacked chip packaging structure, comprising: a substrate including a plurality of top contacts arranged thereon;a first chip attached to the substrate, the first chip comprising a plurality of first pads disposed on an upper surface thereof;a second chip disposed above the first chip, the second chip comprising a bottom surface facing the first chip and an upper surface provided with a plurality of second pads thereon;a plurality of wires electrically respectively connecting one of the first and second contacts to a corresponding top contact of the substrate, each wire forming a wire loop; anda cover disposed above the second chip, the cover having a bottom surface facing the second chip;wherein the bottom surface of the second chip is above the wire loops of the wires connected with the first chip, and the bottom surface of the cover is above the wire loops of the wires connected with the second chip.

2. The stacked chip packaging structure as claimed in claim 1, further comprising an adhesive applied to the upper surface of the first chip and to a periphery of an upper surface of the second chip, wherein the adhesive applied to the first chip holds and thereby spaces the second chip above the wire loops of the wires connected with the first chip, the adhesive applied to the first chip fixing the bottom surface of the second chip thereto, the adhesive applied to the second chip holding the cover above the wire loops of the wires connected with the second chip, the adhesive applied to the second chip fixing the bottom surface of the cover thereto.

3. The stacked chip packaging structure as claimed in claim 2, wherein the adhesive is further applied to the wires in a manner so as to cover the whole of each wire.

4. The stacked chip packaging structure as claimed in claim 1, wherein the substrate comprises a board portion and a frame portion attached to the board portion, and the board portion and the frame portion cooperatively define a receiving cavity therein to respectively receive the first and second chips therein.

5. The stacked chip packaging structure as claimed in claim 4, wherein the top contacts includes a plurality of first top contacts and a plurality of second top contacts, the first top contacts are arranged on the board portion and exposed to the cavity and are respectively electrically connected with corresponding first pads of the first chip, and the second top contacts are arranged on the frame portion and respectively electrically connect with corresponding second pads of the second chip.

6. The stacked chip packaging structure as claimed in claim 1, wherein the substrate comprises a board portion, a first frame portion, and a second frame portion arranged in that order, bottom-to-top, and the board portion and the first and second frame portions cooperatively define a receiving cavity therein to receive the first and second chips therein.

7. The stacked chip packaging structure as claimed in claim 6, further comprising an adhesive, wherein the adhesive is applied to at least one of the upper surface of the first chip and an inner periphery of an upper surface of the first frame portion to fix the second chip thereon, and the adhesive holds and thereby spaces the second chip above the wire loops of the wires connected with the first chip.

8. The stacked chip packaging structure as claimed in claim 7, wherein the adhesive is further applied to a periphery of the second chip and holds the cover above the wire loops of the wires connecting with the second chip.

9. The stacked chip packaging structure as claimed in claim 8, wherein the adhesive is further applied to the wires in a manner so as to cover the whole of each wire.

10. The stacked chip packaging structure as claimed in claim 8, wherein the adhesive is further applied to the top of the second frame portion to fix the bottom surface of the cover thereto.

11. The stacked chip packaging structure as claimed in claim 8, wherein the substrate further comprises a third frame portion, the third frame portion is attached to the second frame portion, and the adhesive is further applied to the top of the third frame portion to fix the bottom surface of the cover thereto.

12. The stacked chip packaging structure as claimed in claim 6, wherein the top contacts comprises a plurality of first top contacts and a plurality of second top contacts, the first top contacts are arranged on at least one of the board portion and the first frame portion and are electrically connected with the first pads of the first chip, and the second top contacts are arranged on at least one of the first frame portion and the second frame portion and are electrically connected with the second pads of the second chip.

13. A stacked chip packaging structure, comprising: a substrate;a first chip mounted on the substrate, the first chip being electrically connected with the substrate via a first plurality of wires;a second chip mounted above the first chip and the wires connected with the first chip, the second chip being electrically connected with the substrate via a second plurality of wires; anda cover mounted above the second chip and the wires connected with the second chip.

14. The stacked chip packaging structure as claimed in claim 13, wherein an adhesive is used to achieve at least one of the mounting of the second chip above the first chip and the mounting of the cover above the second chip, the adhesive being configured to act as a spacer.