The present disclosure relates to integrated circuit (IC); more particularly, relates to, by filling notches or apertures with a conductive material on stacking at least two chips, using circuit contacts and the notches or apertures to connect IC chips together with wires for achieving flexibility of circuit layout, easy fabrication and enhanced reliability.
A conventional chip packaging technique comprises the following steps:
(a) A semiconductor chip is provided, where the chip has a pad mounting surface and a plurality of solder pads disposed on the pad mounting surface; and where the solder pads are not corresponding to solder contacts.
(b) A steel plate is placed on the surface having the solder pads to form through holes. Therein, through holes are formed to expose a part of the solder pads on the surface having the solder pads and to expose a part of the surface having the solder pads too. Thus, a space between walls of the through holes and the surface having the solder pads is obtained for forming electric conductors.
(c) A conductive metal paste is used to form the electric conductors in the above mentioned space through printing. Each electric conductor has an extended part extended from a corresponding solder pad of the chip; and an electrical contact corresponding to the corresponding solder pad of the chip at a free end of the extended part. Thus, by narrowing distance between adjacent solder pads, the problem of hard to be electrically connected with outside circuit is solved.
Although the above prior art can be electrically connected with outside circuit with ease, its connection with the outside circuit is only on one surface. On piling up the chips, a plurality of apertures is required and a conductive material has to be filled into the apertures for connecting two surfaces. Therein, a tool is used to drill out the apertures on the chips; then, a insulative layer is formed on each wall of the apertures through printing, coating, jet printing, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating or electroless plating, so as to present the chips from short cut; and, then, the conductive material is filled into the apertures to connect two surfaces of the chips.
However, because the insulative layer has to be formed after the drilling and the conductive material has to be filled in, the fabrication becomes complicated with low yield and bad reliability. Hence, the prior art does not fulfill all users' requests on actual use.
The main purpose of the present disclosure is to, by filling notches or apertures with a conductive material on stacking at least two chips, use circuit contacts and the notches or apertures to connect IC chips for achieving flexibility of circuit layout, easy fabrication and improved reliability.
To achieve the above purpose, the present disclosure is a stacked integrated circuit device, comprising at least one chip; at least one notch; at least one aperture; a conductive material; and a plurality of wires, where the chip has a plurality of circuit contacts and a plurality of circuit areas; where the notch is located on a peripheral surface of the chip; where the aperture is located at center of the chip; where the aperture is formed through hot drilling and an insulative layer is formed on obtaining the aperture through hot drilling; where the conductive material is located in the notch and the aperture; and where the wire connects the circuit contact, the circuit area and the conductive material. Accordingly, a novel stacked integrated circuit device is obtained.
The present disclosure will be better understood from the following detailed descriptions of the preferred embodiments according to the present disclosure, taken in conjunction with the accompanying drawings, in which
The following descriptions of the preferred embodiments are provided to understand the features and the structures of the present disclosure.
Please refer to
The chip 1 is made of silicon or silicon doped with boron, phosphorus, arsenic or antimony for forming an n-type or p-type material. The chip 1 has a plurality of circuit contacts 11 and a plurality of circuit areas 12 at center of a surface of the chip 1. The circuit contacts 11 and the circuit areas 12 are set on the chip 1 through a semiconductor process. According to requirement, the circuit contacts 11 can be set on a surface of the chip 1, as shown in
The notch 2 is set on a peripheral surface of the chip 1 respectively and is a shallow radius notch.
The aperture 3 is set at center of the chip 1 and is a circle via, where the aperture 3 is formed in the chip 1 through hot drilling in an oxygen environment by using a device like laser; and where, as shown in
The conductive material 4 is set in the notch 2 and the aperture 3 and is a silver paste, where the conductive material 4 is set in the notch 2 and the aperture 3 through a semiconductor process.
The wire 5 connects the circuit contact 11, the circuit area 12 and the conductive material 4 respectively through a semiconductor process. Thus, a novel stacked integrated circuit device is obtained.
Please refer to
Moreover, the apertures 3 are further filled with a conductive material (e.g. silver paste) to connect two surfaces of the chip 1. On stacking, the two chips 1 are formed on the passivation layer 6 at places corresponding to the circuit contacts 11 and the circuit areas 12 to be connected with the wires 5 through the apertures 3. By filling the conductive material 4 into the apertures 3, the two chips 1 and the wires 5 are electrically connected through the apertures 3 for easy fabrication and enhanced reliability.
Please refer to
Moreover, the apertures 3 are further filled with a conductive material (e.g. silver paste) to connect the chips 1,1a. On stacking, the chips 1,1a are formed on the passivation layer 6 at places corresponding to the circuit contacts 11,11a and the circuit areas 12.12a to be connected with the wires 5 through the apertures 3. By filling the conductive material 4 into the apertures 3, the chips 1,1a and the wires 5 are connected through the apertures 3 for easy fabrication and enhanced reliability.
To sum up, the present disclosure is an integrated circuit stacking device, where chips are connected by circuit contacts, circuit areas and apertures filled with a conductive material for easy fabrication and enhanced reliability.
The preferred embodiments herein disclosed are not intended to unnecessarily limit the scope of the disclosure. Therefore, simple modifications or variations belonging to the equivalent of the scope of the claims and the instructions disclosed herein for a patent are all within the scope of the present disclosure.
Number | Date | Country | Kind |
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097212216 | Jul 2008 | TW | national |