Patent Application
20240421156
The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous within many products, particularly as they continue to decrease in cost and size. There is a continued desire to reduce the size of structural features and/or to provide a greater amount of structural features for a given chip size. Miniaturization, in general, allows for increased performance at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field-effect transistors (FETs), and capacitors.
Embodiments of the invention provide techniques for forming stacked transistor structures with hybrid gate pitch.
In one embodiment, a semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. The second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.
In another embodiment, a semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height, wherein the second level is vertically stacked over the first level, and a middle-of-line contact between a first region of one of the transistors in the first set of transistors in the first level and a second region of one of the transistors in the second set of transistors in the second level, the first region at least partially overlapping the second region.
In another embodiment, an integrated circuit includes a stacked transistor structure including a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. The second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.
Illustrative embodiments of the invention may be described herein in the context of illustrative methods for forming stacked transistor structures with hybrid gate pitch, along with illustrative apparatus, systems and devices formed using such methods. However, it is to be understood that embodiments of the invention are not limited to the illustrative methods, apparatus, systems and devices but instead are more broadly applicable to other suitable methods, apparatus, systems and devices.
A field-effect transistor (FET) is a transistor having a source, a gate, and a drain, and having action that depends on the flow of carriers (electrons or holes) along a channel that runs between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate.
FETs are widely used for switching, amplification, filtering, and other tasks. FETs include metal-oxide-semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, where both n-type and p-type transistors (nFET and pFET) are used to fabricate logic and other circuitry. Source and drain regions of a FET are typically formed by adding dopants to target regions of a semiconductor body on either side of a channel, with the gate being formed above the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage current from flowing into the channel when voltage is applied to the gate conductor while allowing applied gate voltage to produce a transverse electric field in the channel.
Various techniques may be used to reduce the size of FETs. One technique is through the use of fin-shaped channels in FinFET devices. Before the advent of FinFET arrangements, CMOS devices were typically substantially planar along the surface of the semiconductor substrate, with the exception of the FET gate disposed over the top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of the channel exposed to the gate. Thus, in FinFET structures the gate can more effectively control the channel, as the gate extends over more than one side or surface of the channel. In some FinFET arrangements, the gate encloses three surfaces of the three-dimensional channel, rather than being disposed over just the top surface of a traditional planar channel.
Another technique useful for reducing the size of FETs is through the use of stacked nanosheet channels formed over a semiconductor substrate. Stacked nanosheet channels may be two-dimensional nanostructures, such as sheets having a thickness range on the order of 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to 7 nm and beyond. A general process flow for formation of a nanosheet stack involves removing sacrificial layers, which may be formed of silicon germanium (SiGe), between sheets of channel material, which may be formed of silicon (Si).
Increasing demand for high density and performance in integrated circuit devices requires development of new structural and design features, including shrinking gate lengths and other reductions in size or scaling of devices. Continued scaling, however, is reaching limits of conventional fabrication techniques.
Stacking transistors in a vertical direction gives an additional dimension for CMOS area scaling. There are various challenges, however, in forming stacked FET structures. One challenge is in locally wiring “bottom” transistor devices to “top” transistor devices, or vice versa. Conventional approaches either lead to poor performance (e.g., when trying to use extremely small contacts to save area for scaling and parasitic capacitance) or larger cell size (e.g., when trying to make a robust contact size and contact spacing). Another challenge is in forming multiple threshold voltages (Vt) with a monolithic fabrication process. Even with bonded flows, bottom to top misalignment (e.g., including misalignment in the range of 2-3 nm) will break the process margin, because there is a need to make fine contacts through the top to the bottom devices, at very tight pitches (e.g., both gate pitch and metallization layer pitches). There is thus a need for solutions for forming stacked transistor structures with improvements in transistor density with design flexibility.
Illustrative embodiments provide a stacked transistor structure with hybrid gate pitch. In some embodiments, a semiconductor device comprises a first or upper level of transistors (e.g., CMOS devices) with a first gate pitch and a first cell height, and a second or lower level of transistors (e.g., CMOS devices) with a second gate pitch and a second cell height, where the first gate pitch is different than the second gate pitch. The first cell height may also be different than the second cell height. Middle-of-line (MOL) connections between the first/upper and second/lower transistors may be formed in some locations where source/drain regions for the first/upper transistors and source/drain regions for the second/lower transistors at least partially overlap with each other, and/or where the source/drain regions of the first/upper transistors and gate regions of the second/lower transistors at least partially overlap one another. One or more deep vias may be formed to connect frontside and backside interconnects (e.g., frontside back-end-of-line (BEOL) interconnects and backside BEOL interconnects). One or more backside interconnects may be connected to the second/lower transistors through backside contacts. The frontside interconnects may comprise both power delivery and signal wirings. The backside interconnects may also comprise both power delivery and signal wirings.
A process flow for forming stacked transistors with hybrid gate pitch may include forming a first set of transistors (e.g., a bottom or lower level) with a first gate pitch and a first cell height, and forming a second set of transistors (e.g., a top or upper level) with a second gate pitch and a second cell height, where the first gate pitch is different than the second gate pitch. The first cell height may also be different than the second cell height. The process flow may also include forming MOL contacts for the first set of transistors, and forming connections between source/drain regions of one or more of the transistors in the first set of transistors and source/drain regions of one or more of the transistors in the second set of transistors only at locations where such source/drain regions at least partially overlap one another. The process flow may further include forming connections between source/drain regions of one or more of the transistors in the first set of transistors and gate regions of one or more of the transistors in the second set of transistors only at locations where such source/drain and gate regions at least partially overlap one another. The process flow may further include forming deep MOL vias (e.g., from a top or frontside of the structure through and into shallow trench isolation regions for the second set of transistors). The process flow may also include forming frontside BEOL interconnects, bonding the structure to a carrier wafer, performing a wafer flip, removing the substrate, and forming backside contacts and backside BEOL interconnects. Connections may also be formed to connect the backside contacts and/or backside BEOL interconnects with one or more of the deep MOL vias.
An illustrative process flow for forming stacked transistor structures with hybrid gate pitch will now be described in further detail with respect to
The first substrate 102 and semiconductor layer 106 may be formed of any suitable semiconductor structure, including various silicon-containing materials including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC) and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc.
The etch stop layer 104 may comprise a buried oxide (BOX) layer or silicon germanium (SiGe), or another suitable material such as a III-V semiconductor epitaxial layer. The etch stop layer 104 may have a height (in direction Z) in the range of 10 to 30 nm.
The channel layers 114 may be formed of similar materials as the first substrate 102 and the semiconductor layer 106. Initially, a nanosheet stack including alternative sacrificial layers and the channel layers 114 may be formed, with the sacrificial layers later being removed and replaced with the gate regions 118. Each of the channel layers 114 may have a thickness (in direction Z) in the range of 4-10 nm.
The STI regions 108 may be formed by patterning a masking layer over the nanosheet stack (e.g., of the alternating sacrificial layers and the channel layers 114), and etching exposed portions of the nanosheet stack and through a portion of the semiconductor layer 106, followed by deposition or other formation of material for the STI regions 108. The STI regions 108 may be formed of a dielectric material such as silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon oxynitride (SiON), etc. The STI regions 108 may have a height (in direction Z) in the range of 20 to 100 nm.
The spacers 112-1 and 112-2 may be formed as part of dummy gate processing, where dummy gates are formed over the nanosheet stack, with the sacrificial layers of the nanosheet stack being selectively removed followed by formation of material of the spacers 112-1 and 112-2. The spacer 112-1 provides a bottom insulator, and the spacer 112-2 provides gate sidewall spacers. The spacers 112-1 and 112-2 may be formed of any suitable insulator such as SiN, silicon boron carbide nitride (SiBCN), silicon oxycarbonitride (SiOCN), etc. The spacer 112-1 may have a height (in direction Z) in the range of 6-15 nm, and the spacer 112-2 may have a uniform thickness in the range of 2-10 nm.
The first source/drain regions 110-1 and the second source/drain regions 110-2 (collectively, source/drain regions 110) may be formed after formation of dummy gates over the nanosheet stack. Sacrificial layers of the nanosheet stack are indented (e.g., using an indent etch process), followed by formation of the inner spacers 116 in the regions formed by the indent etch of the sacrificial layers of the nanosheet stack. The inner spacers 116 may be formed of silicon nitride (SiN) or another suitable material such as SiBCN, silicon carbide oxide (SiCO), SiOCN, etc. The inner spacers 116 may have widths (in direction X) in the range of 2-10 nm, and may have heights (in direction Z) matching that of the sacrificial layers of the nanosheet stack.
The source/drain regions 110 may be formed using epitaxial growth processes, and thus may also be referred to as epitaxial layers. The first source/drain regions 110-1 and the second source/drain regions 110-2 may be suitably doped, such as using ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, etc. In some embodiments, the first source/drain regions 110-1 provide n-type source/drain regions while the second source/drain regions 110-2 provide p-type source drain regions, or vice versa. N-type dopants may be selected from a group of phosphorus (P), arsenic (As) and antimony (Sb), and p-type dopants may be selected from a group of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (Tl). In some embodiments, the epitaxy process used to form the source/drain regions 110 comprises in-situ doping (dopants are incorporated in epitaxy material during epitaxy). Epitaxial materials may be grown from gaseous or liquid precursors. Epitaxial materials may be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and/or carbon doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor to be formed. The dopant concentration in the source/drain can range from 1×1019 cm−3 to 3×1021 cm−3, or preferably between 2×1020 cm−3 to 3×1021 cm−3. The source/drain regions 110 may each have a width (in direction Y) in the range of 10 to 50 nm, and height (in direction Z) in the range of 30 to 100 nm.
After the source/drain regions 110 are formed, the gate regions 118 may be formed. The dummy gates and sacrificial layers of the nanosheet stack may be removed, followed by formation of a gate stack for the gate regions 118 (e.g., using high-k metal gate (HKMG) processing). The gate stack may comprise a gate dielectric layer and a gate conductor layer. The gate dielectric layer may be formed of a high-k dielectric material. Examples of high-k materials include but are not limited to metal oxides such as HfO2, hafnium silicon oxide (Hf—Si—O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer may have a uniform thickness in the range of 1 nm to 3 nm.
The gate conductor layer may include a metal gate or work function metal (WFM). The WFM for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti and Al alloys, a stack which includes a barrier layer (e.g., of TiN, TaN, etc.) followed by one or more of the aforementioned WFM materials, etc. It should be appreciated that various other materials may be used for the gate conductor layer as desired.
The ILD layer 120 may be formed surrounding the source/drain regions 110 as illustrated. The ILD layer 120 may be formed of any suitable isolating material, such as SiO2, SiOC, SiON, etc.
The first set of transistors shown in the structure of
The first source/drain regions 128-1 and second source/drain regions 128-2 (collectively, source/drain regions 128) may be formed using similar processing as that described above with respect to the source/drain regions 110. The first source/drain regions 128-1 may comprise n-type source/drain regions while the second source/drain regions 128-2 may comprise p-type transistors, or vice versa. The inner spacers 130, the gate regions 134 and the ILD layer 136 may be formed of similar materials and with similar sizing as that described above with respect to the inner spacers 116, the gate regions 118 and the ILD layer 120, respectively.
The second set of transistors shown in the structure of
The cross-sectional view 1220 of
The cross-sectional view 1240 of
The cross-sectional view 1260 of
A fundamental issue with the stacked transistor approaches shown in
Semiconductor devices and methods for forming the same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
In some embodiments, the above-described techniques are used in connection with semiconductor devices that may require or otherwise utilize, for example, complementary metal-oxide-semiconductors (CMOSs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and/or fin field-effect transistors (FinFETs). By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.
Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
In some embodiments, a semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. The second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.
The first gate pitch may be greater than the second gate pitch.
The first cell height may be greater than the second cell height.
The semiconductor structure may further include a MOL contact between (i) a first source/drain region of one of the transistors in the first set of transistors in the first level and (ii) a second source/drain region of one of the transistors in the second set of transistors in the second level, wherein the first source/drain region at least partially overlaps the second source/drain region.
The semiconductor structure may further include a MOL contact between (i) a source/drain region of one of the transistors in the first set of transistors in the first level and (ii) a gate region of one of the transistors in the second set of transistors in the second level, wherein the source/drain region at least partially overlaps the gate region.
The semiconductor structure may further include at least one via connecting a first interconnect on a first side of the semiconductor structure below the first level and a second interconnect on a second side of the semiconductor structure above the second level.
The semiconductor structure may further include at least one interconnect on a first side of the semiconductor structure below the first level which connects to at least one transistor of the first set of transistors of the first level through one or more contacts below the first level.
The semiconductor structure may further include one or more interconnects on a first side of the semiconductor structure below the first level, the one or more interconnects on the first side of the semiconductor structure including a power delivery network and signal wirings.
The semiconductor structure may further include one or more interconnects on a second side of the semiconductor structure above the second level, the one or more interconnects on the second side of the semiconductor structure including a power delivery network and signal wirings.
In some embodiments, a semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height, wherein the second level is vertically stacked over the first level, and a MOL contact between a first region of one of the transistors in the first set of transistors in the first level and a second region of one of the transistors in the second set of transistors in the second level, the first region at least partially overlapping the second region
The first gate pitch may be different than the second gate pitch, and the first cell height may be different than the second cell height.
The first region may include a first source/drain region of said one of the transistors in the first set of transistors and the second region includes a second source/drain region of said one of the transistors in the second set of transistors.
The first region may include a source/drain region of said one of the transistors in the first set of transistors and the second region includes a gate region of said one of the transistors in the second set of transistors.
The semiconductor structure may further include at least one via connecting a first interconnect on a first side of the semiconductor structure below the first level and a second interconnect on a second side of the semiconductor structure above the second level.
In some embodiments, an integrated circuit includes a stacked transistor structure including a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. The second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.
The first gate pitch may be greater than the second gate pitch.
The first cell height may be greater than the second cell height.
The integrated circuit may further include a MOL contact between (i) a first source/drain region of one of the transistors in the first set of transistors in the first level and (ii) a second source/drain region of one of the transistors in the second set of transistors in the second level, wherein the first source/drain region at least partially overlaps the second source/drain region.
The integrated circuit may further include a MOL contact between (i) a source/drain region of one of the transistors in the first set of transistors in the first level and (ii) a gate region of one of the transistors in the second set of transistors in the second level, wherein the source/drain region at least partially overlaps the gate region.
It should be understood that the various layers, structures, and regions shown in the figures are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the figures to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures are not repeated for each of the figures. It is to be understood that the terms “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, temperatures, times and other process parameters, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “approximately” or “substantially” as used herein implies that a small margin of error is present, such as ±5%, preferably less than 2% or 1% or less than the stated amount.
In the description above, various materials, dimensions and processing parameters for different elements are provided. Unless otherwise noted, such materials are given by way of example only and embodiments are not limited solely to the specific examples given. Similarly, unless otherwise noted, all dimensions and process parameters are given by way of example and embodiments are not limited solely to the specific dimensions or ranges given.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
