Claims
- 1. A semiconductor apparatus, said apparatus comprising:
a semiconductor substrate member; a core region of said semiconductor substrate having a plurality of first field oxide pads having a first thickness, an alignment marker formed on said semiconductor substrate, said alignment marker having said first thickness; a dielectric material deposited over said plurality of first field oxide pads and said alignment marker, said dielectric material being a protective layer to prevent formation of oxide material on said plurality of first field oxide pads and said alignment marker.
- 2. A semiconductor apparatus as described in claim 1, said apparatus further comprising:
a second region of said semiconductor substrate formed as a peripheral region, said peripheral region having a plurality of second field oxide pads having a second thickness, said second thickness being greater than said first thickness; and said dielectric material being removed to expose said alignment marker for facilitating subsequent wafer alignment accuracy using a stepper alignment technique.
- 3. A semiconductor apparatus as described in claim 2, wherein:
said dielectric material comprises silicon nitride.
- 4. A semiconductor apparatus, said apparatus comprising:
a semiconductor substrate member; a core region delineated on said semiconductor substrate member, said core region having a plurality of first field oxide pads having a first thickness; an alignment marker formed on said semiconductor substrate, said alignment marker having said first thickness; and a peripheral region delineated on said semiconductor substrate, said periphery region having a plurality of second field oxide pads having a second thickness, said alignment marker being unobstructed by oxide material comprising said second field oxide pads and facilitating subsequent wafer alignment accuracy during a die-by-die, stepper alignment technique.
- 5. A semiconductor apparatus as described in claim 4, wherein:
said core region comprises a semiconductor region for forming a memory semiconductor apparatus capable of performing data erasure operations.
- 6. A method for producing wafer alignment accuracy in a semiconductor fabrication process after undergoing a dual field oxide semiconductor fabrication process, said method comprising the steps of:
(a) providing a first photomask member having mask portions for forming a plurality of first field oxide regions on a first region of a semiconductor substrate, said first mask member also having a mask portion for forming an alignment marker; (b) providing a second photomask member having mask portions for forming a plurality of second field oxide regions on a second region of said semiconductor substrate, said second mask member also having mask portions delineated for covering any first field oxide regions and alignment marker formed by using said first photomask member; (c) forming said first field oxide regions and said alignment marker utilizing said first photomask member; (d) covering said formed first field oxide regions and said alignment marker with a photoresist material by utilizing said second photomask member; (e) forming said second said field oxide regions after utilizing said second photomask member; and (f) facilitating wafer alignment accuracy by removing said photoresist material and exposing said alignment marker for use in subsequent semiconductor fabrications process steps.
- 7. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 6, wherein:
said steps (c), (d), (e), and (f) comprise utilizing a stepper wafer alignment means.
- 8. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 6, wherein:
said step (d) comprises covering said formed first field oxide regions and said alignment marker with a silicon nitride material having a thickness of 1700Å.
- 9. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 6, wherein:
said step (c) comprises ) forming said first field oxide regions and said alignment marker with a silicon dioxide material having a thickness of 2000Å; and said step (e) comprises ) forming said second field oxide regions with a silicon dioxide material having a thickness of 4000Å.
- 10. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 6, wherein:
said step (f) facilitates a further series of fabrication steps for forming a memory semiconductor apparatus capable of performing block data erasure operations.
- 11. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 6, wherein:
said step (f) facilitates checking for alignment of subsequent masks used in subsequent fabrication steps by using said exposed alignment marker.
- 12. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 6, wherein:
said step (f) facilitates testing for mask misalignment as part of the monitoring operations of said fabrication process by using said exposed alignment marker.
- 13. A method for producing wafer alignment accuracy in a semiconductor fabrication process after undergoing a dual field oxide semiconductor fabrication process, said method comprising the steps of:
(a) providing a first photomask member having mask portions for forming a plurality of first field oxide regions on a first region of a semiconductor substrate, said first mask member also having a mask portion for forming an alignment marker; (b) providing a second photomask member having mask portions for forming a plurality of second field oxide regions on a second region of said semiconductor substrate, said second mask member also having mask portions delineated for covering any first field oxide regions and alignment marker formed by using said first photomask member; (c) forming said first field oxide regions and said alignment marker utilizing said first photomask member; (d) covering said formed first field oxide regions and said alignment marker with a photoresist material by utilizing said second photomask member; (e) forming said second said field oxide regions after utilizing said second photomask member; (f) facilitating wafer alignment accuracy by removing said photoresist material and exposing said alignment marker; and (g) aligning a semiconductor wafer comprising said semiconductor substrate by utilizing said exposed alignment marker on said semiconductor substrate for forming a memory semiconductor apparatus capable of performing block data erasure operations.
- 14. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 13, wherein:
said steps (c), (d) and (g) comprise utilizing a stepper wafer alignment means.
- 15. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 13, wherein:
said step (d) comprises covering said formed first field oxide regions and said alignment marker with a silicon nitride material having a thickness of 1700Å.
- 16. A method for producing wafer alignment accuracy in a semiconductor fabrication process as described in claim 13, wherein:
said step (c) comprises ) forming said first field oxide regions and said alignment marker with a silicon dioxide material having a thickness of 2000Å; and said step (e) comprises ) forming said second field oxide regions with a silicon dioxide material having a thickness of 4000Å.
RELATED APPLICATION(S)
[0001] This application is a divisional patent application of co-pending U.S. patent application Ser. No. 09/044,389, entitled “STEPPER ALIGNMENT MARK FORMATION WITH DUAL FIELD OXIDE PROCESS”, filed Mar. 18, 1998, by the same applicant.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09044389 |
Mar 1998 |
US |
Child |
09836064 |
Apr 2001 |
US |