This application is related to commonly assigned U.S. patent application Ser. No. 11/849,798, filed Sep. 4, 2007, and entitled “Strained Transistor with Optimized Drive Current and Method of Forming,” which application is incorporated herein by reference.
This invention relates generally to semiconductor devices, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to improving stresses in the MOS devices.
Reductions in the size and inherent features of semiconductor devices, for example, metal-oxide semiconductor (MOS) devices, have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the MOS device and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and a drain of a MOS device alters a resistance associated with the channel region, thereby affecting the performance of the MOS device. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the MOS device, which, assuming other parameters are maintained relatively constant, may allow for an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the MOS device.
To further enhance the performance of MOS devices, stresses may be introduced in the channel region of a MOS device to improve its carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction (channel length direction) and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in the channel length direction.
A commonly used method for applying compressive stresses to the channel regions of MOS devices is to form stressed contact etch stop layers (CESL), which apply stresses to the underlying MOS devices. Since the CESLs were existing components of MOS devices, the introduction of the stressed CESLs resulted in little, if any at all, extra manufacturing costs. For NMOS devices, the overlying CESLs need to have inherent tensile stresses, and apply tensile stresses to the channel regions. For PMOS devices, the overlying CESLs need to have inherent compressive stresses, and apply compressive stresses to the channel regions.
CESLs apply a same stress (either tensile or compressive) to the underlying MOS devices from all directions. However, a MOS device may prefer different types of stresses in different directions. For example, PMOS devices prefer compressive stresses in the channel length directions, and tensile stresses in the channel width directions. Therefore, the compressive stresses applied to the channel width directions of the PMOS devices actually degrade the performance of the PMOS devices. A new structure is provided by the present invention to address the customized stress requirements of the MOS devices.
In accordance with one aspect of the present invention, a semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.
In accordance with another aspect of the present invention, a semiconductor structure includes a semiconductor substrate; an active region in the semiconductor substrate; an isolation region in the semiconductor substrate and adjoining the active region; and a MOS device. The MOS device includes a gate electrode over the active region; and a source region and a drain region on opposing sides of the gate electrode, wherein the source and drain regions overlap portions of the active region. The semiconductor structure further includes a stressor layer over the active region and the isolation region; a stressor-free region encircled by the stressor layer and directly overlying the isolation region; and a first strain bar in the stressor-free region.
In accordance with yet another aspect of the present invention, a semiconductor structure includes a semiconductor substrate; an active region in the semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate and adjoining the active region; and a MOS device. The MOS device includes a gate electrode over the active region, and a source region and a drain region on opposing sides of the gate electrode, wherein the source and drain regions overlap portions of the active region. The semiconductor structure further includes a contact etch stop layer (CESL) over the active region and the STI region; a stressor-free region overlying the isolation region, wherein the stressor-free region is encircled by the CESL; a strain bar filling the stressor-free region; an inter-layer dielectric (ILD) over the CESL; and a contact plug in the ILD and contacting one of the source and drain regions.
In accordance with yet another aspect of the present invention, a method of forming a semiconductor structure includes providing a semiconductor substrate comprising an active region therein; providing an isolation region in the semiconductor substrate and adjoining the active region; and forming a MOS device. The step of forming the MOS device includes forming a gate electrode over the active region; and forming a source region and a drain region on opposing sides of the gate electrode. The method further includes forming a stressor layer over the active region and the isolation region; and forming a strain bar overlying the isolation region, wherein the strain bar is encircled by the stressor layer.
In accordance with yet another aspect of the present invention, a method of forming a semiconductor structure includes providing a semiconductor substrate including an active region therein; providing a STI region in the semiconductor substrate and adjoining the active region; and forming a MOS device. The step of forming the MOS device includes forming a gate electrode over the active region; and forming a source region and a drain region on opposing sides of the gate electrode. The method further includes forming a contact etch stop layer over the active region and the STI region; forming an opening in the CESL and directly overlying the STI region; and filling the opening to form a strain bar.
The advantageous features of the present invention include improved stresses applied to MOS devices, and hence improved performance of the MOS devices.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Novel stressor layers for applying stresses on metal-oxide-semiconductor (MOS) devices are presented. The manufacturing methods of the preferred embodiments are then discussed. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.
As is known in the art, PMOS devices prefer compressive stresses. In this embodiment, stressor layer 114 has an inherent compressive stress. Accordingly, compressive stresses are applied to PMOS device 100 in both the X direction and the Y direction. The compressive stress (both the inherent stress in stressor layer 114 and the stress applied to PMOS device 100 by stressor layer 114) in the X direction (channel length direction) is beneficial for improving the drive current of PMOS device 100, and hence is preferably preserved. The compressive stress in the Y direction (channel width direction) is detrimental for the drive current of PMOS device 100, and hence is preferably eliminated. In the preferred embodiment, two strain bars 116 are formed over the STI region (hence are outside of the active region 110), and in stressor layer 114. Strain bars 116 are formed by etching stressor layer 114 to form openings, and fill the openings with a material different from the material of stressor layer 114. Accordingly, the regions occupied by strain bars 116 are also stressor-free regions. In an embodiment, strain bars 116 are filled with an inter-layer dielectric. In other embodiments, strain bars 116 are filled with a same material as contact plugs. In yet other embodiments, strain bars 116 are filled with a material having a neutral stress (no stress), or a stress type opposite to the stress type of stressor layer 114. In yet other embodiments, strain bars 116 may even be filled with a material having a stress of a same type as, but with a magnitude less than, the stress of stressor layer 114. The materials and the formation methods of strain bars 116 are discussed in detail in subsequent paragraphs. No strain bars are formed on the left and right sides of active region 110.
Strain bars 116 advantageously cut through the strain path in Y direction, and hence reduce the detrimental inherent compressive stress in Y direction. Accordingly, the detrimental compressive stress applied to PMOS device 100 is reduced. The distance Eny, which is between strain bars 116 and the respective edge of active region 110, is thus preferably small. In the preferred embodiment, distance Eny is less than about 1 μm, and more preferably less than about 0.3 μm. When distance Eny increases, stressor layer 114 still has the effect of reducing the stress in the Y direction. However, the amount of reduction is reduced. A greater width W2 of strain bars 116 is helpful in reducing the compressive stress in the Y direction. Preferably, width W2 is greater than about 1.0 μm. The length L2 of strain bars 116 is preferably greater than a path of a detrimental stress applied to a channel of the MOS device. In an exemplary embodiment, the length L2 of strain bars 116 is greater than the width of gate strip 112, and preferably greater than length L1. Further, the left ends and the right ends of strain bars 116 preferably extend beyond the respective left end and right end of active region 110.
PMOS device 100 may also be covered by a stressor layer having an inherent tensile stress, as is shown in
It is appreciated that due to geographical limitations, not all of the above-recited strain bars can be formed. This may occur, for example, if another MOS device occupies the location of a strain bar. The performance of the respective MOS devices, however, may still be improved with only part of the desirable strain bars formed, although in a reduced scale. For example, it is also possible to form only one strain bar in each of the structures shown in
In
In the above-discussed embodiments, in the directions wherein strain bars are not formed, the stressor layers preferably extend far to strengthen the desirable stresses. For example, distances Dx and Dy (refer to
In dual-stressor schemes, a compressive stressor layer is preferably formed over PMOS devices, and a tensile stressor layer is preferably formed over NMOS devices. Accordingly, the respective embodiments may be obtained by combining
It is realized that although strain bars are shown as rectangular bars in
Although
Strain bars 116 and 216 may be designed using logic operations, which may include layout modifications to graphic data system (GDS) files of the masks. For example, in the logic operations, MOS devices and the overlying CESL masks are first found, and the directions of the detrimental stresses applied by the CESL layers are determined. The appropriate locations and sizes of the strain bars are then determined, and the patterns of the strain bars are added to the masks. Alternatively, strain bars may be manually added. Preferably, the strain bars are formed directly over STI regions or field oxide regions, not directly over active regions. In alternative embodiments, the strain bars can also be formed directly over active regions.
By using the embodiments of the present invention, the detrimental stresses applied by the stressor layers are minimized, while the beneficial stresses provided by the same stressor layers are preserved. The performance of the MOS devices is thus improved. The embodiments of the present invention require minimal extra steps and masks, if at all, and thus the manufacturing cost is not substantially increased.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
This application is a continuation of U.S. patent application Ser. No. 12/048,135, entitled “Strain Bars in Stressed Layers of MOS Devices,” filed on Mar. 13, 2008, which application is incorporated herein by reference.
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Number | Date | Country | |
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20110195554 A1 | Aug 2011 | US |
Number | Date | Country | |
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Parent | 12048135 | Mar 2008 | US |
Child | 13089765 | US |